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Nico Coesel wrote: >>I thought xc9536 *is* PC44? >> >> >> >I don't know if this device has luts/flipflops like the Virtex/Spartan >which can hold a 16 bit shift register in one cell. If yes, a divide >by up to 16 element can be put into one cell. Dividing 1MHz downto 1 >Hz takes 5 cascaded shift registers. > > > The 95xx is a CPLD, not an FPGA. A MUCH smaller device, with VERY limited resources. Great as a very simple bus controller, peripheral decoder, or other simple piece of logic. Equivalent to maybe 100 gates, depending a lot on how you define a "gate". It is NOTHING like a Virtex, or even Spartan, except for the logo on the package. If you know what a "PLD" is, this is a bigger one, but only bigger by a small factor. JonArticle: 115026
Jan Panteltje <pNaonStpealmtje@yahoo.com> wrote: > Oh and it says it only works on 32 bit processors, the Athlon is out? Older athlons are still 32-bit, perhaps you remember ;-) Linux hertz 2.6.18.2-34-default #1 SMP Mon Nov 27 11:46:27 UTC 2006\ i686 athlon i386 GNU/Linux -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 115027
Jan Panteltje <pNaonStpealmtje@yahoo.com> wrote: > ... > Installs fine on a 360 MB memory Linux Debian machine here. > Are you sure swap was enabled? > man swapon? Yes, other programs do use swap. -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 115028
> Hi All, > > I was wondering if its possible to stream data at 480Mbps from a PC to > a USB 2.0 port on a FPGA development board and send the data out of a > SMA port on the board. The XUPV2P board has an onboard USB 2.0 and SMA > ports. Can this board be used for this application? > > Thanks, > Billu It's possible, but transfer rate depends from USB chipset.Article: 115029
Does anyone have experience or know the best solution to get Linux on Virtex 4? I heard something about MicroBlaze as a softcore processor.Article: 115030
Any ideas/pointers on how i can get started on a setup like this. So, the USB 2.0 on the XUPV2P might not be able to support 480Mbps. What USB chipset can I use to get the maximum transfer rate, and how would I interface the chipset w/ the PC/FPGA? - Thx On Jan 29, 4:29 pm, g.bernoc...@gmail.com wrote: > > Hi All, > > > I was wondering if its possible to stream data at 480Mbps from a PC to > > a USB 2.0 port on a FPGA development board and send the data out of a > > SMA port on the board. The XUPV2P board has an onboard USB 2.0 and SMA > > ports. Can this board be used for this application? > > > Thanks, > > BilluIt's possible, but transfer rate depends from USB chipset.Article: 115031
Phil, The easiest way to change the distrubuted or block ram INIT values is to edit the .ncd file in FPGA Editor. You can then regenerate a new .bit file without running through the entire implemenation flow. If you are unfamiliar with the .bit binary format or the .rbt ASCII format, I would not recommned you attempt to alter these in an attemt top change the ROM contents. -David "Phil" <mountaineering@web.de> wrote in message news:eea1c25.-1@webx.sUN8CHnE... > Hi, > > I would like to edit ROM contents in Virtex-4 .bit file (in order to avoid > re-synthesis/P&R). Is there any information available how to do this? > Already 'googled' the web and searched Xilinx' web page. So far no > success. Any suggestion welcome! Thanks. > > Thanks, PhilArticle: 115032
Hi Lancer, Lancer wrote: > Ok, many thanks, in XPS I've set main memory on SRAM_256Kx32, main > memory bank on 0, and flash memory on none (I'm using spartan 3 > XC3S1000). Is it correct? 1M of SRAM won't be sufficient for a simple kernel bringup. It can be done if you execute the kernel from flash and other little tricks, but I wouldn't recommend it for a first attempt. But otherwise, in principle your settings sound correct. > Flash memory should be none? XC3S1000 has XCF04S (4 Mbit) > configuration PROM. But I'm unable to set it in Software Platform > Settings... That's correct, it is intended for access to conventional parallel flash on the board, accessed via an opb_emc memory controller. > Although this, now XPS has generated auto-config.in, I've set it in > UNIX format, and put it in uclinux-auto folder. > Make dep ends with no error, but make ends with /fs/binfmt_flat.c > error in function decompress_exec... > I don't know why... > Do you know what kind of problem is this? If you post the error output from the compiler I might be able to help. I suggest you purchase one of the S3E-50 or -160 starter kits to get a platform that will happily run embedded Linux on the MicroBlaze. These boards have plenty of memory and were more or less designed with MicroBlaze/Linux in mind. Also, I suggest you subscribe to the microblaze-uclinux mailing list - there's a greater concentration of people able to assist there than here on comp.arch.fpga. Details here: http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux/Mailing_List Regards, JohnArticle: 115033
Hello Bill, Bill wrote: > Does anyone have experience or know the best solution to get Linux on Virtex 4? I heard something about MicroBlaze as a softcore processor. You can put a MicroBlaze on any Virtex 4 family FPGA, and as long as you have sufficient external memory on the board you can run Linux on it. Alternatively you can use a V4-FX chip with embedded PPC processors, and run PPC Linux on that (again subject to sufficient external memory). See http://www.petalogix.com and http://developer.petalogix.com for commercially supported offerings of Linux on MicroBlaze. Alternatively, subscribe to the microblaze-uclinux mailing list via http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux/Mailing_List/ Regards, JohnArticle: 115034
On Jan 29, 2:10 am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> wrote: > On 28 Jan 2007 15:39:20 -0800, "Weng Tianxiang" > > <wtx...@gmail.com> wrote: > >I want a global error signal to indicate the situation and I am not > >interested in complex design and all FIFO will be called using one > >simple module. > > >The global error signal applies not only to FIFOs, but also to any > >module if there is an error situation happening and it will indicate: > >Hi, it is error here in this clock !!! Using this signal will greatly > >reduce error debugging time also.Weng, > > If this is for simulation only, then you can use global signals. > > We have, in the past, suggested using an array of global > signals, one for each instance that you are debugging. You can > then attach a generic to each instance, and use it to determine > which signal is driven by that instance: > > package DEBUG_SUPPORT is > signal s: std_logic_vector(1 to 100); > end package DEBUG_SUPPORT; > > use work.DEBUG_SUPPORT; > entity DEBUG_ME is > generic (DEBUG_ID: natural := 0); > port (....); > end; > architecture TRACEABLE of DEBUG_ME is > -- Internal signal that reflects the error condition > signal HIGH_WHEN_ERROR: std_logic; > begin > ... > ... all your other stuff > ... > DEBUG_TRACING: if DEBUG_ID > 0 generate > DEBUG_SUPPORT.s(DEBUG_ID) <= > '1' when HIGH_WHEN_ERROR = '1' > else '0'; > end generate; > end; > > However, that's a little messy because you must now use a > complicated hierarchical configuration to assign the right > generic value to each instance. An alternative possibility > is to use a resolved signal for just one global debug signal. > I don't have time to sketch that out now, but if the generics > method doesn't work for you, reply to this and I'll try to post > an example in the next day or two. > -- > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated. Hi Jonathan, Thank you for your help. I have used one of your post on how to generate random number such that I know your name very well. Actually I would like to suggest to add a VHDL language element to resolve the similar problem: how to set or reset a global signal without consideration of their assertion or deassertion time. Why VHDL requires that programmers be allowed to assert or deassert a signal only in one process is to keep their clock relationships without ambiguity: on which conditions it must first be asserted or deasserted and on what other conditions it must be deasserted or asserted and so on. But in reality, there are times, for example, in global error reporting mechanism, the timing to assert or deassert don't matters. It will be very convenient for VHDL to have a global signal type a signal of which can be asserted or deasserted in any processes many times and without consideration of their timing relations. There are two global types of signals: assert first and deassert 2nd. If above mechanism exists, my design problem can be easily resolved: 1. In a package, declare a signal of that type(global type with assertion first and deassertion 2nd); 2. In any process, code can be written to assert the signal or deassert the signal with adding of package; 3. Compiler is responsible to collect all assert conditions and all deassertion conditions, then generate equations that first assert the signal and then deasser the signal. The final equation is as follows: if(all assertion conditions are ORed here) then the-first-assert-2nd-deassert-global-signal <= '1'; elsif(all deassertion conditions are ORed here) then the-first-assert-2nd-deassert-global-signal <= '0'; end if; This type of definitions will not add any harms to VHDL, but simplify programming in some situations dramatically. I don't know if the similar definition exists in current VHDL. Thank you. WengArticle: 115035
Thanks. And do you know if either will support USB 2.0? Would I just a host controller hardware?Article: 115036
Thanks for the advice...unfortunately the upgrade did not do the trick for me :( Ian On Jan 29, 3:13 pm, jesse lackey <j...@celestialaudio.com> wrote: > Hello, I had something similar happening (am using spartan II as well), > inexplicable, and it just stopped being a problem after upgrading (from > 8.2) to 9.1. I'm a newbie so the hows and whys of what is going on I > don't know. Maybe upgrade if you haven't already? > > Good luck! > Jesse > > idp2 wrote: > > Hi, > > > I'm programming on a Spartan-II in ISE. I have a few questions about > > the clk signals and .ucf files. > > > I have assigned my two clock signals PCI_CLK and DHSM_CLK to GCLKBUF0 > > and GCLKBUF1 respectively. However, when I compile it gives an error > > that PCI_RST should be assigned to a GCLK. Is this happening because > > a lot of logic is dependent on the RST? Also when I look at the clock > > report in Xilinx I see: > > > +---------------------+--------------+------+------+------------ > > +-------------+ > > | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max > > Delay(ns)| > > +---------------------+--------------+------+------+------------ > > +-------------+ > > | DHSM_CLK_BUFGP | GCLKBUF0| No | 544 | 0.338 | > > 0.472 | > > +---------------------+--------------+------+------+------------ > > +-------------+ > > | DHSM_RST_BUFGP | GCLKBUF3| No | 231 | 0.091 | > > 0.523 | > > +---------------------+--------------+------+------+------------ > > +-------------+ > > | PCI_CLK_BUFGP | GCLKBUF1| No | 204 | 0.353 | > > 0.487 | > > +---------------------+--------------+------+------+------------ > > +-------------+ > > | wf_data_in_flag | GCLKBUF2| No | 12 | 0.077 | > > 0.506 | > > +---------------------+--------------+------+------+------------ > > +-------------+ > > | d1/c1/mean8_stored | Local| | 2 | 0.000 | > > 0.908 | > > +---------------------+--------------+------+------+------------ > > +-------------+ > > | d1/c1/rng_stored | Local| | 2 | 0.000 | > > 0.728 | > > +---------------------+--------------+------+------+------------ > > +-------------+ > > | d1/c1/_not0004 | Local| | 5 | 0.000 | > > 2.659 | > > +---------------------+--------------+------+------+------------ > > +-------------+ > > | d1/c1/off_stored | Local| | 2 | 0.000 | > > 0.728 | > > +---------------------+--------------+------+------+------------ > > +-------------+ > > > but off_stored, rng_stored, mean8_stored, and wf_data_in_flag are just > > wires in my design that are intended as flags. Where does _not0004 > > come from and why is it assuming that all of these things are clocks?? > > > Thanks, > > IanArticle: 115037
On Jan 29, 7:50 am, "wallge" <wal...@gmail.com> wrote: > Are you saying that I don't need to activate/precharge the bank > when switching to another? > I am kind of unclear on this. When do activate and precharge commands > need to be issued? I thought when switching to a new row or bank you > had > to precharge (close) the previously active one, then activate the new > row/bank before > actually reading from or writing to it. Where am I going wrong here? Each bank is closed or open on a given row. As long as your accesses go to an already open row, you needn't precharge. Beware though you must close the bank after tRAS MAX ~= 70 us. AFAICT, ppl here have been suggesting data layout schemes what will increase your likelyhood of hitting an open row. > Also to the notion that I don't need to refresh since I am doing video > buffering: I am actually buffering multiple frames of video and then > reading > out several frames later. In other words, there may be a significant > fraction > of a second (say 1/8~1/4 sec) of delay between writing data into a > particular page of memory and actually reading it back out. > Is this too much time to expect my pixel data to still be valid > without refreshing? Yes that too much. tREFI (Average periodic refresh interval) is ~ 7 us. TommyArticle: 115038
On 29 Jan 2007 14:00:17 -0800, billu wrote: > > >Any ideas/pointers on how i can get started on a setup like this. So, >the USB 2.0 on the XUPV2P might not be able to support 480Mbps. What >USB chipset can I use to get the maximum transfer rate, and how would >I interface the chipset w/ the PC/FPGA? > >- Thx > >On Jan 29, 4:29 pm, g.bernoc...@gmail.com wrote: >> > Hi All, >> >> > I was wondering if its possible to stream data at 480Mbps from a PC to >> > a USB 2.0 port on a FPGA development board and send the data out of a >> > SMA port on the board. The XUPV2P board has an onboard USB 2.0 and SMA >> > ports. Can this board be used for this application? >> >> > Thanks, >> > BilluIt's possible, but transfer rate depends from USB chipset. > I would look at the Xilinx ML403 eval board. I don't remember the speed of the USB but it does have ethernet 10/100/1000 trimode and a a Vertex 4 (and a bunch of other I/O's.) It runs about $500 US The product brief doe not say what speed the 3 USB ports run at. Here is the link. http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?sGloba lNavPick=PRODUCTS&sSecondaryNavPick=Design+Tools&category=&iLanguageID=1&key=H W-V4-ML403-USAArticle: 115039
On Mon, 29 Jan 2007 13:32:22 -0800, Bill wrote: > > >Does anyone have experience or know the best solution to get Linux on Virtex 4? I heard something about MicroBlaze as a softcore processor. I have seen it running on their ML403 eval board (included in the package) I think they are using the PPC 405 hard processor. http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?sGloba lNavPick=PRODUCTS&sSecondaryNavPick=Design+Tools&category=&iLanguageID=1&key=H W-V4-ML403-USAArticle: 115040
Jan Panteltje <pNaonStpealmtje@yahoo.com> writes: > Oh and it says it only works on 32 bit processors, the Athlon is out? If you run WebPACK on a 64-bit Linux system, the installer will complain and tell you how to run the 32-bit installer (buried in a bin directory). That will run fine (at least on Fedora Core 6). Once it's installed, there's one further hurdle. The settings.sh file (or the .csh equivalent) use the output of a "uname -m" command to decide whether the host is 32-bit or 64-bit, and set the PLATFORM environment variable appropriately. Unfortunately since WebPACK only comes in 32-bit, it gets this wrong. But if you replace the conditional in that script that sets PLATFORM with simply "PLATFORM=lin", then it works fine. EricArticle: 115041
> > Also to the notion that I don't need to refresh since I am doing video > > buffering: I am actually buffering multiple frames of video and then > > reading > > out several frames later. In other words, there may be a significant > > fraction > > of a second (say 1/8~1/4 sec) of delay between writing data into a > > particular page of memory and actually reading it back out. > > Is this too much time to expect my pixel data to still be valid > > without refreshing?Yes that too much. tREFI (Average periodic refresh interval) is ~ 7 > us. Let me try that again. Quoting from Micron's SDRAM (SDR, not DDR) data sheet: "The addressing is generated by the internal refresh controller. This makes the address bits "Don't Care" during an AUTO REFRESH command. The 64Mb SDRAM requires 4,096 AUTO REFRESH cycles every 64ms (EF), regardless of width option." Which suggests that for this SDR SDRAM, a frame rate of 15 Hz or higher is enough to keep all displayed pixels refreshed. DDR SDRAM is probably very similar. Your 1/8 ~ 1/4 s is much too slow. TommyArticle: 115042
Hi, Thanks for your help. I have checked the XAPP224 before, from Xilinx=20 AN documents. It is good and helpful, but not enough. Our company has=20 developed IP to sample data from high speed data rate, now my problem=20 is to verify it with 300MHz clock -- the problem focus on synthesis=20 and P&R. On 1=D4=C229=C8=D5, =CF=C2=CE=E76=CA=B106=B7=D6, "Symon" <symon_bre...@hotm= ail.com> wrote: > "skyworld" <chenyong20...@gmail.com> wrote in message >news:1170036313.13= 3462.61950@v33g2000cwv.googlegroups.com... > > > Hi, > > My design is like this: the data is a serial data stream with data > > rate at 312MHz. The sampling circuitry works at 312MHz also, but there > > are four clocks to sample the data; each clock works at 312MHz, with > > equal spaced phase shift, i.e., 312MHz with 0 degree, 312MHz with 90 > > degree, 312MHz with 180 degree and 312MHz with 270 degree. A logic > > cell will be used to detect the transition between these four clocks > > and determines which clock will be used to sample the data.Well, I reco= mmend using Google before reinventing the wheel. XAPP224. > :-) > HTH, Syms.Article: 115043
On 2007-01-29, idp2 <ian.peikon@gmail.com> wrote: > > I have assigned my two clock signals PCI_CLK and DHSM_CLK to GCLKBUF0 > and GCLKBUF1 respectively. However, when I compile it gives an error > that PCI_RST should be assigned to a GCLK. I'm guessing that your HDL is not matching a standard sync or async reset flipflop and so RST ends up looking like a clk. For example, if you say: always @(posedge rst) foo <= bar; (maybe foo latches a config strapping pin 'bar') then rst is going to be treated as a clock. -- Ben Jackson AD7GD <ben@ben.com> http://www.ben.com/Article: 115044
In article <1170108017.266330.67340@s48g2000cws.googlegroups.com>,
"billu" <bkamakot@gmail.com> writes:
|> Any ideas/pointers on how i can get started on a setup like this. So,
|> the USB 2.0 on the XUPV2P might not be able to support 480Mbps. What
|> USB chipset can I use to get the maximum transfer rate, and how would
|> I interface the chipset w/ the PC/FPGA?
You won't get 480Mbs, regardless of the USB chip. 320 to 400 is the limit, it's
very fragile and requires a lot of "care" on the PC-side. For a start have a
look at the EZUSB2-chips made by Cypress. They have an easy interface bus for
such transfers.
If you want reliable transfers for longer periods over USB: Forget it, you have
been warned...
--
Georg Acher, acher@in.tum.de
http://www.lrr.in.tum.de/~acher
"Oh no, not again !" The bowl of petunias
Article: 115045motty wrote: > You are trying to use both edges of the clock AND use the clock as > data. Let's focus on the first problem. The only flip flops in the > FPGA that can run on both edges of the clock are found in the IO > tiles. And even then, two flip flops are used--one with an inverted > copy of the clock. This is a real problem. > The second problem is that you are using the signal 'clk' as both the > clock and D input of the FF. This is no good. Imagine that both > signals arrive at the FF at the exact same time (and they pretty much > will...even in the real world worst case). You will certainly break > setup time for the flip flop and nothing will work. I remember 30 years ago finding that the 74LS74 has 0ns hold time, so that one can change the input at the clock edge. Among others, this allows one to make a T-FF connecting Qbar to D. As I remember, the 7474 (without LS) didn't have that feature. I thought that Xilinx logic was supposed to have 0ns hold time, though one would have to be careful with the routing. -- glenArticle: 115046
On 2007-01-29, Phil <mountaineering@web.de> wrote: > Hi, > > I would like to edit ROM contents in Virtex-4 .bit file (in order to avoid re-synthesis/P&R). Is there any information available how to do this? Already 'googled' the web and searched Xilinx' web page. So far no success. Any suggestion welcome! Thanks. Look for documentation on the data2mem tool. It does exactly what you want. (I assume that you are using BlockRAMs for your ROM now.) /AndreasArticle: 115047
canest wrote: (snip) > this also seemed to work, but with a lot of warnings along the way > module a2(clka,clkb); > input clka; > output clkb; > reg clkb; > always @(clka) > begin > clkb= !clkb; > end > endmodule Traditionally that should be either (posedge clka) or (negedge clka). > This will half the frequency, I suppose I cannot change clkb=!clkb to > clkb=clka due to the setup time you mentioned. If I understand the simulation, it should do the always block on either transition, so you don't have a divide by two. Again, I don't believe it will synthesize a dual edge FF. -- glenArticle: 115048
On 2007-01-29, billu <bkamakot@gmail.com> wrote: > Hi All, > > I was wondering if its possible to stream data at 480Mbps from a PC to > a USB 2.0 port on a FPGA development board and send the data out of a > SMA port on the board. The XUPV2P board has an onboard USB 2.0 and SMA > ports. Can this board be used for this application? The USB2 port on the XUPV2P board is only designed as a USB programming cable replacement for the purpose of configuring the FPGA. It is actually possible to work around this (look for the xup programming tool), but I guess it will be a lot of work to actually get it working on the XUPV2P board. /AndreasArticle: 115049
Thx for everyones replies. The reason we are looking into FPGA based solutions is b/c we would preferably like a SMA output (since our modules have a SMA interface). The Cypress EZUSB2 output interface is convenient (not fast enough), but its not compatible with our RF module. Assuming we got a board like ML403, how can we go about implementing this application? On Jan 29, 9:10 pm, a...@in.tum.de (Georg Acher) wrote: > In article <1170108017.266330.67...@s48g2000cws.googlegroups.com>, "billu" <bkama...@gmail.com> writes:|> Any ideas/pointers on how i can get started on a setup like this. So, > |> the USB 2.0 on the XUPV2P might not be able to support 480Mbps. What > |> USB chipset can I use to get the maximum transfer rate, and how would > |> I interface the chipset w/ the PC/FPGA? > > You won't get 480Mbs, regardless of the USB chip. 320 to 400 is the limit, it's > very fragile and requires a lot of "care" on the PC-side. For a start have a > look at the EZUSB2-chips made by Cypress. They have an easy interface bus for > such transfers. > > If you want reliable transfers for longer periods over USB: Forget it, you have > been warned... > > -- > Georg Acher, a...@in.tum.de > http://www.lrr.in.tum.de/~acher > "Oh no, not again !" The bowl of petunias
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