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On 28 Jan, 01:19, <canest> wrote: > I want to send off a pcb board design for a xiling xc9536 so that I > can experiment with some simple verilog programs. I > want the most minimal design, so I need one xiling > plcc socket, one 0.1uF bypass capacitor, one jtag > socket, and one led and resistor so that I can do some > basic apps that play with the led. Will this work, do I > need anything else? Here is a simple design of mine: http://www.geocities.com/leon_heller/pld_starter.html LeonArticle: 114976
"Weng Tianxiang" <wtxwtx@gmail.com> wrote in message news:1170012704.301604.246980@q2g2000cwa.googlegroups.com... > Hi, > How to make an internal signal embedded deep in hierarchy to a gloal > output signal? > > I have an internal signal embedded deep in hierarchy showing there is > an error. I would like to see it at the top of hierarchy. > > How can I do it in VHDL? > > Do I have to do the foolish steps to transfer it one module to another > until the top level? > > Weng > If you're bringing the signal out only for debug purposes first check out debug tools for the device that you're using, they may give you a way to pull out nodes from within the design out to physical pins for connection to a logic analyzer or scope. After you specify the signals you want to bring out you re-route and the signals are there for you. Once over the initial learning curve of how to do it in the first place, bringing out other signals for debug will go relatively quickly and will generally be the most efficient way of doing this in the future. If the device software you're using does not have any such capability then you have to either propogate the signal up to the top level by adding the signal(s) as entity ports all the way to the top level (bit of a pain if you're down more than a level or two) or try defining a signal in a package where you assign the signal inside wherever it is you want to pick up the signal and then assign that as an output at the top level (not all tools support this, but support for this is improving...it's definitely less coding if it works). Sample: package pkg_xyz is signal My_Debug_Signal: std_ulogic; end package pkg_xyz; Inside the architecture for where you have the signal that you'd like to monitor... work.pkg_xyz.My_Debug_Signal <= The_Internal_Signal_I_Want_To_Monitor; At the top level... Debug_Output <= work.pkg_xyz.My_Debug_Signal; Kevin JenningsArticle: 114977
Shenli wrote: > Hi all, > > I am reading "Coding Guidelines for Datapath Synthesis" from Synopsys. > > It says "The most important technique to improve the performance of a > datapath is to avoid expensive carry-propagations and to make use of > redundant representations instead (like carry-save or partial-product) > wherever possible." > > 1. Is there any article talk about what's "carry-propagation" and how > to avoid use it? > 2. What's "redundant representations" mean? > > Please recommend some readings about it, thanks in advance! > > Best regards, > Davy > That really is targeted to ASIC implementations. The performance hit for carry propagation in FPGAs that have a "fast carry chain" is mitigated by the much faster carry propagation on these special dedicated circuits. With that in mind, if you are designing on an FPGA with fast carry logic, then this admonishment doesn't apply. Redundant representations refer to alternative number system representations that avoid the propagation of a carry signal across the width of a data word as a result of arithmetic operations. They are not,however, without their own hardships.Article: 114978
On Jan 28, 1:31 pm, "KJ" <kkjenni...@sbcglobal.net> wrote: > "Weng Tianxiang" <wtx...@gmail.com> wrote in messagenews:1170012704.301604.246980@q2g2000cwa.googlegroups.com...> Hi, > > How to make an internal signal embedded deep in hierarchy to a gloal > > output signal? > > > I have an internal signal embedded deep in hierarchy showing there is > > an error. I would like to see it at the top of hierarchy. > > > How can I do it in VHDL? > > > Do I have to do the foolish steps to transfer it one module to another > > until the top level? > > > WengIf you're bringing the signal out only for debug purposes first check out > debug tools for the device that you're using, they may give you a way to > pull out nodes from within the design out to physical pins for connection to > a logic analyzer or scope. After you specify the signals you want to bring > out you re-route and the signals are there for you. Once over the initial > learning curve of how to do it in the first place, bringing out other > signals for debug will go relatively quickly and will generally be the most > efficient way of doing this in the future. > > If the device software you're using does not have any such capability then > you have to either propogate the signal up to the top level by adding the > signal(s) as entity ports all the way to the top level (bit of a pain if > you're down more than a level or two) or try defining a signal in a package > where you assign the signal inside wherever it is you want to pick up the > signal and then assign that as an output at the top level (not all tools > support this, but support for this is improving...it's definitely less > coding if it works). > > Sample: > > package pkg_xyz is > signal My_Debug_Signal: std_ulogic; > end package pkg_xyz; > > Inside the architecture for where you have the signal that you'd like to > monitor... > work.pkg_xyz.My_Debug_Signal <= The_Internal_Signal_I_Want_To_Monitor; > > At the top level... > Debug_Output <= work.pkg_xyz.My_Debug_Signal; > > Kevin Jennings Hi Kevin, Thank you for your advice. I don't think following way works, but if it worked, it would have been very nice. package pkg_xyz is signal My_Global_Error_Signal: std_ulogic; end package pkg_xyz; In an architecture: if() then My_Global_Error_Signal <= '1'; end if; Many components infer to the entity ---> cause multiple assignment??? I don't think this way works. It means: If a signal is declared in a package as a global signal, it can be assigned many times without any multiple assignment violations. WengArticle: 114979
canest wrote: > I want to send off a pcb board design for a xiling xc9536 so that I > can experiment with some simple verilog programs. I > want the most minimal design, so I need one xiling > plcc socket, one 0.1uF bypass capacitor, one jtag > socket, and one led and resistor so that I can do some > basic apps that play with the led. Will this work, do I > need anything else? > > Rather than making and then debugging your own board, go to the Xilinx website and look for the evaluation boards. Diligent sells one for $49.00 that has an xc9572 and a coolrunner on it along with power supply and a breadboard area and a few LEDs. They also sell one through xilinx that has one CPLD, plus a solderless breadboard, switches, 7 segment display and leds for $49-59. For those costs, especially if it is a one-off to get you up the learning curve, you can't beat the kits.Article: 114980
"Weng Tianxiang" <wtxwtx@gmail.com> wrote in message news:1170012704.301604.246980@q2g2000cwa.googlegroups.com... > Hi, > How to make an internal signal embedded deep in hierarchy to a gloal > output signal? > > I have an internal signal embedded deep in hierarchy showing there is > an error. I would like to see it at the top of hierarchy. > > How can I do it in VHDL? > > Do I have to do the foolish steps to transfer it one module to another > until the top level? > > Weng > If you're using Xilinx ISE, you can add a "probe" using the "FPGA Editor" to bring any internal signal out to a spare pin. This does not change the placement and routing of your design, so you can track down intermittent / elusive errors which might vanish if you re-synthesize.Article: 114981
You can minimize the work by routing a VHDL record instance from the bottom level to the top. Then you can just vary the record definition to include your debug signals. You may even have a suitable record defined for another purpose. -- TimArticle: 114982
> Rather than making and then debugging your own board, go to the Xilinx > website and look for the evaluation boards. Diligent sells one for > $49.00 that has an xc9572 and a coolrunner on it along with power supply > and a breadboard area and a few LEDs. They also sell one through xilinx > that has one CPLD, plus a solderless breadboard, switches, 7 segment > display and leds for $49-59. For those costs, especially if it is a Yes, and then they charge another $80 for sending it to the UK. > one-off to get you up the learning curve, you can't beat the kits.Article: 114983
I need urgent help. Perhaps it is just a simple problem, but I don't
know how to solve it. I try to design a simple CPLD project.
I designed a simple schematic using a flip flop ("fd", for instance)
and some logic gates and added some I/O markers.
In the following user constraint menu, when I try to assign pins, the
only pin names are C, D and Q and not the net names I assigned to the
I/O markers.
I am grateful for any ideas, thanks
Hans
Article: 114984
I need urgent help. Perhaps it is just a simple problem, but I don't
know how to solve it. I try to design a simple CPLD project.
I designed a simple schematic using a flip flop ("fd", for instance)
and some logic gates and added some I/O markers.
In the following user constraint menu, when I try to assign pins, the
only pin names are C, D and Q and not the net names I assigned to the
I/O markers.
I am grateful for any ideas, thanks
Hans
Article: 114985On Jan 28, 2:56 pm, "Andrew Holme" <and...@nospam.com> wrote: > "Weng Tianxiang" <wtx...@gmail.com> wrote in messagenews:1170012704.301604.246980@q2g2000cwa.googlegroups.com... > > > Hi, > > How to make an internal signal embedded deep in hierarchy to a gloal > > output signal? > > > I have an internal signal embedded deep in hierarchy showing there is > > an error. I would like to see it at the top of hierarchy. > > > How can I do it in VHDL? > > > Do I have to do the foolish steps to transfer it one module to another > > until the top level? > > > WengIf you're using Xilinx ISE, you can add a "probe" using the "FPGA Editor" to > bring any internal signal out to a spare pin. This does not change the > placement and routing of your design, so you can track down intermittent / > elusive errors which might vanish if you re-synthesize. Hi, I am not debugging my design, I am designing my design and want a global error signal to indicate there is an overflow or underflow of multiple FIFOs, no matter how many FIFOs are. If one of them meets the situation, it sets the global error signal. In a design, there may be 100 FIFOs. That is the problem source: I want a global error signal to indicate the situation and I am not interested in complex design and all FIFO will be called using one simple module. The global error signal applies not only to FIFOs, but also to any module if there is an error situation happening and it will indicate: Hi, it is error here in this clock !!! Using this signal will greatly reduce error debugging time also. Thank you. WengArticle: 114986
I receive the following error ERROR:Xst:899 - "a1.v", line 8: The logic for <clk1> does not match a known FF or Latch template. I use xilinx 4.2i, and the program is this module a1(clk,clk1); input clk; output clk1; reg clk1; //initial clk1=0; always @ (posedge clk or negedge clk) begin clk1 <= clk ; end endmodule What am I doing wrong?Article: 114987
Hi Lancer, Lancer wrote: >>Take a look at developer.petalogix.com - there are quick start guides, >>complete documentation, tutorials and all sort of things to get you going. > > > ...but petalogix provide petalinux documentations, isn't it? Yes - and PetaLinux is how we advise people to get started now. It includes Linux source tree, compiler tool chains, reference designs and helper scripts - basically all in one rather than getting bits and pieces from all over the place. >>One thing to note, Windows is not a supported environment for building >>Microblaze / uClinux systems. It may be one day, but for now you'll >>need a Linux box or virtual machine to build the embedded Linux software. > > > I'm using Slack 11 machine to build uClinux, and Win XP SP2 machine > with Xilinx tools to build Microblaze project. That should be fine - make sure you do a dos2unix conversion on the auto-config.in file when you copy it from Windows -> Linux. > When I begin a project, I specify the repository path > (edk_user_repository) that I've downloaded there: > http://www.petalogix.com/resources/downloads/uclinux-bsp (BSP uClinux > package) > Then I build my Microblaze (for my Spartan 3 XC3S1000) e then I specify > in "Software Platform Settings" the uClinux OS. > Then I launch the libgen, and always I obtain this error message: > > "ERROR:MDT - ERROR FROM TCL:- uclinux () - ERROR :: No MAIN_MEMORY > peripheral or > START/SIZE parameters specified > while executing A typical MSS OS section will look like this: BEGIN OS PARAMETER OS_NAME = uclinux PARAMETER OS_VER = 1.00.d PARAMETER PROC_INSTANCE = microblaze_0 PARAMETER stdout = RS232_Uart PARAMETER stdin = RS232_Uart PARAMETER LMB_MEMORY = ilmb_cntlr PARAMETER MAIN_MEMORY = DDR_SDRAM_32Mx64 PARAMETER main_memory_bank = 0 END You must substitute the instance name of your DDR/SDRAM controller into the "MAIN_MEMORY=" line, and similarly for the stdout/stdin selections. The error message you received suggests that you have not specified the MAIN_MEMORY paramter in your MSS file. You can use the XPS GUI to specifiy all of this - once you have chosen the uClinux BSP, then you move to the next tab to customise it. It will present options to you for setting the main_memory peripheral and so on. I hope this helps, Regards, JohnArticle: 114988
You are trying to use both edges of the clock AND use the clock as data. Let's focus on the first problem. The only flip flops in the FPGA that can run on both edges of the clock are found in the IO tiles. And even then, two flip flops are used--one with an inverted copy of the clock. The second problem is that you are using the signal 'clk' as both the clock and D input of the FF. This is no good. Imagine that both signals arrive at the FF at the exact same time (and they pretty much will...even in the real world worst case). You will certainly break setup time for the flip flop and nothing will work. Let's pretend that your code will work. What is its function? On the rising edge, the FF's Q output would equal the value of the rising edge, 1. On the negedge, the Q output of the FF would be 0. All you are doing is copying the input clock. It seems you may need to learn a little basic digital design before attempting to model things using Verilog. Also, it looks like you have the initial statement commented out. That is good, because it is not a good idea to use this statement for synthesis. Your synthesizer (XST) probably won't support it. I don't know if any do. If you want your logic to start at a known value, use a reset.Article: 114989
canest wrote: > I receive the following error > > ERROR:Xst:899 - "a1.v", line 8: The logic for <clk1> does not match a known > FF or Latch template. > > I use xilinx 4.2i, and the program is this > > module a1(clk,clk1); > input clk; > output clk1; > reg clk1; > //initial clk1=0; > always @ (posedge clk or negedge clk) > begin > clk1 <= clk ; > end > endmodule > > What am I doing wrong? The error message describes the problem. A logic synthesizer works by matching your HDL code to different templates until it finds a match. The typical verilog flip-flop template is: always @(posedge clk) b <= a; You have always @(posedge clk or negedge clk) begin clk1 <= clk ; end The synthesizer can't match this to any simple flip-flop template. There is a similar template, though: always @(posedge clk or negedge reset) if (!reset) b <= 1'b0; else b <= a; But you don't have the if statement, so you don't match that template either. My guess is that you are trying to instantiate a flip-flop that clocks on both edges. Xilinx doesn't have such a flip-flop in the fabric. Also, registering the clock signal isn't typically done. I haven't used 4.1i in a few years, so I don't know if it has language templates. In recent versions (including the free WebPacks), the GUI has language templates accessible from the EDIT menu. --- Joe Samson Pixel VelocityArticle: 114990
hgs wrote: > I need urgent help. Perhaps it is just a simple problem, but I don't > know how to solve it. You might begin by telling us what software you are using. --- Joe Samson Pixel VelocityArticle: 114991
Hi, My design is like this: the data is a serial data stream with data=20 rate at 312MHz. The sampling circuitry works at 312MHz also, but there=20 are four clocks to sample the data; each clock works at 312MHz, with=20 equal spaced phase shift, i.e., 312MHz with 0 degree, 312MHz with 90=20 degree, 312MHz with 180 degree and 312MHz with 270 degree. A logic=20 cell will be used to detect the transition between these four clocks=20 and determines which clock will be used to sample the data. The rule=20 is to choose the clock which is at the center of "sampling window".=20 This IP has been tested with a Spartan FPGA and works at 156MHz. Now=20 I need to migrate this to Virtex 4 and works at 312MHz. The problem I=20 met is that there is timing violation as mentioned above. I'm not=20 familiar to multi-clock designs, and I'm not familiar to set these=20 constraints with Xilinx tools, so I came here to ask for some help.=20 Xilinx's docs just give some descriptions on those aspect, but it is=20 not enough for guys like me to know how to set these constraints and=20 pass the timing. Thanks for your help and reply. skyworld On 1=D4=C228=C8=D5, =C9=CF=CE=E710=CA=B143=B7=D6, "motty" <mottobla...@yaho= o=2Ecom> wrote: > Are you still trying to sample data with 4 phase offset clocks? At > the speed you are talking about, you are effectively making paths that > need to run at a little over 1 GHz. Look at the jitter specs for the > DCM clocks. That number is a pretty big portion of a ~800ps period. > You may want to consider another method of doing what you need.Article: 114992
> You are trying to use both edges of the clock AND use the clock as > data. Let's focus on the first problem. The only flip flops in the > FPGA that can run on both edges of the clock are found in the IO > tiles. And even then, two flip flops are used--one with an inverted > copy of the clock. > > The second problem is that you are using the signal 'clk' as both the > clock and D input of the FF. This is no good. Imagine that both > signals arrive at the FF at the exact same time (and they pretty much > will...even in the real world worst case). You will certainly break > setup time for the flip flop and nothing will work. ok, I see your point. What I wanted is to simply mimic the clock, and simulate it to see if I can see any time lag due to the clock travelling through the internals of the xilinx. I have now changed it to this, and it worked: module a2(clka,clkb); input clka; output clkb; wire clkb; assign clkb = clka ; endmodule this also seemed to work, but with a lot of warnings along the way module a2(clka,clkb); input clka; output clkb; reg clkb; always @(clka) begin clkb= !clkb; end endmodule This will half the frequency, I suppose I cannot change clkb=!clkb to clkb=clka due to the setup time you mentioned. BTW, do you know what exactly is the purpose of the verilog test bench waveform simulation? There are yellow spikes on the output screen, and when I click on them the clk1 signal can be changed from o to 1 etc. > > Let's pretend that your code will work. What is its function? On the > rising edge, the FF's Q output would equal the value of the rising > edge, 1. On the negedge, the Q output of the FF would be 0. All you > are doing is copying the input clock. > > It seems you may need to learn a little basic digital design before > attempting to model things using Verilog. You mean digital design in the context of verilog, I agree. Although I think I got the idea now pritty much, but yes, to understand the internals of the cpld will definately be beneficial. > > Also, it looks like you have the initial statement commented out. > That is good, because it is not a good idea to use this statement for > synthesis. Your synthesizer (XST) probably won't support it. I don't > know if any do. If you want your logic to start at a known value, use > a reset. > >Article: 114993
On 2007-01-28, <canest> <> wrote: >> They will be *very* simple. If you want PC44, get at least a xc9572! > > I thought xc9536 *is* PC44? They both are available in PC44, with compatible pinouts. The '72 has twice as much internal logic to play with. > Do I need three bypass caps, or just one? Is 0.1uF ok or Yes. As close to the power pins as possible. > One microcell per register bit - 1 MHz = 20 bits = 2 ^ 20 Yes. So if you want to see logic happen in "human time", supply the chip with a slow clock that you can see the output. As for those who say not to do it yourself, it depends on what you are trying to learn. If you want to play with Verilog or VHDL, you can do it in a simulator. If you want to see it in real hardware, buy a board. If you want to learn how to build the board, build the board! I built something just like you describe several years ago and learned quite a bit. Not at all what I expected to learn, though! -- Ben Jackson AD7GD <ben@ben.com> http://www.ben.com/Article: 114994
HI Anil, If you are using 9.1i XST, the XST user guide examples of how to infer byte enables. This is only supported in XST starting in ISE 9.1i. The older versions do not support this. HTH Duth On Jan 26, 5:59 pm, "anil" <anil.janumpa...@gmail.com> wrote: > Hello all, > > does any one have an idea about the related question? what is > the type of code written to infer the option mentioned. > > Regards, > AnilArticle: 114995
On 29 Jan., 00:20, "hgs" <hans-georg.sto...@meduniwien.ac.at> wrote:
> I need urgent help. Perhaps it is just a simple problem, but I don't
> know how to solve it. I try to design a simple CPLD project.
> I designed a simple schematic using a flip flop ("fd", for instance)
> and some logic gates and added some I/O markers.
> In the following user constraint menu, when I try to assign pins, the
> only pin names are C, D and Q and not the net names I assigned to the
> I/O markers.
> I am grateful for any ideas, thanks
> Hans
Sorry, I forgot to mention, I use WebPack 9.1 (with SP1) and also
tried WebPack 8.2 (with SP3)
Thanks
Article: 114996As far as I have seen defining global signals in packages and assigning them somewhere in your design is only OK for simulation tools. Rgds AndreArticle: 114997
Hi all, Right now I'm developing a board using virtex-II FPGA, and want to implement a function using the DCM to offer variable(dynamic) phase shifting. I use Xilinx ISE 8.2i, and ModelSim SE for development. As I setup the IP cores for DCM, everything looks fine in the PRP simulation, except that the PSDONE signal never goes high, which means everytime I trigger the PSEN signal to high (for exactly one period, as said in the User Guide), the DCM just doesn't take any action. I just wonder what is other things that I still need to do. If anybody who can address my problem, Thanks!~Article: 114998
Eric Smith <eric@brouhaha.com> writes: > I wrote: >> I do my editing in Emacs, but I despise vhdl-mode. I normally use >> the GUI for everything but editing. > > Martin Thompson <martin.j.thompson@trw.com> writes: >> Interesting - could you say any more about what makes vhdl-mode so >> bad? My experience has been more of people thinking Emacs sucks, but >> they wish their editor did all that vhdl-mode does! > > Completion/templates get in the way of my typing. I know what I want > to write, but if the editor starts inserting stuff for me, I have to > think about the typing much more, so it slows me way down. > Ahh, yes I can understand that - I had a similar problem except that when I started, I was very rusty at VHDL, so it helped. I'm now so used to the templates that inserting a new process becomes: proc<tab><s><type a name for process><clk>then type in s docunmmentation comment if I feel like it and prod enter a few times to get rid of any extraneous prompts. That sounds like a right palaver, but honest, it helps me :-) I wrote a new piece of code the other day and it compiled first time, because the templates and tab-completion of variables/signals meant my customarily inaccurate typing hadn't caused any syntactical problems. Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 114999
"wallge" <wallge@gmail.com> writes: > I am not sure what you mean by two pass approach. > The max (theoretical) bandwidth I have available to/from the SDRAM > is about > 16 bits * 100 Mhz = 1.6 Gbit/sec > > This is not an achievable estimate of course, even if I only did full > page > reads and writes, since there is overhead associated with each. I also > have to refresh periodically. > Don't forget that for video apps, you often don't need to refresh, as you are reading and writing the SDRAM rows in a regular fashion which means you can guarantee that each gets touched often enough. Indeed for some video applications, like output framebuffers, all you need to do is ensure that you read the row out for display soon enough after the write, which is often easy to achieve. Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.html
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