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btw, sorry for the "reply-all", I got used to mailing lists ...Article: 112476
Sylvain, Yes, a complex design is not well protected when it is in a machine readable format (such as something that is parsed by FPGA Editor). These techniques will not prevent their IP from being reverse engineered, it just makes it so it would take more time to do so. One can also prevent the tools from simulating the IP, which may also aid in preventing its miss-use. I do not know how the simulation is prevented, but I can ask if you wish. AustinArticle: 112477
Can you figure a way to functionally break up your design? The only huge "combinational" designs I've known of were either 1) incorrect or 2) part of a genetic algorithm development. Chances are that your design is significantly more complex than it needs to be. Rather than performing everything in one large equation, can you divide it up into functional parts that can give you your goal in several clocks rather than all at once? The idea is the first, most important part of your design. Implementation gets you toward reality. Ask yourself what the hardware can do and use that as a guideline for how to partition your design in functional pieces that can give you what you need over several clocks. Good luck. <olson_ord@yahoo.it> wrote in message news:1164230089.535186.91600@h54g2000cwb.googlegroups.com... > Hi, > This is the second time I am posting to this group within a week, but > I think that this necessitates another thread. (Through google groups > my original thread can be accessed at > http://groups.google.com/group/comp.arch.fpga/browse_frm/thread/6f620f38f06a19df?hl=en) > > My problem is that I am trying to synthesize gate level combinational > circuits that have a large number of signals. (I actually did not > realize how large it was till Thomas and Andreas explained it to me in > the previous thread.) My circuit probably uses around 40 K gates, but a > lot more signals. > > From the discussion in my previous thread, I realized that the > synthesis tools (I use XST) have/has problems with > (1) large number of signals > (2) large combinational paths > > I don't really mind the synthesis time - rather I am concerned that I > run out of memory. (I hit 4 GB - and I don't have the 64 bit version.) > > I would also like to mention that as far as the number of gates is > concerned, I am sure that my design would fit onto one FPGA, with a > utilization of less than 50%. (Using the xc2v6000-4.) > > Does anyone have an idea how I can get this to synthesize? Partial > Synthesis (i.e. synthesis of parts of my design separately) was > suggested to me in my previous post, but I could not figure out how to > do this in XST. (I can dump out the NGC files for different parts of my > design - but how do I combine them?) > > If long combinational paths are an issue, is there a way to break up a > long combinational path (i.e. add registers or latches etc.). I thought > about latches - but then deciding where to insert the latches is a big > question. (I don't mind compromising on timing if this is a factor of > 2, 3 or even 10, but I don't want this running into a factor of 100's > or 1000's.) > > Thanks to all those who may have some ideas. > O.O. >Article: 112478
spartanius@arcor.de wrote: > I am currently using the ISE 8.1 - you seem to use 8.2. Could this be > the explanation for the errors? > > Anyway, I installed the newest available version now, and still have no > success. rightclicking the *.ise opens the ISE, but I have no sources > and have to add them manually again like before. Using 8.1 can't be the explanation, because you have updated to 8.2. I can start the project with double click. > It seems to be a challenge to get a Xilinx Environment run. (?) Well, > when starting with Altera`s, 2 years ago, everything worked fine the > first run (eval board board, first project, quartus ide etc). Maybe someone from Xilinx can help? Looks like you can't have anything: With Quartus you have a nice and clean IDE (ok, sometimes switching to the programmer after synthesizing doesn't update to the last synthesized program and minor other bugs, but at least the GUI looks and feels more modern), but you can't trust the synthesizer until some service packs were released and with ISE webpack the backend may be more stable, but using the IDE is a nightmare sometimes. BTW: in German Windows, deleting "C:\Dokumente und Einstellungen\YourName\Lokale Einstellungen\Temp\xil*" may help. -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 112479
"John Fields" <jfields@austininstruments.com> wrote in message news:ooe9m2ld470u6rg7tqku3vfchh83960698@4ax.com... >>I once wrote an Eratosthenes' prime number sieve using the video display >>as >>an array memory (on a 4K machine). > How high did it go? to 9? You still count on your fingers?Article: 112480
I'm looking at the cost of serial configuration devices from Altera and am a little shocked at how expensive they are. Digi Key sells the EPCS4 for $13, which seems steep for 4Mbit of storage. A quick glance at Digi-Key's website suggests I can get an SPI-compatible PIC chip and a 4Mbit SPI FLASH memory for less than $4, which means I should be able to program the FPGA from the PIC for a third of the cost of Altera's solutoin. Before I go off and reinvent the wheel, does anyone know of a prepackaged solution for programming an Altera device (I'm using a Cyclone) with a microcontroller that I can just drop into my project? I'm sure I can't be the first person to do this. If anyone has a website describing a similar setup, I'd love to see it. Thanks, -NevoArticle: 112481
On Thu, 23 Nov 2006 03:01:47 GMT, "Nevo" <nevo_n@hotmail.com> wrote: >I'm looking at the cost of serial configuration devices from Altera and am a >little shocked at how expensive they are. Digi Key sells the EPCS4 for $13, >which seems steep for 4Mbit of storage. > >A quick glance at Digi-Key's website suggests I can get an SPI-compatible >PIC chip and a 4Mbit SPI FLASH memory for less than $4, which means I should >be able to program the FPGA from the PIC for a third of the cost of Altera's >solutoin. > >Before I go off and reinvent the wheel, does anyone know of a prepackaged >solution for programming an Altera device (I'm using a Cyclone) with a >microcontroller that I can just drop into my project? I'm sure I can't be >the first person to do this. If anyone has a website describing a similar >setup, I'd love to see it. Google is your friend (and above $500 as of today, alas I have none). Using a couple of the keywords in your posting leads one to this site http://vader.ece.ucsb.edu/digilab-fpga/ which I believe does what you need. Comes with schematics too.Article: 112482
Can anybody throw light on vqm editor 1)Back annotation on FPGA of quartus II 6.0.I am confused with that options .Import and export options 2)VQM file.Where this will be used for 3)How to import a hard macro in this file.like nmc file in xilinx. ISE Thanking youArticle: 112483
guybye@hotmail.com yazdi: > Hello i am quite new to EDK world... :). > I am using a microblaze which works on 90Mhz clk. In my design there is > an OPB also 90 Mhz. I would like to use the Exrnal Memory controler in > order to read data from a single Intel Strata flash (8 bits depth) 40 > Mhz. In the EMC pdf there is an example includes EMC and flash. The > example is not so clear- how do i synchronize the EMC(90 Mhz) with the > Flash (40Mhz)? How do I connect the data lines to the OPB i understand > there is a little endian, big endian proble? > > thanks in advance > > Guy Zur. Hello, You can configure the IP so can change speed. Right click on the IP name and Config IP from pop-up menu and System tab.Article: 112484
MM schrieb: > "Antti" <Antti.Lukats@xilant.com> wrote in message > news:1164200166.358021.84400@m73g2000cwd.googlegroups.com... > > > > BUG::: EDK 8.2 generates BMMs incompatible with ISE 8.2 > > when BRAM blocks are consecutive. > > if there is gap in address space then it all works. > > > > there is a workaround to manually fix the generated BMM files > > So they broke it in 8.2!!!! Are you talking about the AR 24296 for the fix? > This is as ugly as it can only get :( I can't beleive this.... > > /Mikhail ROTFL !!! yes, its AR24296 - but see its not a bug, its a FEATURE!!!! Quoting Xilinx: "..is a new feature in 8.2i that does not work well.." ========================================================== I can confirm, that this feature brakes everything in contigous memory blocks. well my workaround is simpler and doesnt require FPGA editor to be used, just wrap all memory blocks in its own ADDRESS_SPACE container and rerun ngdbuild this will update the BMM file properly, but this means that you cant do it from the GUI any more AnttiArticle: 112485
Hi all.
I'm using EDK 8.2.02i. ISE: 8.2.03i. Board: Spartan 3E Xilinx Starter Kit Rev.D
I'd like use C++ for my SW project but I have found problems...
1) Using namespace --------------- In my code application.h I have written:
namespace prova1{ int a=5; };
namespace prova2{ int a=10; int b=8; };
Then to make a test in my application.cc :
printf("prova1::a = %d \n", prova1::a); printf("prova2::a = %d \n", prova2::a); printf("prova2::b = %d \n", prova2::b);
So I expect to see in my terminal right values, but what really happen is:
prova1::a = 5 prova2::a = 5 prova2::b = 8
So system show and see only the first "a".
Moreover, and this is incredible, if in my makefile I compile using -0s optimization (size) then no error happen in linking. But if i DON'T USE ANY OPTIMIZATION this error occurs:
* *********************************************************************************** Creating target elf file... mb-g++ -Wl,-defsym -Wl,_TEXT_START_ADDR=0x22000C00 -o ./application.elf -Wall -g application.cc \ -I../microblaze_0/include/ -I../Libs/ \ -L../microblaze_0/lib/ -L../Libs/ -LD:\EDK/gnu/microblaze/nt/mi croblaze/lib -LD:\EDK/gnu/microblaze/nt/include/C++/3.4.1/ -lcommon -lstdc++ /cygdrive/c/DOCUME~1/alettoal/LOCALS~1/Temp/cc31lsQU.s: Assembler messages: /cygdrive/c/DOCUME~1/alettoal/LOCALS~1/Temp/cc31lsQU.s:102: Fatal error: Symbol a already defined. make: *** [application.elf] Error 1
* ***********************************************************************************
2) Using simple class ------------------
In my application.h :
class Cliente { public: char name[20]; char surname[20]; void p() { printf("Client::p\n"); } virtual void insert_name( void ) = 0; };
class ClienteD : public Cliente { public: void insert_name() { printf("insert_name ClientD\n"); } void p() { printf("ClientD::p\n"); } };
In my application.cc :
...
ClienteD pippo; ...
ClienteD* cliente = new ClienteD(); cliente->insert_name(); cliente->p();
Cliente* base = new ClienteD(); base->insert_name(); base->p();
pippo.p();
But when I see my terminal window NOTHING, NO any printf() Appear !
KEEP IN MIND that the SAME application (Example 2) only) I used for testing C++ with EDK 8.1.01i and all was fine ! Why now I have all these problem ?
Thanks in advance for any answers !
Cheers,
Al.
Article: 112486On Thu, 23 Nov 2006 02:26:46 GMT, "Homer J Simpson" <nobody@nowhere.com> wrote: > >"John Fields" <jfields@austininstruments.com> wrote in message >news:ooe9m2ld470u6rg7tqku3vfchh83960698@4ax.com... > >>>I once wrote an Eratosthenes' prime number sieve using the video display >>>as >>>an array memory (on a 4K machine). > >> How high did it go? to 9? > >You still count on your fingers? --- Sure. For lots of things. -- JFArticle: 112487
Dear John, I actually mentioned this in my previous thread - but I think I need to repeat it here. (I don't have much experience posting to news groups.) I am a student, without much experience of synthesis. My task was to make some modifications (i.e. insert faults) to the ISCAS benchmark circuits and synthesize them to the FPGAs. I read the circuits using the ISCAS benchmark format - made my changes to the circuit structure and dumped out the VHDL. As my initial circuit is combinational and a gate level netlist - it cannot be functionally divided in anyway. I can of course group neighboring gates into higher level entities - but I don't think that this would make things easier for the synthesis tool. I am not sure if this clarifies some aspects regarding my post - if it does not let me know where I should elaborate. Thanks a lot. O.O. John_H wrote: > Can you figure a way to functionally break up your design? The only huge > "combinational" designs I've known of were either 1) incorrect or 2) part of > a genetic algorithm development. Chances are that your design is > significantly more complex than it needs to be. Rather than performing > everything in one large equation, can you divide it up into functional parts > that can give you your goal in several clocks rather than all at once? > > The idea is the first, most important part of your design. Implementation > gets you toward reality. Ask yourself what the hardware can do and use that > as a guideline for how to partition your design in functional pieces that > can give you what you need over several clocks. > > Good luck. >Article: 112488
Nevo wrote: > I'm looking at the cost of serial configuration devices from Altera and am a > little shocked at how expensive they are. Digi Key sells the EPCS4 for $13, > which seems steep for 4Mbit of storage. > > A quick glance at Digi-Key's website suggests I can get an SPI-compatible > PIC chip and a 4Mbit SPI FLASH memory for less than $4, which means I should > be able to program the FPGA from the PIC for a third of the cost of Altera's > solutoin. > > Before I go off and reinvent the wheel, does anyone know of a prepackaged > solution for programming an Altera device (I'm using a Cyclone) with a > microcontroller that I can just drop into my project? I'm sure I can't be > the first person to do this. If anyone has a website describing a similar > setup, I'd love to see it. Some years ago I designed a system with an ADI DSP and Altera FPGA. I bit-banged the configuration data into the FPGA using a couple of outputs on the DSP. Altera had an application note on how to do it which I used. LeonArticle: 112489
Hi, I have now written a program to initialise the 68013 to slave fifo mode, but I am struggling to find any tutorials on how to program this onto the 68013 and test it. If for example I wished to write to a memory location on the 8051 and then read it back how could I do this. Thanks again, AlArticle: 112490
Hi, I'm trying to connect a MicroBlaze system build in EDK to a custom periphal core. I am using Atmark's Suzaku board [1]. It is shipped with an example project which I would like to extend via FSL. Here is what I did: - Added two FSL cores and connected them to the MB - Changed the ports for my periphal to "make external" My intention is to import the EDK project into ISE later on to connect it to my system. The instantiation template looks fine but when I try to generate the netlist of the processor system I get the folllowing error message: [snip] > fsl_v20 (fsl_from_mb) - > X:\Controller\EDK\xps_proj.mhs line 332 - 1 > master(s) : 0 slave(s) > ERROR:MDT - fsl_v20 (fsl_from_mb) - > X:\Controller\EDK\xps_proj.mhs line 332 - must > have atleast 1 slave assigned! > fsl_v20 (fsl_to_mb) - X:\Controller\EDK\xps_proj.mhs > line 342 - 0 master(s) : 1 slave(s) > ERROR:MDT - fsl_v20 (fsl_to_mb) - > X:\Controller\EDK\xps_proj.mhs line 342 - must > have atleast 1 master assigned! > > Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC... > ERROR:MDT - platgen failed with errors! > > make: *** [implementation/microblaze_i_wrapper.ngc] Error 2 [snap] The FSL master and slave ports will be connected in ISE, of course. Is there any way to override the error message? Is there a better solution? EDK and ISE are the latest version with all service packs/patches applied... Thanks in advance, cheers /Chris [1] http://suzaku-en.atmark-techno.com/Article: 112491
On 2006-11-23, olson_ord@yahoo.it <olson_ord@yahoo.it> wrote: > Dear John, > I actually mentioned this in my previous thread - but I think I need > to repeat it here. (I don't have much experience posting to news > groups.) > > I am a student, without much experience of synthesis. My task was to > make some modifications (i.e. insert faults) to the ISCAS benchmark > circuits and synthesize them to the FPGAs. I read the circuits using > the ISCAS benchmark format - made my changes to the circuit structure > and dumped out the VHDL. > > As my initial circuit is combinational and a gate level netlist - it > cannot be functionally divided in anyway. I can of course group > neighboring gates into higher level entities - but I don't think that > this would make things easier for the synthesis tool. What kind of gates do you have in your original netlist? Is it simple nand/and/or/nor-gates with few inputs? If you have that kind of gates with 4 or less inputs it is easy to map one gate to one LUT. In that case you will feed a netlist to the synthesizer which is already composed of primitives so the synthesizer will not be able to optimize the design much and therefore should be able to run with less effort (hopefully). /AndreasArticle: 112492
Christian Schleiffer schrieb: > Hi, > > I'm trying to connect a MicroBlaze system build in EDK to a custom > periphal core. I am using Atmark's Suzaku board [1]. It is shipped with > an example project which I would like to extend via FSL. Here is what I did: > > - Added two FSL cores and connected them to the MB > - Changed the ports for my periphal to "make external" > > My intention is to import the EDK project into ISE later on to connect > it to my system. The instantiation template looks fine but when I try to > generate the netlist of the processor system I get the folllowing error > message: > > [snip] > > fsl_v20 (fsl_from_mb) - > > X:\Controller\EDK\xps_proj.mhs line 332 - 1 > > master(s) : 0 slave(s) > > ERROR:MDT - fsl_v20 (fsl_from_mb) - > > X:\Controller\EDK\xps_proj.mhs line 332 - must > > have atleast 1 slave assigned! > > fsl_v20 (fsl_to_mb) - X:\Controller\EDK\xps_proj.mhs > > line 342 - 0 master(s) : 1 slave(s) > > ERROR:MDT - fsl_v20 (fsl_to_mb) - > > X:\Controller\EDK\xps_proj.mhs line 342 - must > > have atleast 1 master assigned! > > > > Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC... > > ERROR:MDT - platgen failed with errors! > > > > make: *** [implementation/microblaze_i_wrapper.ngc] Error 2 > [snap] > > The FSL master and slave ports will be connected in ISE, of course. Is > there any way to override the error message? Is there a better solution? > EDK and ISE are the latest version with all service packs/patches applied... > > Thanks in advance, cheers > /Chris > > [1] http://suzaku-en.atmark-techno.com/ one solution is to make the MB FSL ports external, in that case you have no FSL bus in EDK, this works for sure, but you have to implement the FSL bus and-or fifos in ISE toplevel then AnttiArticle: 112493
Antti wrote: > one solution is to make the MB FSL ports external, in that case you > have no FSL bus in EDK, this works for sure, but you have to implement > the FSL bus and-or fifos in ISE toplevel then Good point. It should be quite simple to implement FSL myself, but I think I even saw some source files somewhere in the EDK directory...Article: 112494
Andreas Ehliar wrote:
>
> What kind of gates do you have in your original netlist? Is it simple
> nand/and/or/nor-gates with few inputs?
>
> If you have that kind of gates with 4 or less inputs it is easy to map
> one gate to one LUT. In that case you will feed a netlist to the synthesizer
> which is already composed of primitives so the synthesizer will not be able
> to optimize the design much and therefore should be able to run with less
> effort (hopefully).
>
>
> /Andreas
Hi Andreas,
Though the number of signals in my design is large - I am sure that
most of the gates are simple and have less than 4 inputs.
I am not sure how I should map a gate to a LUT. Could you show me an
example how to do that? (Right now XST does that for me - but I would
be glad to specify that myself.) An example of a gate in my design
looks like
And_2_282_1319 : node_R1207_U134_Cell_1282 <=
node_R1207_U242_Cell_1282 and node_R1207_U241_Cell_1282;
I should mention that I have a really large number of signals (due to
the way I wrote my C++ code to generate the VHDL) that feed into each
other
For e.g. Somewhere I have
node_R1207_U242_Cell_1282 <= forg_node_R1207_U242_Cell_1282;
then in another place I have
forg_node_R1207_U242_Cell_1282 <= forg_node_R1207_U242;
In yet another place I have
forg_node_R1207_U242 <= node_R1207_U242;
and finally I have
node_R1207_U242 <= node_R1207_U242_Cell_1283;
Before it gets to the next gate with
Nand_2_956_1320 : node_R1207_U242_Cell_1283 <= not
(node_U3081_Cell_1283 and node_R1207_U210_Cell_1283);
That's 4 signals that are actually equivalent. I thought that the
synthesis tool should be able to figure that out - so do you think that
this may be a problem? Actually changing my C++ code is going to be
really difficult and could take 3 weeks to a month, so I don't want to
change this.
Thanks a lot for your ideas.
O.O.
Article: 112495Tool = ISE 8.2i Target = Spartan 3 xc3s400-4tq144 I'm using an external 50 MHz oscillator and a single DCM to generate clocks of 50, 100 and 200 MHz. The static timing reports says the minimum period for my 200 MHz clock is 4.999ns i.e. 1ps to spare. I saw this comment in the Verilog file auto-generated by the DCM wizard: // Period Jitter (unit interval) for block DCM_INST = 0.14 UI // Period Jitter (Peak-to-Peak) for block DCM_INST = 0.70 ns What does this mean? How can I meet timing by 1ps when the jitter is 700ps?Article: 112496
Tool = ISE 8.2i Target = Spartan 3 xc3s400-4tq144 I created a prorated VOLTAGE constraint using the GUI constraints editor; but it seems to be ignored when I implement my design. The PAR report quotes the default of 1.140V. When I launch Timing Analyzer, it says prorating is not available for my device and speed grade. Is there any way around this? My design achieves timing closure, but only by 1ps, which is cutting it a bit fine! Should I be worried?Article: 112497
Tool = ISE 8.2i Target = Spartan 3 xc3s400-4tq144 I'm using an external 50 MHz oscillator and a single DCM to generate clocks of 50, 100 and 200 MHz. I would like to change this to 50, 90 and 180 MHz from the same external oscillator. I tried this using two DCMs and the timing analysis report went crazy! I think this is because the clock edges from a single DCM are all synchronised, but now I have routing delays which cannot be cancelled by the DLL. How do I stop the tools from checking paths between different clock domains?Article: 112498
"Andrew Holme" <ajholme@hotmail.com> wrote in message news:1164289962.815338.179200@j44g2000cwa.googlegroups.com... > Tool = ISE 8.2i > Target = Spartan 3 xc3s400-4tq144 > > I have routing delays which cannot be cancelled by the DLL. How do I > stop the tools from checking paths between different clock domains? > Google UCF TIG HTH, Syms.Article: 112499
Hi I have a design with a Power PC that I am trying to put through ISE. The problem I have is that I get the following error. Failed to process BMM file Not sure why or how to fix this as there is a bmm file in the implementation dir. Any help would be appreciated Jon
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