Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
On Tue, 21 Nov 2006 17:51:46 -0500, Ray Andraka <ray@andraka.com> wrote: >> I understand why the vendors don't specifically target the async market, >> although I will say that the software developers who do the tools don't >> always appear to truly understand hardware (it covers so many sins, I am >> not surprised, nor is it a complaint, more an acknowledgment). > >Yup, I agree here. I really think the developers should be required to >sit and use their tools on a design, but then they'd have to get up to >speed on digital design first. Rob, my best FPGA guy, has given up on using the Xilinx 8.2/sp3 IDE software... it's way too flakey. But he says the underlying chunks work fine from the command line, so he put together a "make" thing to process the chip we're working on. So it looks like the core fpga-crunching software was coded by people who know what they're doing, and the IDE wrapper (which runs in 90 megabytes of ram!) was coded by Windows programmers. JohnArticle: 112426
Grant Stockly wrote: > > One type of computer that might actually be interesting to build of > > relays and operate would be a time piece. To keep the power > > consumption down, you might use latching relays. The contain a > > permanet magnet that holds the contact in either state and a pulse from > > the coil is required to change the state. Each relay is then a FF. > > The logic would be done by stringing relays in series or parallel to > > form AND and OR functions (with or without inversions). You could also > > use diodes to form the logic if you want to save some space. There are > > some fairly minature relays available at around $5 or less. We are > > using some latching RF relays at that price. They are about 15 x 10 mm > > so a clock circuit might take up a square foot depending on the > > density. It would also tick every second with major noises on the > > minutes and hours. > > > > I am working on a relay controller circuit for an RF module and when I > > do the test code, it will have a few options to sound out tap dancing > > like music. That should prove interesting and entertaining! > > That is a pretty good idea. Would you have to use vaccume tubes with a > crystal to generate the 1 second clock? (to maintain period > technology) > > Now you have my head spinning...Its a good thing I'm done with the > Altair! :) > > Before that I wanted to answer the question "What is the latency of a > ping to a relay based computer?" My friends would hardly talk to me > about that one. They think I'm crazy too. > > ALL the relays need to be the clear ice cube kind with the LED to > indicate state. Or a separate LED I guess. I really like visual > things. :) Years ago when I was in college, my dad got me a job with the railroad he worked for. I was an apprentice helper to the signalman who kept the signals working on the Old Main Line between Baltimore and points west of Brunswick, MD. One of the things that really impressed me was when I got to see inside one of the signal cabinets at a larger crossing. It had a dozen or so relays that were made of separate components. The top was a coil and the binding posts for the wiring. The bottom was a glass cover with the contacts inside. It was glass so that they could be visually inspected without disassembly. Inside each glass was a hand written tag showing when the relay was put in service and last maintained. This was in the 70's and the relays had been last maintained 20 years before and put into service 50 years before! These things were about 8 inches square at the base and perhaps 10 inches to a foot tall. So they would be hard to make a clock from. But it was impressive to see something that was really made to last a long time in contrast to how things are made today... cheap to make and a low failure rate for 5 years maybe. After that it no longer matters since the device is likely to be obsolete. It makes me want to build things that last a long time.Article: 112427
John Larkin wrote: > We just solved a nasty problem with this: > > A d-flop: D tied high; clocked from a pin, CE from internal gating > logic. Its Q output drives a BUFG clock net buffer, and Q also feeds a > delay line back into its own async clear. When the input pin rises, if > CE permits, it makes a single clock pulse. Everything downstream is > "synchronous" in that it's clocked from this gadget. > > The delay line is a chain of AND gates (with transparent latches > enabled in the logic cells, just to add a little more delay), with > each fed from the ff Q and also from the previous gate. This is a > delay line with a fast discharge mechanism when its input goes low, so > we don't have to wait for the 0 to propagate through, chasing the 1. How do you synchronize the input clock with the internal CE signal? If it is not synchronized, couldn't you get nasty splinter pulses? How do you control the timing of the delay line? Is the timing window that you can work in pretty wide?Article: 112428
> hm, i have two 64K blocks on LMB bus, and only first one is updated in the > BMM file :( > I dont think this is advanced use ? One obvious difference is that I am working with PPC and using PLB_BRAM controllers while you are dealing with MicroBlaze... I can't say why it should matter though... /MikhailArticle: 112429
On 21 Nov 2006 20:14:43 -0800, "rickman" <gnuarm@gmail.com> wrote: >John Larkin wrote: >> We just solved a nasty problem with this: >> >> A d-flop: D tied high; clocked from a pin, CE from internal gating >> logic. Its Q output drives a BUFG clock net buffer, and Q also feeds a >> delay line back into its own async clear. When the input pin rises, if >> CE permits, it makes a single clock pulse. Everything downstream is >> "synchronous" in that it's clocked from this gadget. >> >> The delay line is a chain of AND gates (with transparent latches >> enabled in the logic cells, just to add a little more delay), with >> each fed from the ff Q and also from the previous gate. This is a >> delay line with a fast discharge mechanism when its input goes low, so >> we don't have to wait for the 0 to propagate through, chasing the 1. > >How do you synchronize the input clock with the internal CE signal? If >it is not synchronized, couldn't you get nasty splinter pulses? The gate signal is totally async to the clock. We're sort of hoping that the output of the logic block is either going to go high or not. A metastability glitch within a Spartan3 flip flop is (optimistically) narrower than the inter-cell routing can propagate. We'll have to try that and see. I could put setup and hold time requirements on the trigger gate specs, and make it the customer's problem! >How do you control the timing of the delay line? Is the timing window >that you can work in pretty wide? The downstream logic has to work at 80 MHz max. So if we experimentally tune the BUFG output width to, say, 4 ns, we should have a pretty good margin both ways. Most silicon processes seem to be pretty stable these days. I suppose we could make the delay tunable through a register our uP could write, and we could check a test point now and then to make sure we have it right. Just a mux selecting delay-line taps would work. We only need to do this once in the product, and it's important, so this is worth some hassle. The trick is, I suppose, to only take risks when you really need to. JohnArticle: 112430
Jozsef schrieb: > Hello, > > as many people over this world, I have a problem. The problem is the > connection beetween a CPLD and the WEBPACK ISE 8.2.03 software. > Simptoms like very static: I have an Parallel Cable III, the ISE > software, and a XC9500XL family CPLD. The Impact cannot recognise the > CPLD, for example a simple XC95144XL showed five unknown device in the > JTAG chain on automatic JTAG chain initialize. I' has been tried to add > the device manually, but there is not accepted as a result, because > Impact answers unknown device ID. I'm told each family because tried > with xc9536XL, simptoms are same. > The cable is OK, I using it to program other devices (for example, > XC3S400) on everyday. > On software side, tried an older software (Xilinx Foundation 4) to > program these devices, that programs all without problems. > > The question is what is the problem with ISE 8.2.03 ??? Hi I have not tried XC95xx programming with ISE 8.x but the CPLD fitter for XC95xx is badly broken so I cant use 8.x tools anyway - wait - i have ML501 board and impact DOES reconize XC95144XL in te chain ok, so jtag programming shoud work with 8.x AnttiArticle: 112431
>Rob, my best FPGA guy, has given up on using the Xilinx 8.2/sp3 IDE >software... it's way too flakey. But he says the underlying chunks >work fine from the command line, so he put together a "make" thing to >process the chip we're working on. So it looks like the core >fpga-crunching software was coded by people who know what they're >doing, and the IDE wrapper (which runs in 90 megabytes of ram!) was >coded by Windows programmers. Seems the GUI-mafia just love RAM.. :)Article: 112432
Your symptoms suggest a JTAG chain problem and could be reflections on the chain, poor power supply to JTAG head, poor head connections, pickup of noise on JTAG. If you are using the flying lead set normally attached to Cable III head do check the connectors of lead set. These have a habit breaking eventually. Also check if the TDO line out of the XC95144XL needs a pullup to operate correctly and it's value. Some parts do and some don't. John Adair Enterpoint Ltd. Jozsef wrote: > Hello, > > as many people over this world, I have a problem. The problem is the > connection beetween a CPLD and the WEBPACK ISE 8.2.03 software. > Simptoms like very static: I have an Parallel Cable III, the ISE > software, and a XC9500XL family CPLD. The Impact cannot recognise the > CPLD, for example a simple XC95144XL showed five unknown device in the > JTAG chain on automatic JTAG chain initialize. I' has been tried to add > the device manually, but there is not accepted as a result, because > Impact answers unknown device ID. I'm told each family because tried > with xc9536XL, simptoms are same. > The cable is OK, I using it to program other devices (for example, > XC3S400) on everyday. > On software side, tried an older software (Xilinx Foundation 4) to > program these devices, that programs all without problems. > > The question is what is the problem with ISE 8.2.03 ???Article: 112433
Grant Stockly wrote: [snip] > That is a pretty good idea. Would you have to use vaccume tubes with a > crystal to generate the 1 second clock? (to maintain period > technology) > A tuning fork might be more in keeping: middle A = 440Hz, which could make a useful timebase.Article: 112434
"rickman" <gnuarm@gmail.com> wrote in message news:1164168367.414035.264980@e3g2000cwe.googlegroups.com... > > since the device is likely to be obsolete. It makes me want to build > things that last a long time. > Hi Rick, Have you seen this? http://www.longnow.org/projects/clock/principles/ Cheers, Syms.Article: 112435
On a sunny day (Tue, 21 Nov 2006 23:30:19 GMT) it happened "ma" <ma@nowhere.com> wrote in <f_L8h.40$bz5.28@fe3.news.blueyonder.co.uk>: >Hello, > > I know that it is possible to demodulate an FM signal using a CORDIC >ATAN core and the subtracting the current ouput of cordic from the last one. >But I can not understand how carrier frequency and sampling rate would >change it? What are the requirements? Where are the limitations? > > > >Regards You can also demodulate an FM signal by generating a short fixed length fixed amplitude pulse (one shot) on each zero crossing on an output, and then doing a lowpass. A lot simpler.Article: 112436
On Mon, 20 Nov 2006 11:05:58 -0800, Vangelis <> wrote: >Does anynone know where can I find VHDL models for DDR modules? I have an XUP board and I want to run some simulations before downloading my design to the FPGA. I am not looking for a specific model. Any generic DDR model will do the job. Micron used to provide good models; unfortunately they don't seem to for DDR, if you need VHDL. The Hynix models seem to work OK. - BrianArticle: 112437
Very interesting! In fact I can understand its mathematic! calculating frequncy based on zero crossing. How can I do this in software or FPGA? Regards "Jan Panteltje" <pNaonStpealmtje@yahoo.com> wrote in message news:ek1bjv$hut$1@news.datemas.de... > On a sunny day (Tue, 21 Nov 2006 23:30:19 GMT) it happened "ma" > <ma@nowhere.com> wrote in <f_L8h.40$bz5.28@fe3.news.blueyonder.co.uk>: > >>Hello, >> >> I know that it is possible to demodulate an FM signal using a CORDIC >>ATAN core and the subtracting the current ouput of cordic from the last >>one. >>But I can not understand how carrier frequency and sampling rate would >>change it? What are the requirements? Where are the limitations? >> >> >> >>Regards > > You can also demodulate an FM signal by generating a short fixed length > fixed > amplitude pulse (one shot) on each zero crossing on an output, and then > doing > a lowpass. > A lot simpler.Article: 112438
Hello, I'm working for a company that sell FPGA IP in netlist form. I'd like to protect theses IP as much as I can, to try to make it as hard as possible to RE them. I know I can't possibly fully protect them, but that doesn't mean it doesn't worth trying. I've already used the "secure netlist" option of the Xilinx tools, but it's not that secure. Also, the net names stays the same. So I'm looking at an obfuscating tool that would rename all net/instances for me. And also other methods you might know ? Thanks, SylvainArticle: 112439
Hi when looking at EDK OPB_MCH_DDR2 memory controller datasheet then it looks like each access to DDR2 memory takes about 30 system clock cycles (60 memory clocks) so maximum bandwith when reading bursts is about 50MB/s and even less when doing random reads, this sounds like EXTREMLY low performance, I wonder if the datasheet timings are wrong, or maybe the timing is fixed in EDK 9.1? AnttiArticle: 112440
On a sunny day (Wed, 22 Nov 2006 11:36:59 GMT) it happened "ma"
<ma@nowhere.com> wrote in <vDW8h.688$qd7.415@fe1.news.blueyonder.co.uk>:
>Very interesting! In fact I can understand its mathematic! calculating
>frequncy based on zero crossing. How can I do this in software or FPGA?
generate short pulse with XOR
.........................................
.
---gate delay-- IO pin
FM--| XOR------ pulse----0---- resistor---------- demodulated FM
--------------- . |
. ===
. |
FPGA . ///
.........................................
LOL
Article: 112441this needs that FM signal be an analouge signal but in my case it is a digital one ( samples using an ADC). Am I wrong? "Jan Panteltje" <pNaonStpealmtje@yahoo.com> wrote in message news:ek1fef$qbu$1@news.datemas.de... > On a sunny day (Wed, 22 Nov 2006 11:36:59 GMT) it happened "ma" > <ma@nowhere.com> wrote in <vDW8h.688$qd7.415@fe1.news.blueyonder.co.uk>: > >>Very interesting! In fact I can understand its mathematic! calculating >>frequncy based on zero crossing. How can I do this in software or FPGA? > > generate short pulse with XOR > ......................................... > . > ---gate delay-- IO pin > FM--| XOR------ pulse----0---- resistor---------- > demodulated FM > --------------- . | > . === > . | > FPGA . /// > ......................................... > > LOLArticle: 112442
Hello i am quite new to EDK world... :). I am using a microblaze which works on 90Mhz clk. In my design there is an OPB also 90 Mhz. I would like to use the Exrnal Memory controler in order to read data from a single Intel Strata flash (8 bits depth) 40 Mhz. In the EMC pdf there is an example includes EMC and flash. The example is not so clear- how do i synchronize the EMC(90 Mhz) with the Flash (40Mhz)? How do I connect the data lines to the OPB i understand there is a little endian, big endian proble? thanks in advance Guy Zur.Article: 112443
MM schrieb: > > hm, i have two 64K blocks on LMB bus, and only first one is updated in the > > BMM file :( > > I dont think this is advanced use ? > > One obvious difference is that I am working with PPC and using PLB_BRAM > controllers while you are dealing with MicroBlaze... I can't say why it > should matter though... > > /Mikhail BUG::: EDK 8.2 generates BMMs incompatible with ISE 8.2 when BRAM blocks are consecutive. if there is gap in address space then it all works. there is a workaround to manually fix the generated BMM files AnttiArticle: 112444
John Larkin wrote: > On 21 Nov 2006 20:14:43 -0800, "rickman" <gnuarm@gmail.com> wrote: > > >John Larkin wrote: > >> We just solved a nasty problem with this: > >> > >> A d-flop: D tied high; clocked from a pin, CE from internal gating > >> logic. Its Q output drives a BUFG clock net buffer, and Q also feeds a > >> delay line back into its own async clear. When the input pin rises, if > >> CE permits, it makes a single clock pulse. Everything downstream is > >> "synchronous" in that it's clocked from this gadget. > >> > >> The delay line is a chain of AND gates (with transparent latches > >> enabled in the logic cells, just to add a little more delay), with > >> each fed from the ff Q and also from the previous gate. This is a > >> delay line with a fast discharge mechanism when its input goes low, so > >> we don't have to wait for the 0 to propagate through, chasing the 1. > > > >How do you synchronize the input clock with the internal CE signal? If > >it is not synchronized, couldn't you get nasty splinter pulses? > > The gate signal is totally async to the clock. We're sort of hoping > that the output of the logic block is either going to go high or not. > A metastability glitch within a Spartan3 flip flop is (optimistically) > narrower than the inter-cell routing can propagate. We'll have to try > that and see. I could put setup and hold time requirements on the > trigger gate specs, and make it the customer's problem! > > >How do you control the timing of the delay line? Is the timing window > >that you can work in pretty wide? > > The downstream logic has to work at 80 MHz max. So if we > experimentally tune the BUFG output width to, say, 4 ns, we should > have a pretty good margin both ways. Most silicon processes seem to be > pretty stable these days. > > I suppose we could make the delay tunable through a register our uP > could write, and we could check a test point now and then to make sure > we have it right. Just a mux selecting delay-line taps would work. We > only need to do this once in the product, and it's important, so this > is worth some hassle. The trick is, I suppose, to only take risks when > you really need to. I'm not sure I understand your problem, so I'll ask a few more questions. What is the speed of the clock in the design? How often does the internally clocked CE signal gate the external signal to generate a clock pulse? If the external signal will not generate a clock edge on every internal clock there might be an easier way to do this that does not depend on timing delays. It can generate a clock enable signal that is asserted on every other clock cycle. But this may or may not work for your application.Article: 112445
On a sunny day (Wed, 22 Nov 2006 12:47:26 GMT) it happened "ma" <ma@nowhere.com> wrote in <yFX8h.715$qd7.168@fe1.news.blueyonder.co.uk>: >this needs that FM signal be an analouge signal but in my case it is a >digital one ( samples using an ADC). Am I wrong? That depends, in *FM* there must be some zero crossings, and depending on how you digitised the signal that would corresond to a specific level. For example 8 bit ADC, and symmetric AC, and zero at 128 decimal, use comparator, pseudo code: if( my_signal > 128 ) then pulse = 1; else pulse = 0; Feed that 'pulse' to xor gate below. In a micro you can count period time too, or grab and then reset a counter that inclremets on a fst clock, there are many ways. > >"Jan Panteltje" <pNaonStpealmtje@yahoo.com> wrote in message >news:ek1fef$qbu$1@news.datemas.de... >> On a sunny day (Wed, 22 Nov 2006 11:36:59 GMT) it happened "ma" >> <ma@nowhere.com> wrote in <vDW8h.688$qd7.415@fe1.news.blueyonder.co.uk>: >> >>>Very interesting! In fact I can understand its mathematic! calculating >>>frequncy based on zero crossing. How can I do this in software or FPGA? >> >> generate short pulse with XOR >> ......................................... >> . >> ---gate delay-- IO pin >> FM--| XOR------ pulse----0---- resistor---------- >> demodulated FM >> --------------- . | >> . === >> . | >> FPGA . /// >> ......................................... >> >> LOL > > >Article: 112446
Of course the code should have been: if( adc > 127) ... else .... So you can simply grab the 'sign bit', bit 7.Article: 112447
Hello, I was just browsing the Xilinx Libraries Guide pdf in search of BUFT component. However, it is not mentioned anymore in the 'Virtex 4 Libraries Guide for HDL designs'. I was looking into them to optimize wide muxes and a bus traversing the complete FPGA fabric. Are tristates left out of the Virtex4? Is there an alternative? What could be the motivation for such an architectural change? Best Regards, Koen.Article: 112448
Thanks. On Nov 21, 4:56 am, Sean Durkin <s...@despammed.com> wrote: > lecroy7...@chek.com wrote: > > I can't seem to find a document that calls out the XY locations for the > > IDELAYCTRL. Where is this information found?Try Jim Wu's free ADEPT-Tool:http://home.comcast.net/~jimwu88/tools/adept/ > > There's a view where you can see the IDELAYCTRL-locations and the pins > that are controlled by this specific IDELAYCTRL. This tools is really > handy for other stuff as well (like seeing which IOs belong to which > IO-Clock-Region and regional clock and things like that), and doesn't > cost anything. > > cu, > SeanArticle: 112449
This is what I plan to do. I agree, it appears to trim out the unused ones anyway. Xilinx had a lot of notes about using the LOC, so it seemed like this was important, but maybe it's not so much an issue now. So, I have a little prototype card I am using to evaluate the IDELAY. We placed an XC4VSX35FF668-12 on it. I have two clocks that I can drive the FPGA with. One is a 50MHZ CMOS type, the other an SMA that drives a LVPECL driver that goes to the FPGA. I see no problems using the IDELAY when I use the RF generator for the clock source. In this case I am running the input clock at 200MHz. However when I use the 50MHz clock and multiply it up to 200MHz with a DCM, the IDELAY does some strange things. I have a MICTOR on the board that I can use to look at some of the signals. Looking at the CLKFX output from the DCM, it appears normal and is running at 200MHz. I see both the DCM and IDELAYCRTL readys. What is strange is that when I program in a delayline, rather than seeing 75ps of delay, I see about 200ps per tap. I read Austin's note on using the DCM as a source and it seems like it should work. Another strange problem I am seeing is that certain pin that have the same number of taps selected give a different delay. Again, everything works fine when I drive the IDELAYCRTL without using the DCM. I am at a loss. On Nov 20, 5:00 pm, Ray Andraka <r...@andraka.com> wrote: > lecroy7...@chek.com wrote: > > I can't seem to find a document that calls out the XY locations for the > > IDELAYCTRL. Where is this information found? > > > When I don't use the LOC, the report for P&R says it has used 100% of > > the IDELAYCTRLs. No surprize. When I look at the FPGA editor I would > > expext to see all of them listed but instead I only see a small portion > > of them. Why? > > > It appears that if I include an IDELAY that there is some sort of > > requirement on where the IDELAYCTRL is located. Currently I don't use > > the LOC, let the tool P&R then use the FPGA editor to see where it > > placed it. Then I use the LOC. What a pain. There must be a simpler > > way. I tell the tools where the IDELAY is to be used, why is it that > > the tools can't place the controller automatically? > > > If I select the wrong location for the IDELAYCTRL, the tool does not > > flag an error, the design just fails to work. You would think it would > > be smart enough to know.As long as you run all the idelays on the same 200 MHz reference clock, > and that reference clock runs continuously, you shouldn't need to > separately reference the idelayctrl's, which means you can just put one > at the top level of your design and run the idly_rdy to all instances of > your idelays. If there is only one idelayctrl instantiated in your > design, then the PAR tools automatically replicate it and you don't need > to put any RLOCs on it. I believe the replication replicates it into > all sites, and then map later trims out any that are in regions where > there are no idelays used and the rdy pin is not used. If the rdy pin is > used, the software instantiates an AND gate to combine all the RDY's > into one signal, so if RDY is used, all the idelaysctrls remain in the > circuit. This will lead to higher power consumption, but otherwise > doesn't adversely affect the design. Xilinx does recommend using LOCs > and explicitly placing these, but like you, I found that highly > inconvenient. The only place I think you can get the locations is off > FPGA editor, and those change depending on the particular device. > Unless you are either a) concerned about every bit of power consumption, > b) using the rdy's differently for different banks and can't live with > waiting till all the idelayctrls come on line, or c) are doing something > where you have different reference clocks (why would you do this?) or > different resets for the idelayctrls, then I think the added power > consumption and the big and gate are a very small price to pay for the > simplicity of the un LOC'd instancing.
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z