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Antti wrote: > iceg...@gmail.com schrieb: > > > I'm searching Microblaze example projects and codes. I think There are > > only a few example on the Xilinx web page. Also I can't find a document > > about drivers of microblaze. Dou you know any documents about drivers > > like as gpio.h or gpio.c etc? > > those documents are on EDK CD, not on xilinx website. > some of them are website too, but not all > > Antti I have got EDK Eval DVD but there is no document. How I can learn it?Article: 112676
Hello Ram, If you have Quartus II 6.0 or 6.0 SP1 take a look at the Advisors available under the Tools->Advisor menu. There are three advisors for Resources, Timing and Power. These advisors provide information on how to improve the performance of your design. It makes use of design information to provide advice that is targeted for your specific design. Information in these Advisors can be used to achieve Resource reduction (includes routing usage), Timing Closure and Power Reduction. They are very easy to use and they are updated each release. It is one of the best ways to learn about the new and existing capabilities that exist in Quartus . Hope this helps, Subroto Datta Altera Corp. "ram" <vsrpkumar@rediffmail.com> wrote in message news:1164624527.286353.216840@45g2000cws.googlegroups.com... > Can anyone give tips for Placement and ruoting tips for altera > quartusII.I think it will be helpful for many people in the > forum.Thanking you > kumar >Article: 112677
EHLO (o; What happened to the nios2 sources which were once accessable via the doc/degree ftp login documented on the Altera website? Unfortunately Altera stopped sponsoring me with Quartus/NIOS for doing core tests and porting cores to sopc builder...so I won't get any more nios2 toolchain sources on CD (o; cheers rickArticle: 112678
Richard Klingler schrieb: > EHLO (o; > > > What happened to the nios2 sources which were once accessable > via the doc/degree ftp login documented on the Altera website? > > Unfortunately Altera stopped sponsoring me with Quartus/NIOS > for doing core tests and porting cores to sopc builder...so > I won't get any more nios2 toolchain sources on CD (o; > cheers > rick well if they dont want to violate the GPL license they must provide the source codes, like both Xilinx and Lattice do for their soft cpus AnttiArticle: 112679
On 2006-11-27 16:30:59 +0100, "Antti" <Antti.Lukats@xilant.com> said: > Richard Klingler schrieb: > >> EHLO (o; >> >> >> What happened to the nios2 sources which were once accessable >> via the doc/degree ftp login documented on the Altera website? >> >> Unfortunately Altera stopped sponsoring me with Quartus/NIOS >> for doing core tests and porting cores to sopc builder...so >> I won't get any more nios2 toolchain sources on CD (o; >> cheers >> rick > > well if they dont want to violate the GPL license they must provide > the source codes, like both Xilinx and Lattice do for their soft cpus > > Antti Aaahh....familiar name (o; At least I could win Lattice and Actel for sponsoring design software and devices. But concentrating on porting to Lattice now as Actel sended an obsolete evaluation board (o; Isn't that with GPL that you only have to give the sources upon requests if you already bought their product? So basically someone without a NIOS board the request could be denied? cheers rickArticle: 112680
The chip on the board shows: Xilinx Virtex-5 XC5VLX50 FFG676CGU0629 DD16917A 1C-ES I can't get the speed grade information (-1, -2 or -3?) from the chip and either the document. Can anybody tell me? Thanks a lot, Cathy.Article: 112681
We're close to december now. Have anyone heard when Lynuxworks will deliver? /JGArticle: 112682
Richard Klingler <me@aol.com> writes:
> Isn't that with GPL that you only have to give the sources upon
> requests if you already bought their product? So basically someone
> without a NIOS board the request could be denied?
IANAL but I've dealt with the GPL for a *long* time. The GPL allows
for three options when you distribute binaries:
1. Always include the source with the binaries. This works with
physical media, such as CD-ROM. (GPL 3a)
2. Make the source available via the same means as the binaries. This
works with web downloads, but the sources must be at the same site
(i.e. same admins) and "as accessible" as the binaries (i.e. if
there's no password on the binaries, there should be no password on
the sources). The rule is, if you can get the binaries, you must
be able to get the sources - although you may choose not to.
Otherwise, the sources don't "accompany" the binaries. (also GPL
3a)
3. Include a written offer, good for three years, to provide the
sources at a later date (for cost of media and postage). IMHO this
only works if the offer can be considered a "legal document" as
it's a dated contract. I interpret this as meaning "downloaded
text files don't count" although digitally signed files may if the
signed text includes the current date. (GPL 3b and 3c)
Note that option 3 is transferrable and sharable - if you get an
offer, you can photocopy it for as many friends as you like, and the
distributor is legally obligated to honor them. This is the only
option that *requires* you to give sources to someone you've never
given binaries to. GPL 3b covers when the originator creates the
offer for binaries they distribute, GPL 3c covers propogation of such
offer. Note the "any third party" in 3b :-)
I include GPL section 3 verbatim below.
3. You may copy and distribute the Program (or a work based on it,
under Section 2) in object code or executable form under the terms of
Sections 1 and 2 above provided that you also do one of the following:
a) Accompany it with the complete corresponding machine-readable
source code, which must be distributed under the terms of Sections
1 and 2 above on a medium customarily used for software interchange; or,
b) Accompany it with a written offer, valid for at least three
years, to give any third party, for a charge no more than your
cost of physically performing source distribution, a complete
machine-readable copy of the corresponding source code, to be
distributed under the terms of Sections 1 and 2 above on a medium
customarily used for software interchange; or,
c) Accompany it with the information you received as to the offer
to distribute corresponding source code. (This alternative is
allowed only for noncommercial distribution and only if you
received the program in object code or executable form with such
an offer, in accord with Subsection b above.)
Article: 112683cathy schrieb: > The chip on the board shows: > > Xilinx > Virtex-5 > XC5VLX50 > FFG676CGU0629 > DD16917A > 1C-ES > > I can't get the speed grade information (-1, -2 or -3?) from the chip > and either the document. Can anybody tell me? > Thanks a lot, > Cathy. last line -1 speed C commercial -ES engineering sample, READ ERRATA EN049.pdf AnttiArticle: 112684
"Symon" <symon_brewer@hotmail.com> wrote in message news:456ae4c0$1_1@x-privat.org... > "rickman" <gnuarm@gmail.com> wrote in message > news:1164628372.027773.61250@h54g2000cwb.googlegroups.com... >> Symon wrote: >>> "Sean Durkin" <news_nov06@durkin.de> wrote in message >>> news:456a8e5d$1@news.fhg.de... >>> > PeteS wrote: >>> >> On the S3, at least, VccAux powers the JTAG chain, part of the init >>> >> setup and the DCMs. I don't believe it powers anything else. >>> > It usually supplies input and output buffers for LVDS as well (at >>> > least >>> > it does in Virtex2 Pro and Virtex 4), even if the bank those IOs are >>> > in >>> > is supplied with i.e. 3.3V. >>> > >>> > cu, >>> > Sean >>> > >>> ...except for the differential termination bit. That seems to be powered >>> from VCCO. Pure genius. >> >> I can't say I understand this. Can you explain? >> > Hi Rick, > You can use LVDS receivers in a Vcco = 3.3V bank. As Sean says, it appears > they're powered from Vccaux. However, you can only use LVDS_DT receivers > if Vcco = 2.5V. Check out the note on Figure 31, DS083. I've posted here a > couple of times about this, I don't think I ever found out why it is so. > Cheers, Syms. > I suspect that the output stage for LVDS is always powered by VCCO (but the input side is powered by VCCAUX). Either way, it really is a PAIN IN THE BUTT that the differential termination only works at a specific VCCO supply voltage -- a REAL pain in the BUTT, Xilinx. BobArticle: 112685
pavan kumar wrote: > hi, i found that Julien Lochen is having I2C Controller implementation > using vhdl.Plz send me the src code(& test benches if u have) of this. > i need urgently..My email id is meetpavankumar@gmail.com > Have you tried open cores, or doing a web search for "I2C" and "FPGA"? I know that the I2C bus can be bit-banged on a microprocessor, so as long as you can control a pin to be open-drain you should have no problem with an FPGA. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Posting from Google? See http://cfaj.freeshell.org/google/ "Applied Control Theory for Embedded Systems" came out in April. See details at http://www.wescottdesign.com/actfes/actfes.htmlArticle: 112686
Could you list which device family are you targeting, what was the configuration ( # of lanes, 2/4 bytes, streaming/framing etc ) you choose to generate the design and the ISE tool's version which is throwing this error? With these details I might be able to answer your question. Roger wrote: > When I try to Implement a design with an Aurora core (v2.4) in it I get the > following error: > > ERROR:NgdBuild:753 - Line 68 in 'toplevel.ucf': Could not find instance(s) > 'Inst_aurora_sample/aurora_module_i/lane_0_phase_align_i/phase_align_flops_r* > ' in the design. To suppress this error specify the correct instance > name or > remove the constraint. > > The path to the FFs is correct. > > If I comment the following lines in "phase_align.vhd", it all seems to work > OK: > > -- Attribute Declaration > attribute KEEP_HIERARCHY : string; > attribute KEEP_HIERARCHY of RTL: architecture is "true"; > > Does anyone know what's going on here please? > > TIA, > > Rog.Article: 112687
"Sean Durkin" <news_nov06@durkin.de> wrote in message news:456af0f9$1@news.fhg.de... > Symon wrote: >> Hi Rick, >> You can use LVDS receivers in a Vcco = 3.3V bank. As Sean says, it >> appears >> they're powered from Vccaux. However, you can only use LVDS_DT receivers >> if >> Vcco = 2.5V. > Well, you CAN use them (i.e. the tools don't stop with an error or give > you w warning or anything), but the termination value won't be 100 Ohms. > Xilinx doesn't specify what the actual value might be, since they don't > recommend using the terminations that way. > I've used it successfully on 2 boards with VCCO=3.3V. "Successfully" > meaning that it works and the signal at the balls doesn't look that bad. > Right, thanks for making that clear Sean. (I remember we had a similar conversation here some time ago.) I've done the same myself, but only in prototypes. As you say, it worked fine. Of course, if Xilinx told us what the actual value was with 3.3V Vcco we could design the traces to suit. But they won't, because they'd have to have some kind of spec. which would add cost. As Bob says, a PITA. Maybe Rick should design in the _DT with Vcco 3.3V and take it along to one of his legendary 'peer reviews'! :-) Cheers, Syms.Article: 112688
Thank you very much, Antti.Article: 112689
Jan Panteltje wrote: > On a sunny day (Tue, 21 Nov 2006 23:30:19 GMT) it happened "ma" > <ma@nowhere.com> wrote in <f_L8h.40$bz5.28@fe3.news.blueyonder.co.uk>: > > >>Hello, >> >> I know that it is possible to demodulate an FM signal using a CORDIC >>ATAN core and the subtracting the current ouput of cordic from the last one. >>But I can not understand how carrier frequency and sampling rate would >>change it? What are the requirements? Where are the limitations? >> >> >> >>Regards > > > You can also demodulate an FM signal by generating a short fixed length fixed > amplitude pulse (one shot) on each zero crossing on an output, and then doing > a lowpass. > A lot simpler. A lot noisier too, I think. No?Article: 112690
Richard Klingler schrieb: > On 2006-11-27 16:30:59 +0100, "Antti" <Antti.Lukats@xilant.com> said: > > > Richard Klingler schrieb: > > > >> EHLO (o; > >> > >> > >> What happened to the nios2 sources which were once accessable > >> via the doc/degree ftp login documented on the Altera website? > >> > >> Unfortunately Altera stopped sponsoring me with Quartus/NIOS > >> for doing core tests and porting cores to sopc builder...so > >> I won't get any more nios2 toolchain sources on CD (o; > >> cheers > >> rick > > > > well if they dont want to violate the GPL license they must provide > > the source codes, like both Xilinx and Lattice do for their soft cpus > > > > Antti > > Aaahh....familiar name (o; > > At least I could win Lattice and Actel for sponsoring design software > and devices. But concentrating on porting to Lattice now as Actel > sended an obsolete evaluation board (o; > > Isn't that with GPL that you only have to give the sources upon > requests if you already bought their product? So basically someone > without a NIOS board the request could be denied? > > > cheers > rick well, if there is anything that can be downloaded from Altera like NIOS eval, that includes GPL based stuff then you should be able to get sources of that - even if you did not pay for the product. so NIOS eval is downloadable - those the GCC sources should be also available at the same method, eg download.. AnttiArticle: 112691
Thank you for your answer Jon, The JTAG problem was expected, and is easy to fix (write your own JTAG block). Regarding the MMU, well, I have heard the MB cannot be modified to include a MMU, is the same true for Mico32? The reason that I posted my previous questions in the first place was that if you synthesize a Mico32 project with, say, Quartus II you will notice that it cant fit in _any_ Cyclone II devices. The reason is that the lm32_ram block is designed in such way that the Quartus synthesizer cannot infer MK4 blocks... So my question to the list: has _anyone_ tried this CPU on Altera devices? regards, burns (still waiting for my ECP2M kit) Jon Beniston wrote: > > - If I plan to use a non-Lattice FPGA, would things work as smooth or > > will development become much more difficult? > > The only tricky bit will be the debugger, as that uses the dedicated > Lattice JTAG block. Workaround that, and the rest should be no problem > at all. > > > - Are any there any technical difficulties against porting Linux to > > this CPU? (just out of curiosity and completely unrelated to my > > project) > > It doesn't have an MMU, so the full blown Linux is out of the question. > However, it should be relatively straight forward to port uCLinux. > > Cheers, > JonArticle: 112692
Will Dean wrote: > > Just curious - what destination of the second 10-pin connector inside > > of %subject% (JS2)? First one used as external JTAG connector.. > > > > Is there an EPLD in there? (ISTR there is) - if so it's probably for > programming that. Probably. http://www.edaboard.com/files-eboard/4899745lvw_111.jpgArticle: 112693
On a sunny day (Mon, 27 Nov 2006 12:00:20 -0500) it happened Ray Andraka <ray@andraka.com> wrote in <rREah.13$m06.7@newsfe24.lga>: >Jan Panteltje wrote: >> You can also demodulate an FM signal by generating a short fixed length fixed >> amplitude pulse (one shot) on each zero crossing on an output, and then doing >> a lowpass. >> A lot simpler. > >A lot noisier too, I think. No? No, why should it be. You take the sign bit of the ADC, do the xor-delay thingy (basically a oneshot on each zero crossing), and average the output with a lowpass. There are a few issues: 1) You need a stable supply (pulse height). 2) you need a stable pulse length. 3) If no input, then the signal will drop to zero. This is a very classical method, and was used in the first consumer video recorder (Sony Umatic) for FM demodulation of the video. High bandwidth, good quality too. Unfortunately dropouts in the tape caused a huge white spike in the signal. Because it is such a good demodulation method Philips later used it again in the semie prof BVU? helical scans, but they used a trick, had the FM signal sync an oscillator, so if the input was interrupted (tape dropout) that oscillator would run at its own frequency, and that was 'black level'. That was some history. I made a 10GHz wireless video link using this modulation in the seventies. All that said, how would you do it?Article: 112694
burn.sir@gmail.com schrieb: > Thank you for your answer Jon, > > > The JTAG problem was expected, and is easy to fix (write your own JTAG > block). Regarding the MMU, well, I have heard the MB cannot be modified > to include a MMU, is the same true for Mico32? > > > The reason that I posted my previous questions in the first place was > that if you synthesize a Mico32 project with, say, Quartus II you will > notice that it cant fit in _any_ Cyclone II devices. The reason is that > the lm32_ram block is designed in such way that the Quartus synthesizer > cannot infer MK4 blocks... > > > So my question to the list: has _anyone_ tried this CPU on Altera > devices? > > > regards, burns (still waiting for my ECP2M kit) > it works on Xilinx so should also work in A :) AnttiArticle: 112695
http://gpl-violations.org/ Anyway, I fail to see why you need the source code anyway. I suspect that the only person in this list that can make any use of the GCC code is Mr Delorie :) bruns Richard Klingler wrote: > On 2006-11-27 16:30:59 +0100, "Antti" <Antti.Lukats@xilant.com> said: > > > Richard Klingler schrieb: > > > >> EHLO (o; > >> > >> > >> What happened to the nios2 sources which were once accessable > >> via the doc/degree ftp login documented on the Altera website? > >> > >> Unfortunately Altera stopped sponsoring me with Quartus/NIOS > >> for doing core tests and porting cores to sopc builder...so > >> I won't get any more nios2 toolchain sources on CD (o; > >> cheers > >> rick > > > > well if they dont want to violate the GPL license they must provide > > the source codes, like both Xilinx and Lattice do for their soft cpus > > > > Antti > > Aaahh....familiar name (o; > > At least I could win Lattice and Actel for sponsoring design software > and devices. But concentrating on porting to Lattice now as Actel > sended an obsolete evaluation board (o; > > Isn't that with GPL that you only have to give the sources upon > requests if you already bought their product? So basically someone > without a NIOS board the request could be denied? > > > cheers > rickArticle: 112696
No surprise there, Mico32 was Originally _designed_ for Xilinx FPGAs. burns Antti wrote: > it works on Xilinx so should also work in A :) > > AnttiArticle: 112697
burn.sir@gmail.com schrieb: > No surprise there, Mico32 was Originally _designed_ for Xilinx FPGAs. > > > burns > hmm. I had a vision that it wasnt directly originated from Lattice ;) AnttiArticle: 112698
The sources that you are looking for are they the ones that come on the install CDs or the ones described in application note 267 (AN267)? Derek Richard Klingler wrote: > EHLO (o; > > > What happened to the nios2 sources which were once accessable > via the doc/degree ftp login documented on the Altera website? > > Unfortunately Altera stopped sponsoring me with Quartus/NIOS > for doing core tests and porting cores to sopc builder...so > I won't get any more nios2 toolchain sources on CD (o; > > > > cheers > rickArticle: 112699
Al wrote: > Hi to everyone, I'm trying to generate a 5-10 ns pulse width out of an > edge, without the use of any clock, just with internal delays. > Unfortunately I can imagine how much this delay will depend on > temperature and voltage and how much the width will be affected, but > still I have some margins (anyway everything will be tested in a > thermal chamber to verify functionalities). > So far I developed a sort of a "ripple-counter" with an auto-reset for > each FF (Q(0) will asynchronously reset Q(0)) so that I can start an > internal oscillation (a clock!). > After that a normal counter can be realized on the basis of this > clock, allowing to build a pulse. Once the pulse is over a reset is > generated to stop asynchronously all the FFs. I needed a delay to advance an address counter after a bus strobe ended. It was for a CPLD on a small plug-in board, and there was no other need for a clock on the board. So, I routed the signal out one pin, through a 1.5 K Ohm resistor, and into another pin. The input capacitance of the pin became the C of the RC time constant. This has worked well in the application. In your case, taking the signal through a similar external delay, and then bringing it back in to an AND2B1 for a pulse only on the rising edge, or an XOR if you want pulses on both edges should do what you want. Adjust the resistor value to get the desired time delay. It may also be possible to route to an unbonded IO pad with weak drive and get a fair amount of delay, easily 5 ns, but probably not 10. Jon
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