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On Sun, 19 Nov 2006 18:04:13 -0500, Ray Andraka <ray@andraka.com> wrote: >John Larkin wrote: > > >> >> They should back off this religious devotion to fully synchronous >> logic and give us a couple of dozen programmable true delay elements, >> scattered about the chip. But they won't because it's not politically >> correct, and because they figure that we're so dumb that we'd get into >> trouble using them. >> >> >> John >> > >Virtex4 has them. They are the idelay elements, which give you 64 steps >of delay with 75ps granularity. Almost 5 ns! Most cool. JohnArticle: 112301
Antti wrote: > Trevor Coolidge schrieb: > > >>I am working on a design that takes a source-synchronous LVDS bus (8 data >>bits + clock, SDR) at a high speed (250MHz) as the input off a cable. I >>will be using the XC4VLX15 part. I read in the databook about the >>IDELAY/IDELAYCTRL operation that can be used to account for package and >>routing skews. What I don't quite understand is the calibration process. I >>understand the timing (64 taps @ 78.125Mhz with non-accumulating error) and >>how an n-tap delay line works. I just don't understand how to calibrate a >>signal dynamically without an input signal being present. Since my data and >>clock source is external (and I have no idea when data will start) I don't >>understand how the calibration can take place. When the cable is idle, the >>clock line will toggle, but the data lines will all be static. (I do see >>that an idle pattern of FF-00-FF-00... could be handy). When the cable is >>not connected though everything will be 0 - even the clock. >> The other option seems to be the fixed delay approach - then I just need >>to use the static timing analyzer to account for the flight time and routing >>delays so that they all "line-up" right on the balls. The datasheet claims >>a maximum flight-time skew of 80ps for any pin in the device (+/- 1 on the >>tap count). Then, I just need to look up the PAD --> IDELAY.D, divide by >>78ps and add 1 for each of the 8 data bits. Am I missing something? >> >> I can't tell you how many times in my life I wished I could slide the >>clock or data to account for internal chip routing delays. Especially on >>pad to pad delay paths that went through a flip-flop. >> >> This seems too good to be true - so I must be missing something. >> >>Trevor Coolidge > > > Hi Trevor, > > the IDELAY calibrates against 200MHz clock. > there is no need to have any of the IOs toggling or having any signal, > all you need is 200MHz reference clock. In early xilinx docs this > 200MHz was required to come directly from external source, but later > it was relaxed so it is allowed to generat the 200MHz using a DCM. > > Antti > The Idelays can be adjusted at any time once the 200 MHz reference clock is present, however that adjustment just allows you to increment or decrement the delay in 75ps increments. Your training state machine normally should use one of the externally applied signals (clock or data) as a reference to set the delay. Typically, you'd adjust the delay to first find the edges in the incoming signal, then set the delay midway between the edges so that you are centered in the eye. You need the external signal present and switching on every clock cycle in order to do this type of training. If you've got an incoming clock at the same frequency as a clock in the FPGA but at an unknown phase, you can use that incoming clock as the reference (This is the case with QDR memory, for example). If there is not an incoming clock, you may need a training pattern on the data lines to force an alternating 1 -0 pattern to train against.Article: 112302
Hi all, I'm a bit confuse about the Spartan-3E datasheet. How many SRL16 and FDE inside single slice (SLICEM) anyway ? My initial understanding is that it has 2-SRL16E and 2-FDE inside single SLICEM. My design have 2-SRL16E and 2-FDE. The XST said that my design would need : Number of Slices: 1 out of 4656 0% Number of Slice Flip Flops: 2 out of 9312 0% That's weird for me, since I thought I'd need 1-slices only. Could somebody help me ? Thank you very much Regards, -danielArticle: 112303
kunil wrote: > I'm a bit confuse about the Spartan-3E datasheet. How many SRL16 and > FDE inside single slice (SLICEM) anyway ? My initial understanding is > that it has 2-SRL16E and 2-FDE inside single SLICEM. > > My design have 2-SRL16E and 2-FDE. The XST said that my design would > need : > Number of Slices: 1 out of 4656 0% > Number of Slice Flip Flops: 2 out of 9312 0% > > That's weird for me, since I thought I'd need 1-slices only. Until the part nears capacity, par tries to put things in separate slices. But the best way to see what the software has done is to open it with fpga_editor. Alan NishiokaArticle: 112304
I am using cyclone/cyclone II FPGA.I am using 120 delay chains with help of # command in verilog.Problem is 10 channel constitute one channel .12 channels are there.Some delay chains are differing with remaining in delays.How to constraint in FPGA with quartus 6.0 s/w so that all delays will be same for all 12 channels.I am using for DSP applications kumarArticle: 112305
Hi .
Can anyone throw some light on false path and how to determine it
during synthesis.
Article: 112306Hi, I am new to VHDL and working on a clock divider but I don't get 50% duty cycle for all divisors. Can anyone explain me the effect of irregular or non 50% duty cycle clock to digital logic circuits? Thanks in advance BRArticle: 112307
Ray Andraka schrieb: > Antti wrote: > > > Trevor Coolidge schrieb: > > > > > >>I am working on a design that takes a source-synchronous LVDS bus (8 data > >>bits + clock, SDR) at a high speed (250MHz) as the input off a cable. I > >>will be using the XC4VLX15 part. I read in the databook about the > >>IDELAY/IDELAYCTRL operation that can be used to account for package and > >>routing skews. What I don't quite understand is the calibration process. I > >>understand the timing (64 taps @ 78.125Mhz with non-accumulating error) and > >>how an n-tap delay line works. I just don't understand how to calibrate a > >>signal dynamically without an input signal being present. Since my data and > >>clock source is external (and I have no idea when data will start) I don't > >>understand how the calibration can take place. When the cable is idle, the > >>clock line will toggle, but the data lines will all be static. (I do see > >>that an idle pattern of FF-00-FF-00... could be handy). When the cable is > >>not connected though everything will be 0 - even the clock. > >> The other option seems to be the fixed delay approach - then I just need > >>to use the static timing analyzer to account for the flight time and routing > >>delays so that they all "line-up" right on the balls. The datasheet claims > >>a maximum flight-time skew of 80ps for any pin in the device (+/- 1 on the > >>tap count). Then, I just need to look up the PAD --> IDELAY.D, divide by > >>78ps and add 1 for each of the 8 data bits. Am I missing something? > >> > >> I can't tell you how many times in my life I wished I could slide the > >>clock or data to account for internal chip routing delays. Especially on > >>pad to pad delay paths that went through a flip-flop. > >> > >> This seems too good to be true - so I must be missing something. > >> > >>Trevor Coolidge > > > > > > Hi Trevor, > > > > the IDELAY calibrates against 200MHz clock. > > there is no need to have any of the IOs toggling or having any signal, > > all you need is 200MHz reference clock. In early xilinx docs this > > 200MHz was required to come directly from external source, but later > > it was relaxed so it is allowed to generat the 200MHz using a DCM. > > > > Antti > > > > > The Idelays can be adjusted at any time once the 200 MHz reference clock > is present, however that adjustment just allows you to increment or > decrement the delay in 75ps increments. Your training state machine > normally should use one of the externally applied signals (clock or > data) as a reference to set the delay. Typically, you'd adjust the > delay to first find the edges in the incoming signal, then set the delay > midway between the edges so that you are centered in the eye. You need > the external signal present and switching on every clock cycle in order > to do this type of training. If you've got an incoming clock at the > same frequency as a clock in the FPGA but at an unknown phase, you can > use that incoming clock as the reference (This is the case with QDR > memory, for example). If there is not an incoming clock, you may need a > training pattern on the data lines to force an alternating 1 -0 pattern > to train against. correct I was refererring to IDELAYCTRL that is used to calibrate the IDELAY taps to be constant over temperature and process this only requires the 200MHz to present. to actually calibrate the IDELAYs some signal is required on each IOs to compare against with. AnttiArticle: 112308
On 2006-11-17, olson_ord@yahoo.it <olson_ord@yahoo.it> wrote: > Dear Andreas, > Thanks for your reply to this post. I took the time to have a look at > incremental synthesis (for XST) and it seems to be useful only if you > have changed part of your design and want to save resynthesis time. As > far as XST is concerned I am not so much concerned about the run time - > than the Memory consumption. (I only have access to the 32 bit version > so XST can use only 4GB of memory.) XST runs out of memory and then > crashes - that's my problem. It is also possible to synthesize parts of your design and then include that part as presynthesized logic. In this way, XST synthesizes parts of your large design separately. However I don't know how to do that in ISE as I haven't tried to do that myself. The makefiles in the EDK seems to work in that way as well. /AndreasArticle: 112309
Actually i don't have much experinece on fpga design. But in my case, i need send many different Matrix and vectors into FPGA borad, which has been implemented my algorithm many times. That is, everything is same but the data writing into the board. I set the number of trials is 10K. It never finish the operation, in end it stopped on a trial (randomly). If receiver cannot accept any more data, why it not stop on the first trial instead of running some trials. Andrew Holme wrote: > "ZHI" <threeinchnail@gmail.com> wrote in message > news:1163937858.531219.138760@h48g2000cwc.googlegroups.com... > > Andrew Holme wrote: > >> "ZHI" <threeinchnail@gmail.com> wrote in message > >> news:1163783381.788279.19070@j44g2000cwa.googlegroups.com... > >> >I implemented an algorithm into fpga board. I wrote the Matrix data to > >> > FPGA board from Matlab and the result came back. I was using a loop to > >> > execute the operation many times. It can operate normally for some > >> > times, but in the end it stopped with the error in the line : > >> > fwrite(sx,datafile,'int8'); > >> > and the error messege showed : serial.fwrite A timeout occurred during > >> > the write operation. How could it happen? How could it execute some > >> > trials but happen time out error at some time? > >> > > >> > >> Are you using handshaking for flow control? > >I am using hardware for flow control. > Maybe it timed-out because the receiver would not accept any more data.Article: 112310
Hi!, I am developing a complex system and at this moment I would like to test one of its blocks: block_B. This block receives its input signals from a different block_A and a third one: block_C controls the hold_inputs of each flip-flop contained in the block_B. When I prepare the test_bench with the "test bench waveform tool", my doubt comes when I have to model the behaviour of the hold_input which feeds the block_B. The test bench waveform asks me for inserting the "input setup time" and I notice that the Xilinx tool consider the "hold_input" an input from one IOB which is not true. If I insert a 0 (zero) into the "input setup time" box I have an error in the simulation since there is an "high VIOLATION ON CE WITH RESPECT TO CLK", so I understand that I have to increase the value of that time but, How much? My question is: How do I have to model the inputs coming from other blocks of the system (not from IOBs), like "hold_input" from block_C or "input signals" from block_A?. Thanx Jajo.Article: 112311
I can't seem to find a document that calls out the XY locations for the IDELAYCTRL. Where is this information found? When I don't use the LOC, the report for P&R says it has used 100% of the IDELAYCTRLs. No surprize. When I look at the FPGA editor I would expext to see all of them listed but instead I only see a small portion of them. Why? It appears that if I include an IDELAY that there is some sort of requirement on where the IDELAYCTRL is located. Currently I don't use the LOC, let the tool P&R then use the FPGA editor to see where it placed it. Then I use the LOC. What a pain. There must be a simpler way. I tell the tools where the IDELAY is to be used, why is it that the tools can't place the controller automatically? If I select the wrong location for the IDELAYCTRL, the tool does not flag an error, the design just fails to work. You would think it would be smart enough to know.Article: 112312
<bhavanireddy@gmail.com> wrote in message news:1164004931.830237.322220@e3g2000cwe.googlegroups.com... > Hi, > > I am new to VHDL and working on a clock divider but I don't get 50% > duty cycle for all divisors. Can anyone explain me the effect of > irregular or non 50% duty cycle clock to digital logic circuits? If you use the rising edge of the clock exclusively (as is generally the case with most synchronous designs) then duty cycle of the clock is irrelevant as long as the 'high time' and 'low time' also meet the specs for the part that you're using. If you use both rising and falling edges of the clock then duty cycle is very important since it directly impacts the time between the rising and falling edges. KJArticle: 112313
jajo wrote: > Hi!, > > I am developing a complex system and at this moment I would like to > test one of its blocks: block_B. This block receives its input signals > from a different block_A and a third one: block_C controls the > hold_inputs of each flip-flop contained in the block_B. > > When I prepare the test_bench with the "test bench waveform tool", my > doubt comes when I have to model the behaviour of the hold_input which > feeds the block_B. The test bench waveform asks me for inserting the > "input setup time" and I notice that the Xilinx tool consider the > "hold_input" an input from one IOB which is not true. If I insert a 0 > (zero) into the "input setup time" box I have an error in the > simulation since there is an "high VIOLATION ON CE WITH RESPECT TO > CLK", so I understand that I have to increase the value of that time > but, How much? > > My question is: How do I have to model the inputs coming from other > blocks of the system (not from IOBs), like "hold_input" from block_C or > "input signals" from block_A?. Hopefully you are not trying to do a timing simulation until you have completed a logic simulation. Timing is typically analyzed with a static timing analysis on the routed design. But there is little point in doing this before you have a completed chip design other than as a cursory check. This is because the timing will change each time you Place & Route. As more of the chip is used the timing typically gets worse. So initially each module should meet it timing constraints easly. This may not show in a timing analysis because the tool routes to meet timing, not to exceed it. The first thing you need to do is a logic simulation where you don't worry about the timing at all. This makes it easier to focus on getting the logic correct. Once the logic is right you can worry about timing. When you simulate a design for an FPGA, it typically assumes your external inputs are I/Os. I have never used the test bench toll you are describing, I have always written my own test bench code. Just give the tool what it needs to work without error. How much actual setup and hold time you need in your real design depends on how you are designing your module interfaces. Typically you might put FFs at each of the module outputs, or possibly the inputs, but this is a design decision and you might not have FFs on either of the modulel IOs depending on what you are doing. Where you do have FFs, you would use the data sheet setup and hold times for the FF.Article: 112314
For some reason, I'm not getting how to create the various .mif files to initialize enhanced PLLs with Quartus II. I'm trying to target a Stratix II device. The situation that I'm in will require me to reconfigure the PLL's divisors dependent upon the state of an input pin on the FPGA. Anyone got a step-by-step set of instructions that cleary describe how to do this?Article: 112315
It's about a year that Spartan3E are on the market but i am still confused on pricing. On: http://www.xilinx.com/products/spartan3e/faq105-sp3e.pdf xilinx states that XC3S1200E is less than $9. On the major distributors (Nu Horizons, Avnet) the same part goes for about $45. Is $9 a marketing thing only, or is there any chance that quantity prices will drop to that level ? tullioArticle: 112316
Hi,
I want to convert a differential digital signal to single ended
signal.
But, because of skew, the positive and negative signals are not exactly
complementary, but will have some difference in pulse widths. So the
pulse widths in single ended o/p should be (pw1+pw2)/2.
In spartan fpga, the global buffer IBUFDS converts from differential to
sihgle ended but the truth table tells that
i/p-p i/p-n o/p
0 1 --------->0
1 0----------->1
0 0-----------------> no change
1 1------------> no change
So is there any other way to generate this w/f?
Thanks and Regards,
prathap
Article: 112317tullio schrieb: > It's about a year that Spartan3E are on the market but i am still > confused on pricing. > On: http://www.xilinx.com/products/spartan3e/faq105-sp3e.pdf xilinx > states that > XC3S1200E is less than $9. > > On the major distributors (Nu Horizons, Avnet) the same part goes for > about $45. > Is $9 a marketing thing only, or is there any chance that quantity > prices will drop to that level ? > > tullio did you ask quote for 500,000 pieces single order? its clearly stated this is possible price for 0.5M pieces orders only. for smaller orders you may be able to get the price down to around $20 USD slowest speed cheapest package, but dont expect prices below that unless you are really buyins millions of pieces. AnttiArticle: 112318
kunil wrote: > Hi all, > > I'm a bit confuse about the Spartan-3E datasheet. How many SRL16 and > FDE inside single slice (SLICEM) anyway ? My initial understanding is > that it has 2-SRL16E and 2-FDE inside single SLICEM. > > My design have 2-SRL16E and 2-FDE. The XST said that my design would > need : > Number of Slices: 1 out of 4656 0% > Number of Slice Flip Flops: 2 out of 9312 0% > > That's weird for me, since I thought I'd need 1-slices only. > > Could somebody help me ? > > Thank you very much > > Regards, > -daniel There are restrictions on whether an SRL can pack with a register. Since you specify an FDE, you *should* have those restrictions basically taken care of; the SRL write enable and register enable are different signals and the FDE doesn't use a reset. It may just be the tool chose to spread things out. I've had to use the RLOC or other constraint to pack my output registers with my SRLs at times. The tools don't always make the "best" decisions but you can usually get them to do what you need in the critical paths through further constraints.Article: 112319
Parallax, the company that makes those nifty little BASIC stamps, is (or was) selling off the last of the Cyclone and Stratix "Fast/Smartpack" boards. These are pretty utilitarian boards, with a custom serial programmer & configuration system, a serial line driver, a clock oscillator, and a handful of LED's. They would have been great for embedding in projects had they not been so ridiculously expensive. It's a shame, really; as I liked the minimalist approach of just provididing I/O and basic configuration / clock circuitry. At any rate, I bought one of the closeout Stratix Smartpacks with a EP1S10 on eBay for $76. I'm curious to know if any add-on boards were developed for these? Perhaps a "mainboard" with a bit of RAM, ethernet, etc?Article: 112320
Hello, What you expected is what the report said. I think you may have misunderstood it. It has used 1 out of 4656 slices. The "Slice Flip Flops" count is count of how many flip flops were used in your 1 slice. The report could be a bit more clear, I think in the mapper report, this relationship is more obvious due to the use of indentation in the text. Eric "kunil" <kunilkuda@gmail.com> wrote in message news:1163982590.481863.272520@b28g2000cwb.googlegroups.com... > Hi all, > > I'm a bit confuse about the Spartan-3E datasheet. How many SRL16 and > FDE inside single slice (SLICEM) anyway ? My initial understanding is > that it has 2-SRL16E and 2-FDE inside single SLICEM. > > My design have 2-SRL16E and 2-FDE. The XST said that my design would > need : > Number of Slices: 1 out of 4656 0% > Number of Slice Flip Flops: 2 out of 9312 0% > > That's weird for me, since I thought I'd need 1-slices only. > > Could somebody help me ? > > Thank you very much > > Regards, > -daniel >Article: 112321
When I try to open the XST properties dialog box in ISE, the box appears but the options don't (i.e. an empty box). Has anyone else had this problem? If so is there a solution? TIA, Rog.Article: 112322
John, "John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message news:1ejvl2d3j9tj96emac307rtjfr2l4o40q1@4ax.com... > They should back off this religious devotion to fully synchronous > logic and give us a couple of dozen programmable true delay elements, > scattered about the chip. But they won't because it's not politically > correct, and because they figure that we're so dumb that we'd get into > trouble using them. I think the real problems are that: 1) It'd be difficult (read: expensive) for them to provide reasonably accurate delay elements. With synchronous design, they just add a ring oscillator somewhere and empirically determine how fast the thing will run, bin them accordingly, and they're done! For delay elements... well, what are the options? Laser trimming? Non-volatile tapped delay lines? Nothing that I can think of that's dirt cheap. 2) You're correct, they do figure that "you" [as a whole] will get into trouble using them. You -- personally -- clearly won't, but if you're running a business it's clearly useful (to your bottom line!) to set up the system so that you try to protect people who don't know what they're doing from blowing their feet off. That being said, this approach is often taken too far to not only keep a couple of the more advanced "doors" closed, but to put locks on them altogether. I've seen software development tools go this route as well -- they're perhaps improved and easier to use for novices, but actually harder and less functional for experts. These days I have to hold my tongue rather than go around claiming things aren't "expert friendly," because it is seen as an attack somehow on the less-than-expert users. That's where the political correctness BS comes into play!Article: 112323
"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message news:0if1m2hfi8eqchditu8552pudqrkff2c7u@4ax.com... > I toured the Cornell EE department recently. 95% of the screens are on > PC's, maybe 5% are oscilloscopes. No soldering irons in sight, just > those drecky white plastic breadboards. I think solderless breadboards are great when you aren't doing anything particularly fast or high-speed -- they really do improve productivity. There are many commercial microcontroller designs out there that you could still fully "design" on one. Obviously the kind of stuff you do wouldn't be applicable to solderless breadboard design... Solderless breadboards are probably one of the mediums where it really is excess capacitance rather than inductance that keeps a design slow. :-) > Tulane, my alma mater, used > Katrina as an excuse for eliminating the EE department entirely. I > guess those labs are too expensive, compared to one TA teaching 400 > kids art history in a lecture hall, all at once. When I was an undergraduate we already has labs where the professor was shown on a videotape at the beginning of the lab. A TA would then "help" with getting the labs working, although some of them were of course much more useful than others (the guys doing their theses on, e.g., optimizing compilers weren't much help getting photodiode amplifiers going... I wonder if Phil Hobbs was ever a TA? That would have been cool...) I had some control systems lab where we designed temperature controlled ovens -- I left my soldered-together controller there for the TAs to use as the "golden model" since it didn't have the long-term reliability problems the prior solderless breadboards versions did! ---JoelArticle: 112324
<pbdelete@spamnuke.ludd.luthdelete.se.invalid> wrote in message news:4560c4d3$0$486$cc7c7865@news.luth.se... > I heard an interesting comment once, students are not to be trusted with > untyped languages because they can't handle it. STILL same persons are > expected to handle advanced math with pen & paper.. ...and the computer-algebra system running on their calculators! I hope that the "students are not to be trusted with untyped languages" idea is universal; I'd be shocked if there weren't universities where, e.g., Python isn't being used on a regular basis. (If John Larkin wasn't already quite so fond of PowerBasic I'd suggest he'd probably really like Python...)
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