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I am using xilinx xup virtex2 pro Dev system board, and I am trying to communicate 2 boards together, using chipscope, in the pro analyzer window when I apply settings and arm the trigger I notice that the waveform window is waiting for upload and it stays that way, what does that mean and how to take care of this problem. Thank you nanaArticle: 114051
Tim wrote: > smount wrote: > >> Does anyone know what is needed to work with surface mount >> ic's, what sort of starting price tag are we talking about? >> (Assuming I have ready made boards, i.e. only the soldering >> phase is required) > > > Prices drop all the time, but last time I checked: > > $500 to $800 for a decent stereo microscope (you need approx x4 to x10 > mag) with zoom, illumination, a boom arm, and a very heavy base. You want one with a very large "working distance" so you can get your hands under there, and a large "throat" meaning the objective lens is well away from the vertical support for the microscope head. There is a VERY common stereo microscope in the US $300 range that is quite UNsuitable for this purpose, for the two reasons mentioned above. I'd check eBay for use Bausch & Lomb, Olympus, Zeiss, etc. microscopes with relatively LOW magnification. 10 - 20 X is what you want, and if you can get the low-mag eyepieces or the accessory lens to cover the 5 - 10 X range, that may be best. > JonArticle: 114052
Hello, I start playing with a Spartan 3 demo board. I want to program a 8 bits counter with one button that increments the counter, one button that decrements the counter and one reset button that erases the counter. Output of the counter is connected to the 8 leds. Here is the very naive code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity test is port ( inc: in std_logic; dec: in std_logic; reset: in std_logic; led_value: out std_logic_vector(7 downto 0) ); end test; architecture Behavioral of test is begin process (inc, dec, reset) variable counter_value: std_logic_vector(7 downto 0); variable flag_inc: std_logic; variable flag_dec: std_logic; begin if (reset='1') then counter_value := "00000000"; flag_inc := '0'; flag_dec := '0'; end if; if (inc='1' and flag_inc='0') then flag_inc := '1'; counter_value := counter_value + 1; end if; if (dec='1' and flag_dec='0') then flag_dec := '1'; counter_value := counter_value - 1; end if; if (inc='0') then flag_inc := '0'; end if; if (dec='0') then flag_dec := '0'; end if; led_value <= counter_value; end process; end Behavioral; The reset button seems to work, but not the dec and inc buttons. When I push the dec or inc button there are some activities on the leds but nothing like an increment or a decrement by one. Thanks for your help ... OlivierArticle: 114053
This is a V4FX60 design using one of the PowerPCs and one of the EMACs. The mapper uses the EMAC that has hard connections to the other PowerPC. Therefore the EMACDCR and DCREMAC produce "unroutable" errors. Is it possible to constrain the EMAC to a specific location?Article: 114054
I suppose you have bouncing contacts (all mechanical contacts bounce) which makes every contact closure appear as a sequence of multiple closures. Unless your contacts are "single-pole-double-throw", you need to add a delay that ignores subsequent closures for a certain time, say 100 ms. That may require a long binary counter. To learn good digital habits, I suggest you design the delay as a 20 to 24 bit 50 MHz counter, which is trivial in modern FPGAs. Your up and down switches can share a common counter, and the reset switch is allowed to bounce as much as it wants to. Peter Alfke, Xilinx Applications On Jan 3, 1:17 pm, Olivier Scalbert <olivier.scalb...@algosyn.com> wrote: > Hello, > > I start playing with a Spartan 3 demo board. > I want to program a 8 bits counter with one button that increments the > counter, one button that decrements the counter and one reset button > that erases the counter. Output of the counter is connected to the 8 leds. > > Here is the very naive code: > > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > use IEEE.STD_LOGIC_ARITH.ALL; > use IEEE.STD_LOGIC_UNSIGNED.ALL; > > ---- Uncomment the following library declaration if instantiating > ---- any Xilinx primitives in this code. > --library UNISIM; > --use UNISIM.VComponents.all; > > entity test is > port ( > inc: in std_logic; > dec: in std_logic; > reset: in std_logic; > led_value: out std_logic_vector(7 downto 0) > ); > end test; > > architecture Behavioral of test is > begin > process (inc, dec, reset) > variable counter_value: std_logic_vector(7 downto 0); > variable flag_inc: std_logic; > variable flag_dec: std_logic; > begin > if (reset='1') then > counter_value := "00000000"; > flag_inc := '0'; > flag_dec := '0'; > end if; > > if (inc='1' and flag_inc='0') then > flag_inc := '1'; > counter_value := counter_value + 1; > end if; > > if (dec='1' and flag_dec='0') then > flag_dec := '1'; > counter_value := counter_value - 1; > end if; > > if (inc='0') then > flag_inc := '0'; > end if; > > if (dec='0') then > flag_dec := '0'; > end if; > > led_value <= counter_value; > > end process; > > end Behavioral; > > The reset button seems to work, but not the dec and inc buttons. When I > push the dec or inc button there are some activities on the leds but > nothing like an increment or a decrement by one. > Thanks for your help ... > > OlivierArticle: 114055
Are you coming from a software background? Electronics hobbyist? First, buttons need to be understood. The mechanical reality of switches is that they bounce. The contacts don't physically go from 100% open to 100% closed and back reliably. To accommodate the bounce, analog or digital "debounce" circuits are used to give you one event for one action. Second, modern digital electronics work well with a single system clock that takes inputs from the outside world through synchronizing blocks such that each input event is seen in the system clock domain as a single event, much like the debounce; this is most important when many changes occur at the same time such as when 8 commuters (one byte of information) are trying to enter a train at the same time the doors (system clock) are closing (hitting the posedge). Not every commuter can get on the train if they all show up right when the door closes. A system clock will allow the design to see a switch transition and lock out a change in that switch until a specified time goes by. The counter - which wants a single clock - will then have the ability to go up or down depending on the debounced switch settings once per switch press. It almost sounds like when I wanted to do a simple Microsoft Windows program (having done much command-line stuff before) and had to deal with all the infrastructure to produce the windows and their somewhat involved behavior. But at least the nuances in electronics are fewer. Switch debounce for digital circuits is usually one of the first lessons. - John_H "Olivier Scalbert" <olivier.scalbert@algosyn.com> wrote in message news:459c1d57$0$5521$ba620e4c@news.skynet.be... > Hello, > > I start playing with a Spartan 3 demo board. > I want to program a 8 bits counter with one button that increments the > counter, one button that decrements the counter and one reset button that > erases the counter. Output of the counter is connected to the 8 leds. > > Here is the very naive code: > > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > use IEEE.STD_LOGIC_ARITH.ALL; > use IEEE.STD_LOGIC_UNSIGNED.ALL; > > ---- Uncomment the following library declaration if instantiating > ---- any Xilinx primitives in this code. > --library UNISIM; > --use UNISIM.VComponents.all; > > entity test is > port ( > inc: in std_logic; > dec: in std_logic; > reset: in std_logic; > led_value: out std_logic_vector(7 downto 0) > ); > end test; > > architecture Behavioral of test is > begin > process (inc, dec, reset) > variable counter_value: std_logic_vector(7 downto 0); > variable flag_inc: std_logic; > variable flag_dec: std_logic; > begin > if (reset='1') then > counter_value := "00000000"; > flag_inc := '0'; > flag_dec := '0'; > end if; > > if (inc='1' and flag_inc='0') then > flag_inc := '1'; > counter_value := counter_value + 1; > end if; > > if (dec='1' and flag_dec='0') then > flag_dec := '1'; > counter_value := counter_value - 1; > end if; > > if (inc='0') then > flag_inc := '0'; > end if; > > if (dec='0') then > flag_dec := '0'; > end if; > > led_value <= counter_value; > > end process; > > end Behavioral; > > The reset button seems to work, but not the dec and inc buttons. When I > push the dec or inc button there are some activities on the leds but > nothing like an increment or a decrement by one. > Thanks for your help ... > > Olivier >Article: 114056
Jeff Cunningham wrote: > This may be of interest: > http://groups.google.com/group/comp.arch.fpga/browse_thread/thread/9af5a3a80c9ae87/f47a83956ec2ac3f?lnk=st&q=&rnum=4&hl=en#f47a83956ec2ac3f > http://www.enterpoint.co.uk/techitips/OPB_RAM3.VHD > take the above file through the import IP wizard, tell it you have a OPB > slave interface, and map the IOs to OPB signals as appropriate. I was > able to make this compile and route painlessly, though I haven't tested > it out by actually running it. Thanks for the code, Jeff. I inserted it and it did indeed compile. But as you say it's not been debugged and I'd have to modify for my purposes. I'll keep it on hold for now. TomArticle: 114057
John_H wrote: > Are you coming from a software background? Electronics hobbyist? > > First, buttons need to be understood. The mechanical reality of switches is > that they bounce. The contacts don't physically go from 100% open to 100% > closed and back reliably. To accommodate the bounce, analog or digital > "debounce" circuits are used to give you one event for one action. > > Second, modern digital electronics work well with a single system clock that > takes inputs from the outside world through synchronizing blocks such that > each input event is seen in the system clock domain as a single event, much > like the debounce; this is most important when many changes occur at the > same time such as when 8 commuters (one byte of information) are trying to > enter a train at the same time the doors (system clock) are closing (hitting > the posedge). Not every commuter can get on the train if they all show up > right when the door closes. > > A system clock will allow the design to see a switch transition and lock out > a change in that switch until a specified time goes by. The counter - which > wants a single clock - will then have the ability to go up or down depending > on the debounced switch settings once per switch press. > > It almost sounds like when I wanted to do a simple Microsoft Windows program > (having done much command-line stuff before) and had to deal with all the > infrastructure to produce the windows and their somewhat involved behavior. > But at least the nuances in electronics are fewer. Switch debounce for > digital circuits is usually one of the first lessons. > > - John_H > A typical switch will bounce for a few tens to a few thousands of hits, depending on the switch and other circuitry (a small cap works wonders but will not eliminate the bounce). As to those numbers, I have measured them - one particularly bad switch gave me over 2000 hits on a switch event. Perhaps the OP needs to learn some electronics basics (suggestion : post to s.e.b. asking about switch bounce and possible solutions) Cheers PeteS > > "Olivier Scalbert" <olivier.scalbert@algosyn.com> wrote in message > news:459c1d57$0$5521$ba620e4c@news.skynet.be... >> Hello, >> >> I start playing with a Spartan 3 demo board. >> I want to program a 8 bits counter with one button that increments the >> counter, one button that decrements the counter and one reset button that >> erases the counter. Output of the counter is connected to the 8 leds. >> >> Here is the very naive code: >> >> library IEEE; >> use IEEE.STD_LOGIC_1164.ALL; >> use IEEE.STD_LOGIC_ARITH.ALL; >> use IEEE.STD_LOGIC_UNSIGNED.ALL; >> >> ---- Uncomment the following library declaration if instantiating >> ---- any Xilinx primitives in this code. >> --library UNISIM; >> --use UNISIM.VComponents.all; >> >> entity test is >> port ( >> inc: in std_logic; >> dec: in std_logic; >> reset: in std_logic; >> led_value: out std_logic_vector(7 downto 0) >> ); >> end test; >> >> architecture Behavioral of test is >> begin >> process (inc, dec, reset) >> variable counter_value: std_logic_vector(7 downto 0); >> variable flag_inc: std_logic; >> variable flag_dec: std_logic; >> begin >> if (reset='1') then >> counter_value := "00000000"; >> flag_inc := '0'; >> flag_dec := '0'; >> end if; >> >> if (inc='1' and flag_inc='0') then >> flag_inc := '1'; >> counter_value := counter_value + 1; >> end if; >> >> if (dec='1' and flag_dec='0') then >> flag_dec := '1'; >> counter_value := counter_value - 1; >> end if; >> >> if (inc='0') then >> flag_inc := '0'; >> end if; >> >> if (dec='0') then >> flag_dec := '0'; >> end if; >> >> led_value <= counter_value; >> >> end process; >> >> end Behavioral; >> >> The reset button seems to work, but not the dec and inc buttons. When I >> push the dec or inc button there are some activities on the leds but >> nothing like an increment or a decrement by one. >> Thanks for your help ... >> >> Olivier >> > >Article: 114058
Hi everyone:
I am new to FPGA and looking for a possible topic on FPGA routing
algrithm. I read some classic articals in this field and find that when
people are talking about routing algrithms (i.e. pathfinder) they
generally ignore the architecture of switch box, while it is said that
the topology of swich box may have an impact on the routability on the
router. Thus, I am wondering how the router determine the path inside
the switch box? And I am thinking is it possible to add the routing
cost on the switch box to the cost function to the pathfinder algrithm?
I am totally new to the FPGA and its routing. I hope the above
question may not be so naive. And I am still not sure which topic in
this area is worthy to do. I appreciate if anyone give me some advice.
Thanks and happy new year.
Ruiz
TAMU
Article: 114059Ruiz, please tell us what you intend to do. There are literally hundreds of design engineers at Xilinx, Altera,and Lattice exploring this particular subject, not to mention the researchers at several universities. I do not want to sound too discouraging, but: This is a well-plowed field... Peter Alfke On Jan 3, 3:20 pm, "Ray" <ryan1...@gmail.com> wrote: > Hi everyone: > I am new to FPGA and looking for a possible topic on FPGA routing > algrithm. I read some classic articals in this field and find that when > people are talking about routing algrithms (i.e. pathfinder) they > generally ignore the architecture of switch box, while it is said that > the topology of swich box may have an impact on the routability on the > router. Thus, I am wondering how the router determine the path inside > the switch box? And I am thinking is it possible to add the routing > cost on the switch box to the cost function to the pathfinder algrithm? > > I am totally new to the FPGA and its routing. I hope the above > question may not be so naive. And I am still not sure which topic in > this area is worthy to do. I appreciate if anyone give me some advice. > > Thanks and happy new year. > > Ruiz > TAMUArticle: 114060
something like this: INST "ll_temac_0/ll_temac_0*v4_emac" LOC = "EMAC_X0Y1" ;Article: 114061
There is no problem with the PPC405 caches in Virtex-4, i.e. they work as expected. CPU errata 213 does not apply to the PPC405 in V4 as you can see in Table 1 (pg. 2) of the errata document you are refering to. Setting bits 1 and 3 in CCR0 was needed in early silicon (PVR 0x20011430) to work around a problem that was fixed in production silicon (PVR 0x20011470). The workaround is enabled automatically by the boot code used by XPS and is transparent to the user. > Actually I need caching for some 10MB of DDR memory. How to specfy this > in XCache_EnableXCache() ? XCache_EnableDCache(0x80000000) and XCache_EnableDCache(0x80000000) enables the instruction and data caches for the first 128MB [0..0x07ffffff] of memory. Cheers, - PeterArticle: 114062
As an example of a simple PLB master you can look at the PLB TFT controller which ships as part of the reference designs for most of the Xilinx boards (for example http://www.xilinx.com/products/boards/ml403/files/ml403_emb_ref_ppc_81.zip). It is a read-only master sitting on the PLB and fetching pixels from a framebuffer in main memory. The control interface is through DCR. Building a master device for the PLB is in general simpler than building a slave device as the signaling is more straight-forward. - Peter Jeff Cunningham wrote: > Rick North wrote: > >> Hi all, >> >> I want to load my PPC program in an external SRAM connected to the PLB >> bus on the PPC. But I fail to find any suitable IP with in EDK. For now >> I have bypassed the PPC and use a mux which either lets the PPC control >> the SRAM or the FPGA fabric. Since the program gets loaded at start up >> the PPC is hold in reset until the program is loaded. >> >> However, I would like to have a general PLB master function which can >> access the PPC address space from the FPGA fabric. Does such an IP >> exist or am I missing something about EDK IPs which makes this >> possible? > > > I am in the same boat - i.e. I have the need to develop a master PLB > interface for my own FPGA fabric logic. From what I have gathered so > far, there is a PLB IPIF type component. However, I tend to agree with > some on this NG who question how useful that really is - you still need > to understand how the client side IPIF interface works, it takes up > logic and will probably not be optimized for your application. At the > end of the day, it may be better to just bite the bullet and read the > PLB coreconnect spec and whip up your own interface with just the > functionality you need. > > What I am unclear on is what type of simulation models are available for > helping me debug my own interface design. I just have Modelsim Xilinx > Edition (not PE or EE). I haven't been able to get a clear picture of > what is available for MXE. I have seen reference to bus functional > models, but I think you need the outrageously expensive version of > Modelsim to run it - can anybody verify whether this is true? > > For your booting problem, could you allocate one or two block rams to > hold a PPC bootloader? The bootloader could read your flash or wherever > your code comes from using the DCR bus or something and initialize your > external big RAM space that way. > > -JeffArticle: 114063
cpmetz@googlemail.com wrote: > currently I think they should have left the caches out. This would have been a really bad idea. Everything would go so slowly, and the caches take up a tiny amount of area compared to an equivalent number of blockrams. > In my design > (something with MPMC, some local-link-DMA's and Gig-Ethernet), > everytime I activate the instruction caches I get Program-Exceptions > (jump to offset 0x700 in the vector table), sporadic resets and so on. > I suspect that in my case the I-side plb (also taken from the > mpmc-example) is too aggresive for the cache. Or whatever. Tried > everything mentioned in the erratas... Sometimes it gets better, > sometimes not... Played around with priorities in the MPMC... If you disable the caches you will also change how the processor interacts with the PLB bus. With caches disabled there will be no bursting on the bus. With caches enabled some (or in some modes all) transactions will result in bursting an entire cacheline. I would suspect the problem has much more to do with the memory controller - possibly it won't do a burst read correctly in all circumstances (i.e. design flaw). The timings may not be set correctly. The next possibility is a power distribution or signal integrity problem. With the cache enabled you will be operating the dram in a burst mode which will both increase noise and power draw. Maybe there isn't enough margin in the design. If you want to test the memory controller, disable the Icache, enable the Dcache in an appropriate mode, and write a memory test that is guaranteed to force burst reads at addresses that will result in continually reloading the same cacheline with different data. You will have to look at the data sheet for the processor to determine the cacheline to physical address mapping. What you pick for the data will allow you to determine where/what the problem is. You should be able to pick patterns that will allow you to determine if the memory controller won't burst on the PLB side, or the external port, and whether the timings are marginal or not. These problems aren't fun to track down. Before getting too carried away I would suggest that you look at the setup of the clock tree and phases of the clocks/data. If the controller works reliably in single transfers, but not bursts, it could be an insufficient hold time, as the bus will capacitively hold the data if it is not being overwritten. Looking at the address/data patterns that make the memory tests fail can give good insight. I can second the voice of Peter Ryser from Xilinx, the caches do work in V4, even with ES silicon. Regards, Erik. --- Erik Widding President Birger Engineering, Inc. (mail) 100 Boylston St #1070; Boston, MA 02116 (voice) 617.695.9233 (fax) 617.695.9234 (web) http://www.birger.comArticle: 114064
Hi Peter:
Thanks for your reply.
Do you mean there is not much to do in the FPGA routing? I have some
interests in FPGA and hope to work in this field in future. But I am
not sure which topics people are working at in this field nowadays. (Or
which topic may help me find a good job in this field when I graduate.)
The lab I am in is mainly concerned with VLSI algorithm, that is why I
first looked into the routing algorithm in FPGA.
Can you please give me some advice or show me where to find such
kind of infomation.
Thanks
Ruiz.
On Jan 3, 5:37 pm, "Peter Alfke" <p...@xilinx.com> wrote:
> Ruiz, please tell us what you intend to do.
> There are literally hundreds of design engineers at Xilinx, Altera,and
> Lattice exploring this particular subject, not to mention the
> researchers at several universities.
> I do not want to sound too discouraging, but: This is a well-plowed
> field...
> Peter Alfke
>
> On Jan 3, 3:20 pm, "Ray" <ryan1...@gmail.com> wrote:
>
> > Hi everyone:
> > I am new to FPGA and looking for a possible topic on FPGA routing
> > algrithm. I read some classic articals in this field and find that when
> > people are talking about routing algrithms (i.e. pathfinder) they
> > generally ignore the architecture of switch box, while it is said that
> > the topology of swich box may have an impact on the routability on the
> > router. Thus, I am wondering how the router determine the path inside
> > the switch box? And I am thinking is it possible to add the routing
> > cost on the switch box to the cost function to the pathfinder algrithm?
>
> > I am totally new to the FPGA and its routing. I hope the above
> > question may not be so naive. And I am still not sure which topic in
> > this area is worthy to do. I appreciate if anyone give me some advice.
>
> > Thanks and happy new year.
>
> > Ruiz
> > TAMU
Article: 114065On Tue, 2 Jan 2007 10:14:21 -0000, "Symon" <symon_brewer@hotmail.com> wrote: >p.s. On the subject of US vs. UK toasting techniques, IMO the problem in the >US is not the toaster machines, it's the post-toasting technology. The toast >just gets piled up on a plate. The US seems to be a veritable toast rack >desert, so the toast always ends up soggy. I guess that's why it's IHOP and >not IHOT! :-) We are an odd country: as you've suggested, we have very poor post-toasting technology, but we do have a cereal called Post Toasties. No one can explain this. Bob Perlman Cambrian Design Works http://www.cambriandesign.comArticle: 114066
Symon wrote:
>
> But I can't find any of these:-
> http://images.google.com/images?hl=en&q=toast+rack
> which greatly enhance the toast experience!
>
Many thanks for that wonderful link, which has led me to the ultimate
British Toasting Experience, a Wallace and Gromit Toast Rack:
http://www.aardmarket.com/wg/productdetail.php?number=A6490
Sadly, they have chosen not to bundle a free Toast-O-Matic
jelly applicator with each purchase.
Brian
p.s. As an added bonus, I discovered these newer W&G shorts
while looking for online video of the jelly launcher in action:
http://video.google.com/videoplay?docid=877124040670507488&q=wallace+and+gromit
From dave@comteck.com Wed Jan 03 21:16:30 2007
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From: Dave <dave@comteck.com>
Subject: Re: xilinx spi example under linux
Date: Thu, 04 Jan 2007 00:16:30 -0500
User-Agent: Pan/0.14.2 (This is not a psychotic episode. It's a cleansing moment of clarity.)
Message-Id: <pan.2007.01.04.05.16.30.867499@comteck.com>
Newsgroups: comp.arch.fpga
References: <459c0269$0$8961$4c368faf@roadrunner.com> <enhh4e$2ss1@cnn.xsj.xilinx.com>
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On Wed, 03 Jan 2007 16:17:27 -0800, Peter Ryser wrote:
> In the attachment find a small program that works with Linux 2.4 and
> read/writes the SPI EEPROM on the Xilinx ML300 board.
Was there really an attachment to this? If so, my newsreader must be
doing funny things.
~Dave~
Article: 114067Ray wrote: > Hi Peter: > Thanks for your reply. > Do you mean there is not much to do in the FPGA routing? I have some > interests in FPGA and hope to work in this field in future. But I am > not sure which topics people are working at in this field nowadays. (Or > which topic may help me find a good job in this field when I graduate.) > The lab I am in is mainly concerned with VLSI algorithm, that is why I > first looked into the routing algorithm in FPGA. > Can you please give me some advice or show me where to find such > kind of infomation. > Thanks > > Ruiz. > > > > On Jan 3, 5:37 pm, "Peter Alfke" <p...@xilinx.com> wrote: > > Ruiz, please tell us what you intend to do. > > There are literally hundreds of design engineers at Xilinx, Altera,and > > Lattice exploring this particular subject, not to mention the > > researchers at several universities. > > I do not want to sound too discouraging, but: This is a well-plowed > > field... > > Peter Alfke > > > > On Jan 3, 3:20 pm, "Ray" <ryan1...@gmail.com> wrote: > > > > > Hi everyone: > > > I am new to FPGA and looking for a possible topic on FPGA routing > > > algrithm. I read some classic articals in this field and find that when > > > people are talking about routing algrithms (i.e. pathfinder) they > > > generally ignore the architecture of switch box, while it is said that > > > the topology of swich box may have an impact on the routability on the > > > router. Thus, I am wondering how the router determine the path inside > > > the switch box? And I am thinking is it possible to add the routing > > > cost on the switch box to the cost function to the pathfinder algrithm? > > > > > I am totally new to the FPGA and its routing. I hope the above > > > question may not be so naive. And I am still not sure which topic in > > > this area is worthy to do. I appreciate if anyone give me some advice. > > > > > Thanks and happy new year. > > > > > Ruiz > > > TAMU Perhaps you are familiar with the VLSI EDA "DAC" conference, I used to go to it eons ago (when FPGAs almost didna exist yet), since then they must have presented a few papers on FPGA EDA too. Check out this and other conferences in the FPGA, EDA field start with IEEE or ACM. Also if you visit the DAC website or go to one of the shows floor exhibits you can see who the hardware vendors are for accelerating EDA, usually with the most expensive FPGAs hidden in big box, some of them must be still around, used to be lots of them. Also just google back through this NG, this question pops up regularly. John JaksonArticle: 114068
Hai Hans...
Thanks for the reply..One more doubt..Is there is any tool
provided by Xilinx..?
regards
subin
Hans wrote:
> "subint" <subin.82@gmail.com> wrote in message
> news:1167456641.853139.193370@s34g2000cwa.googlegroups.com...
> > Hi,
> > i would like to know is there is any tools available from
> > xilinx or other to split the design into multiple fpga and
> > synthesize...
>
> Have a look at Certify
> (http://www.synplicity.com/products/certify/index.html), BYO
> (http://www.byo-solutions.com/index.htm) and Auspy (http://www.auspy.com/),
>
> Hans
> www.ht-lab.com
>
>
> > regards
> > subin
> >
Article: 114069Yes, there was. I'll forward it to you in a private email. - Peter Dave wrote: > On Wed, 03 Jan 2007 16:17:27 -0800, Peter Ryser wrote: > > >>In the attachment find a small program that works with Linux 2.4 and >>read/writes the SPI EEPROM on the Xilinx ML300 board. > > > Was there really an attachment to this? If so, my newsreader must be > doing funny things. > > > ~Dave~Article: 114070
Hi all, I am new to Synopsys DC. And I have a basic problem. When I find timing violation in DC report, what shall I do first? 1. Shall I change the script of DC? To let the tools do something like retiming? 2. Shall I change the RTL code? To pipeline the comb logic manually? 3. Other choice, please recommend. What circumstance to do "1" or "2" or "1 and 2 at the same time"? Best regards, ShenliArticle: 114071
I wrote:
> None of the .xbd files supplied with EDK 8.2 show bidir GPIOs, so I
> dug around in the .mpd file to figure out how to do it. I tried adding
> this to the .xbd:
>
> BEGIN IO_INTERFACE
> ATTRIBUTE IOTYPE = XIL_GPIO_V1
> ATTRIBUTE_INSTANCE = Exp_Conn_A2
^
That underscore between ATTRIBUTE and INSTANCE was the first problem.
I haven't got bidir I/O pins working yet, but I'm getting closer. :-)
Article: 114072PeteS wrote: > colin wrote: > > Hi all > > > > I'm having trouble finding pcb layout recomendations on the altera and > > xilinx web sites for lead free bga's. I'm wanting to use an altera F256 > > package and I can find all I need for the leaded version but nothing > > for the rohs packages. Does anyone know where I should be looking or > > what changes to the leaded footprints I should make? > > > > all the best in 07 > > > > Colin > > I'm facing that issue right now for a FT256 package, and I'll do what > I've done with all the other RoHS BGA parts I've had done leadfree (and > that's quite a few) - use non-SMD pads with the recommended sizes from > the leaded versions. > > If my manufacturer thinks it needs to be tweaked - after all, they do a > *lot* of BGAs - they'll let me know. > > So far I haven't had any problems provided I use a gold finish; of > course, I haven't had sufficient time to get decent long term > reliability data. > > Cheers > > PeteS Thanks Pete, I will do the same. ColinArticle: 114073
I use MPMC2 memory controller with my peripheral connected to NPI port (DMA write capable). When I enable caches the PPC does not read the addr 0x00000000 properly, but when caching is disabled it works OK. I am not clearing the caches before using it. I have two Avnet Virtex-4 Mini Modules with ES FPGAs. Is it possible to put a memory address at the end (or the beginnig) of cached area; e.g. caching first 128MB and DDR memory start at 0x07800000? Can this work? Why is there no specs for bits 1-8 of CCR0? What do the bit 1 and 3 do? Cheers, Guru Erik Widding wrote: > cpmetz@googlemail.com wrote: > > currently I think they should have left the caches out. > > This would have been a really bad idea. Everything would go so slowly, > and the caches take up a tiny amount of area compared to an equivalent > number of blockrams. > > > In my design > > (something with MPMC, some local-link-DMA's and Gig-Ethernet), > > everytime I activate the instruction caches I get Program-Exceptions > > (jump to offset 0x700 in the vector table), sporadic resets and so on. > > I suspect that in my case the I-side plb (also taken from the > > mpmc-example) is too aggresive for the cache. Or whatever. Tried > > everything mentioned in the erratas... Sometimes it gets better, > > sometimes not... Played around with priorities in the MPMC... > but > If you disable the caches you will also change how the processor > interacts with the PLB bus. With caches disabled there will be no > bursting on the bus. With caches enabled some (or in some modes all) > transactions will result in bursting an entire cacheline. > > I would suspect the problem has much more to do with the memory > controller - possibly it won't do a burst read correctly in all > circumstances (i.e. design flaw). The timings may not be set > correctly. The next possibility is a power distribution or signal > integrity problem. With the cache enabled you will be operating the > dram in a burst mode which will both increase noise and power draw. > Maybe there isn't enough margin in the design. > > If you want to test the memory controller, disable the Icache, enable > the Dcache in an appropriate mode, and write a memory test that is > guaranteed to force burst reads at addresses that will result in > continually reloading the same cacheline with different data. You will > have to look at the data sheet for the processor to determine the > cacheline to physical address mapping. > > What you pick for the data will allow you to determine where/what the > problem is. You should be able to pick patterns that will allow you to > determine if the memory controller won't burst on the PLB side, or the > external port, and whether the timings are marginal or not. These > problems aren't fun to track down. > > Before getting too carried away I would suggest that you look at the > setup of the clock tree and phases of the clocks/data. If the > controller works reliably in single transfers, but not bursts, it could > be an insufficient hold time, as the bus will capacitively hold the > data if it is not being overwritten. Looking at the address/data > patterns that make the memory tests fail can give good insight. > > I can second the voice of Peter Ryser from Xilinx, the caches do work > in V4, even with ES silicon. > > > Regards, > Erik. > > --- > Erik Widding > President > Birger Engineering, Inc. > > (mail) 100 Boylston St #1070; Boston, MA 02116 > (voice) 617.695.9233 > (fax) 617.695.9234 > (web) http://www.birger.comArticle: 114074
Hi,
i will just describe what i do:
First, try to understand the violation:
is this a real one?
if not, add either a false path or a multicycle path or redefine
the timing definition in order to remove this false violation
if yes, change the RTL
regards.
Davy a écrit :
> Hi all,
>
> I am new to Synopsys DC. And I have a basic problem. When I find timing
> violation in DC report, what shall I do first?
>
> 1. Shall I change the script of DC? To let the tools do something like
> retiming?
> 2. Shall I change the RTL code? To pipeline the comb logic manually?
> 3. Other choice, please recommend.
>
> What circumstance to do "1" or "2" or "1 and 2 at the same time"?
>
> Best regards,
> Shenli
>
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