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Well, we seem to have the same problem. I did some cache-tests as proposed, and everything works fine in my design; at least when no DMA-transfers of the LocalLink-Interface are issued. So I apologize for the PPC-bashing, it was a sign of my frustration :-) Anyone had issues with the MPMC2 under heavy load from different ports? Cheers, Christian. Guru schrieb: > I use MPMC2 memory controller with my peripheral connected to NPI port > (DMA write capable). When I enable caches the PPC does not read the > addr 0x00000000 properly, but when caching is disabled it works OK. I > am not clearing the caches before using it. > I have two Avnet Virtex-4 Mini Modules with ES FPGAs. > > Is it possible to put a memory address at the end (or the beginnig) of > cached area; e.g. caching first 128MB and DDR memory start at > 0x07800000? Can this work? > > Why is there no specs for bits 1-8 of CCR0? What do the bit 1 and 3 do? > > Cheers, > > Guru > > > Erik Widding wrote: > > cpmetz@googlemail.com wrote: > > > currently I think they should have left the caches out. > > > > This would have been a really bad idea. Everything would go so slowly, > > and the caches take up a tiny amount of area compared to an equivalent > > number of blockrams. > > > > > In my design > > > (something with MPMC, some local-link-DMA's and Gig-Ethernet), > > > everytime I activate the instruction caches I get Program-Exceptions > > > (jump to offset 0x700 in the vector table), sporadic resets and so on. > > > I suspect that in my case the I-side plb (also taken from the > > > mpmc-example) is too aggresive for the cache. Or whatever. Tried > > > everything mentioned in the erratas... Sometimes it gets better, > > > sometimes not... Played around with priorities in the MPMC... > > but > > If you disable the caches you will also change how the processor > > interacts with the PLB bus. With caches disabled there will be no > > bursting on the bus. With caches enabled some (or in some modes all) > > transactions will result in bursting an entire cacheline. > > > > I would suspect the problem has much more to do with the memory > > controller - possibly it won't do a burst read correctly in all > > circumstances (i.e. design flaw). The timings may not be set > > correctly. The next possibility is a power distribution or signal > > integrity problem. With the cache enabled you will be operating the > > dram in a burst mode which will both increase noise and power draw. > > Maybe there isn't enough margin in the design. > > > > If you want to test the memory controller, disable the Icache, enable > > the Dcache in an appropriate mode, and write a memory test that is > > guaranteed to force burst reads at addresses that will result in > > continually reloading the same cacheline with different data. You will > > have to look at the data sheet for the processor to determine the > > cacheline to physical address mapping. > > > > What you pick for the data will allow you to determine where/what the > > problem is. You should be able to pick patterns that will allow you to > > determine if the memory controller won't burst on the PLB side, or the > > external port, and whether the timings are marginal or not. These > > problems aren't fun to track down. > > > > Before getting too carried away I would suggest that you look at the > > setup of the clock tree and phases of the clocks/data. If the > > controller works reliably in single transfers, but not bursts, it could > > be an insufficient hold time, as the bus will capacitively hold the > > data if it is not being overwritten. Looking at the address/data > > patterns that make the memory tests fail can give good insight. > > > > I can second the voice of Peter Ryser from Xilinx, the caches do work > > in V4, even with ES silicon. > > > > > > Regards, > > Erik. > > > > --- > > Erik Widding > > President > > Birger Engineering, Inc. > > > > (mail) 100 Boylston St #1070; Boston, MA 02116 > > (voice) 617.695.9233 > > (fax) 617.695.9234 > > (web) http://www.birger.comArticle: 114076
Davy wrote: > I am new to Synopsys DC. And I have a basic problem. When I find timing > violation in DC report, what shall I do first? > > 1. Shall I change the script of DC? To let the tools do something like > retiming? > 2. Shall I change the RTL code? To pipeline the comb logic manually? > 3. Other choice, please recommend. > > What circumstance to do "1" or "2" or "1 and 2 at the same time"? This all depends how big the violation is and how fast the technology is. If the violation is very small then just some playing with the scripts (overconstraining) can help. Some other options can also help, like retiming and more advanced optimizations in the more expensive DC editions. Of course small violations can be fixed at layout phase with careful manual placement etc. If the violations are quite big, then it's wise to change the rtl. That is usually the fastest and most reliable way to fix the problem. Usually the tricks in synthesis and layout are done in very late phases, when you don't want to touch the verified design. --KimArticle: 114077
Hi Jerome, Thanks a lot! Can you tell me what's false path and multicycle path mean? Best regards, Shenli Jerome wrote: > Hi, > > i will just describe what i do: > > First, try to understand the violation: > is this a real one? > if not, add either a false path or a multicycle path or redefine > the timing definition in order to remove this false violation > if yes, change the RTL > regards. > > > Davy a =E9crit : > > Hi all, > > > > I am new to Synopsys DC. And I have a basic problem. When I find timing > > violation in DC report, what shall I do first? > > > > 1. Shall I change the script of DC? To let the tools do something like > > retiming? > > 2. Shall I change the RTL code? To pipeline the comb logic manually? > > 3. Other choice, please recommend. > > > > What circumstance to do "1" or "2" or "1 and 2 at the same time"? > >=20 > > Best regards, > > Shenli > >Article: 114078
Hello!
Thanks for your help.
With the following code, with the 50MHz clock, I have only few bouncing
contacts.
So Xilinx switches are good !
Of course, bouncing contacts disappear if I reduce the clock frequency.
However something must be wrong with my previous code and bouncing
contacts do not explain everything ...
Any code improvement is welcomed !
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:24:58 01/03/07
-- Design Name:
-- Module Name: test - Behavioral
-- Project Name:
-- Target Device:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity test is
port (
inc: in std_logic;
dec: in std_logic;
reset: in std_logic;
clock: in std_logic;
led_value: out std_logic_vector(7 downto 0)
);
end test;
architecture Behavioral of test is
begin
process (clock)
variable counter_value: std_logic_vector(7 downto 0);
variable flag_inc: std_logic;
variable flag_dec: std_logic;
begin
if (reset='1') then
counter_value := "00000000";
flag_inc := '0';
flag_dec := '0';
elsif (clock'event and clock='1') then
if (inc='1') then
if (flag_inc = '0') then
counter_value := counter_value + 1;
flag_inc := '1';
end if;
else
flag_inc := '0';
end if;
if (dec='1') then
if (flag_dec = '0') then
counter_value := counter_value - 1;
flag_dec := '1';
end if;
else
flag_dec := '0';
end if;
end if;
led_value <= counter_value;
end process;
end Behavioral;
Olivier Scalbert wrote:
> Hello,
>
> I start playing with a Spartan 3 demo board.
> I want to program a 8 bits counter with one button that increments the
> counter, one button that decrements the counter and one reset button
> that erases the counter. Output of the counter is connected to the 8 leds.
>
> ...
Article: 1140791mm pitch small number BGA could be hand soldered with a good hot air tool (some about $150-$300) if you have enough available parts "to make your hand" first. You also need proffesional solder paste which is quite expensive (some Kester is $47 a few ml). greetings, Vasile smount wrote: > Does anyone know what is needed to work with surface mount > ic's, what sort of starting price tag are we talking about? > (Assuming I have ready made boards, i.e. only the soldering > phase is required)Article: 114080
FPGA in BGA running at hight frequency is quite a challange to route (I'm talking about more than 484 balls package). The first important step is to assure a correct grid and route thickness. The second one is to place manually via on pad according to the required padstack. And the third is to choose right the power supply filtering capacitors and/or high capacitance supply laminate core (as ZBC1000 or ZBC2000) and all the routes impedances. I suggest you a deeply visit on the following site: http://www.pcblibraries.com/resources/GEN-docs.asp and of course browsing the email topics on the forum. greetings, Vasile Ray wrote: > Hi everyone: > I am new to FPGA and looking for a possible topic on FPGA routing > algrithm. I read some classic articals in this field and find that when > people are talking about routing algrithms (i.e. pathfinder) they > generally ignore the architecture of switch box, while it is said that > the topology of swich box may have an impact on the routability on the > router. Thus, I am wondering how the router determine the path inside > the switch box? And I am thinking is it possible to add the routing > cost on the switch box to the cost function to the pathfinder algrithm? > > I am totally new to the FPGA and its routing. I hope the above > question may not be so naive. And I am still not sure which topic in > this area is worthy to do. I appreciate if anyone give me some advice. > > Thanks and happy new year. > > Ruiz > TAMUArticle: 114081
OK, this is about routing outside the FPGA, sorry. vasile wrote: > FPGA in BGA running at hight frequency is quite a challange to route > (I'm talking about more than 484 balls package). The first important > step is to assure a correct grid and route thickness. > The second one is to place manually via on pad according to the > required padstack. > And the third is to choose right the power supply filtering capacitors > and/or high capacitance supply laminate core (as ZBC1000 or ZBC2000) > and all the routes impedances. > I suggest you a deeply visit on the following site: > http://www.pcblibraries.com/resources/GEN-docs.asp > and of course browsing the email topics on the forum. > > greetings, > Vasile > > > Ray wrote: > > Hi everyone: > > I am new to FPGA and looking for a possible topic on FPGA routing > > algrithm. I read some classic articals in this field and find that when > > people are talking about routing algrithms (i.e. pathfinder) they > > generally ignore the architecture of switch box, while it is said that > > the topology of swich box may have an impact on the routability on the > > router. Thus, I am wondering how the router determine the path inside > > the switch box? And I am thinking is it possible to add the routing > > cost on the switch box to the cost function to the pathfinder algrithm? > > > > I am totally new to the FPGA and its routing. I hope the above > > question may not be so naive. And I am still not sure which topic in > > this area is worthy to do. I appreciate if anyone give me some advice. > > > > Thanks and happy new year. > > > > Ruiz > > TAMUArticle: 114082
"Brian Davis" <brimdavis@aol.com> wrote in message news:1167885240.697044.105030@v33g2000cwv.googlegroups.com... > Symon wrote: >> >> But I can't find any of these:- >> http://images.google.com/images?hl=en&q=toast+rack >> which greatly enhance the toast experience! >> > Many thanks for that wonderful link, which has led me to the ultimate > British Toasting Experience, a Wallace and Gromit Toast Rack: > http://www.aardmarket.com/wg/productdetail.php?number=A6490 > > Sadly, they have chosen not to bundle a free Toast-O-Matic > jelly applicator with each purchase. > Good link Brian, I wonder if our Plasticine heroes could help popularise the toast rack in America? However, one question. Do you mean 'jam applicator'? Jelly's something you put in trifle and will definitely soggy the toast. Here's a link with a picture of Jelly in it's pre-packed state. http://news.bbc.co.uk/1/hi/world/europe/6035821.stm Perhaps we should stick with marmalade, I think it's the same in both lands! Syms. p.s. On the first day of a new job having just moved to the US I asked the guy in the cube next to me if I could borrow a rubber. Apparently I wanted an eraser. p.p.s. Bob, I found this http://en.wikipedia.org/wiki/Post_Toasties . The article is on Wikipedia, so it must be true. It even mentions 'angry clergyman', lending that needed air of authenticity.Article: 114083
"vasile" <piclist9@gmail.com> wrote in message news:1167911474.881022.304720@51g2000cwl.googlegroups.com... > I suggest you a deeply visit on the following site: > http://www.pcblibraries.com/resources/GEN-docs.asp > and of course browsing the email topics on the forum. > Hi Vasile, Good link! As you say, I think the OP meant something else, but thanks for this! I'll add it to the RoHS BGA thread. Cheers, Syms.Article: 114084
This link might be useful! "vasile" <piclist9@gmail.com> wrote in message news:1167911474.881022.304720@51g2000cwl.googlegroups.com... > I suggest you a deeply visit on the following site: > http://www.pcblibraries.com/resources/GEN-docs.asp > and of course browsing the email topics on the forum. > Hi Vasile, Good link! As you say, I think the OP meant something else, but thanks for this! I'll add it to the RoHS BGA thread. Cheers, Syms.Article: 114085
On Thu, 4 Jan 2007 12:06:55 -0000, "Symon" <symon_brewer@hotmail.com> wrote: >However, one question. Do you mean 'jam applicator'? Jelly's something you >put in trifle Only in England. Scots speak of "jelly pieces" (=jam butties to you). BTW: trifle with jelly/Jell-O is an abomination acceptable only at young children's birthday parties, but that's another discussion altogether... I'm still in detox after my cousin made grandmother's trifle recipe at Christmas. Too sloppy and tiramisu-like for my taste, but pretty good anyway. I usually find myself agreeing pretty strongly with Symon about electronics, but it seems we part company about gastronomy :-) Toast-racks are better described as "toast coolers". The ONLY way to eat toast is very soon after it emerges from the grill, which is why breakfast-time toast in English hotels is always such a disappointment. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 114086
Symon wrote: > > However, one question. Do you mean 'jam applicator'? Jelly's something > you put in trifle and will definitely soggy the toast. > I should know better than to trifle with toast. I did in fact consider 'marmalade applicator', but thought that 'jelly' would provide us with more breakfast language fodder. > >Good link Brian, I wonder if our Plasticine heroes could help >popularise the toast rack in America? > I suspect one impediment to the widespread adoption of British Toaster Technology in the American kitchen is that the heated toast racks require a high-amperage DC supply having positive ground. BrianArticle: 114087
Bob Perlman wrote: > On Tue, 2 Jan 2007 10:14:21 -0000, "Symon" <symon_brewer@hotmail.com> > wrote: > > >p.s. On the subject of US vs. UK toasting techniques, IMO the problem in the > >US is not the toaster machines, it's the post-toasting technology. The toast > >just gets piled up on a plate. The US seems to be a veritable toast rack > >desert, so the toast always ends up soggy. I guess that's why it's IHOP and > >not IHOT! :-) > Bob Perlman said: We are an odd country: as you've suggested, we have very poor post-toasting technology, but we do have a cereal called Post Toasties. No one can explain this. And we drive on parkways and park on driveways. And we "pre-drill" and "pre-heat". ;) -Dave PollumArticle: 114088
On Thu, 04 Jan 2007 12:32:31 +0100, Olivier Scalbert
<olivier.scalbert@algosyn.com> wrote:
>Hello!
>Thanks for your help.
>
>With the following code, with the 50MHz clock, I have only few bouncing
>contacts.
>So Xilinx switches are good !
>
>Of course, bouncing contacts disappear if I reduce the clock frequency.
>
>However something must be wrong with my previous code and bouncing
>contacts do not explain everything ...
John_H gave you the strongest hint: In current digital technologies,
and particularly in FPGAs, it is a VERY bad idea to try to describe
asynchronous state machines. Essentially you had something like
this...
process(button)
begin
if button = '1' then
if button_seen = '0' then
button_seen <= '1';
count <= count + 1;
end if;
else --- button = '0'
button_seen <= '0';
end if;
end process;
Logically this is fine, but think what it is asking the
hardware to do... On the transition of button from
0 to 1 you need to set the "button_seen" flag and,
AT THE SAME INSTANT, increment the counter.
That requires all 8 bits (or however many) of the
counter to take up their new values simultaneously,
WITHIN the rather narrow time window between
button going true and button_seen following it.
Getting this to work right is exceptionally tricky,
since all the various pieces may take up their
new values at different speeds - so some may
reliably get their new values, some may fail to
get them, and others may do it unreliably.
The solution is to use *synchronous design*,
exactly as you have done in your recent
clocked example, which follows the standard
synthesisable process template. Why, you may
well ask, is that different from what you did before?
Because the synthesis tool understands that it
implies flip-flops, and flip-flops have been very
carefully designed by your device vendor to ensure
that they reliably take up their new values on
each new clock cycle. To make this work you need
two things from your device vendor:
(1) reliable flip-flops as I've just described;
(2) a very cleverly designed clock distribution
network, so that all your flip-flops see the clock
at effectively the same instant - to find out more
about this, check out "hold time" in any good
digital design text book.
Not surprisingly, the FPGA vendors provide
exactly this for you. So your new design
works, and you now have only the switch
bounce issues to worry about.
Switches typically bounce for between 0.1ms
and 5ms, depending on how they're made.
At 50MHz that means you need quite a long
time delay to remove the bounce. Here's
a little piece of code that will do the trick:
entity debounce is
generic (delay_count: natural := 10000);
port (
clock, reset: in std_logic;
switch: in std_logic;
debounced: out std_logic
);
end;
architecture A of debounce is
begin
process(clock, reset)
variable count: natural range 0 to delay_count;
variable new_switch, old_switch: std_logic;
begin
if reset = '1' then
count := delay_count;
old_switch := '0';
new_switch := '0';
elsif rising_edge(clock) then
if old_switch = new_switch then ---- switch stable, count down
if count=0 then --- timeout has expired, update output
debounced <= old_switch;
else --- still counting
count := count - 1;
end if;
else ---- switch has changed, start timing again
count := delay_count;
end if;
old_switch := new_switch;
new_switch := switch;
end if;
end process;
end;
Note that the ONLY thing I do with the original switch input
is to copy it into the "new_switch" flip-flop, thereby avoiding
input hazards (another good search term to study!). Really
paranoid engineers might consider adding a metastability-
hardening flip-flop too, but I reckon that's too much for
a manual switch input.
The reset isn't really essential in hardware because the
design will always sort itself out within a reasonable
time, but it makes life much easier for simulation.
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Article: 114089On 4 Jan 2007 05:09:24 -0800, "Dave Pollum" <vze24h5m@verizon.net> wrote: >And we drive on parkways and park on driveways. And you normally drive your cars on the pavement, which in Britain would be a good way to demolish a few pedestrians! -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 114090
"nana" <nmichou@utk.edu> ??????:1167855860.324557.23270@k21g2000cwa.googlegroups.com... >I am using xilinx xup virtex2 pro Dev system board, and I am trying to > communicate 2 boards together, using chipscope, in the pro analyzer > window when I apply settings and arm the trigger I notice that the > waveform window is waiting for upload and it stays that way, what does > that mean and how to take care of this problem. > > Thank you > nana > No trigger clock, or the trigger conditions are not satisfied. Sun Lei.Article: 114091
hey, i have this piece of code where i want to use the multiply/add functionality of the DSP48 slice of a V4, i want to infer it instead of instantiate (to be portable but also to try it out) and i have found following example code: signal a_reg : std_logic_vector((a_width - 1) downto 0); signal b_reg : std_logic_vector((b_width - 1) downto 0); signal c_align : std_logic_vector((c_width - 1) downto 0); signal c_reg : std_logic_vector((c_width - 1) downto 0); signal m_reg : std_logic_vector((a_width + b_width - 1) downto 0); multadd_proc : process(clk) begin if (clk'event and clk = '1') then if (reset = '1') then a_reg <= (others => '0'); b_reg <= (others => '0'); c_align <= (others => '0'); c_reg <= (others => '0'); m_reg <= (others => '0'); p_out <= (others => '0'); elsif (ce = '1') then a_reg <= a; b_reg <= b; c_align <= c; c_reg <= c_align; m_reg <= a_reg * b_reg; p_out <= m_reg + c_reg; end if; end if; end process; and indeed it infers the DSP48 n a multiply/add functionality ... now i need it for one application in such a way that it has 2 constants of 18bits (the previous code also works with this 18bit setup): multadd_proc : process(clk) begin if (clk'event and clk = '1') then if (reset = '1') then a_int <= (others => '0'); b_int <= (others => '0'); c_int <= (others => '0'); c_int_d <= (others => '0'); m_reg <= (others => '0'); p_out <= (others => '0'); else a_int <= a; b_int <= "000000000001010101"; c_int <= "101000000000000000"; c_int_d <= c_int; m_reg <= a_int * b_int; p_out <= m_reg + c_int_d; end if; end if; end process; but in this code is does not find the right DSP48 functionality and uses a 18x18 multiplier and LUT/FF adder ... even when using the use_48 constraint on the p_out signal and when using the use_dsp48 on the component it generates 3 DSP48 slices instead of just 1 (or 2 if it does not see the the fact that they can be placed in one). What i'm i doing wrong, am i missing something? Thanks for the feedback and help, kind regards, Tim VerstraeteArticle: 114092
On 4 Jan 2007 06:13:00 -0800, "Tim Verstraete" <tim.verstraete@barco.com> wrote: >i have this piece of code where i want to use the multiply/add >functionality of the DSP48 slice of a V4, i want to infer it instead of >instantiate (to be portable but also to try it out) and i have found >following example code: > [snip much code] >but in this code is does not find the right DSP48 functionality and >uses a 18x18 multiplier and LUT/FF adder ... even when using the use_48 >constraint on the p_out signal and when using the use_dsp48 on the >component it generates 3 DSP48 slices instead of just 1 (or 2 if it >does not see the the fact that they can be placed in one). What i'm i >doing wrong, am i missing something? I'm not 100% sure, but I suspect it's because you are using std_logic_unsigned and consequently implying 18x18 UNSIGNED multipliers, whereas the DSP48 blocks have 18x18 SIGNED multipliers. The easy way to check this theory is to tweak the design so that all the inputs are 17 bits instead of 18 bits wide. If, as I suspect, this then gives you just the one DSP48, then I'm right and either you need to make everything signed or you need to reconsider how to do the DSP. Apologies if this is a wild goose chase. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 114093
indeed, that is also what i thought and when i use it on the template: LIBRARY ieee; USE ieee.std_logic_1164.ALL; use ieee.std_logic_arith.all; use ieee.std_logic_signed.all; entity multadd is generic ( a_width : integer :=18; b_width : integer :=18; c_width : integer :=35 ); port ( ce : in std_logic; reset : in std_logic; clk : in std_logic; a : in std_logic_vector((a_width - 1) downto 0); b : in std_logic_vector((b_width - 1) downto 0); c : in std_logic_vector((c_width - 1) downto 0); p_out : out std_logic_vector((c_width - 1) downto 0) ); end multadd; architecture rtl of multadd is signal a_reg : std_logic_vector((a_width - 1) downto 0); signal b_reg : std_logic_vector((b_width - 1) downto 0); signal c_align : std_logic_vector((c_width - 1) downto 0); signal c_reg : std_logic_vector((c_width - 1) downto 0); signal m_reg : std_logic_vector((a_width + b_width - 1) downto 0); begin multadd_proc : process(clk) begin if (clk'event and clk = '1') then if (reset = '1') then a_reg <= (others => '0'); b_reg <= (others => '0'); c_align <= (others => '0'); c_reg <= (others => '0'); m_reg <= (others => '0'); p_out <= (others => '0'); elsif (ce = '1') then a_reg <= a; b_reg <= b; c_align <= c; c_reg <= c_align; m_reg <= a_reg * b_reg; p_out <= m_reg + c_reg; end if; end if; end process; end rtl; i use the 18x18bit and i get only one 1 DSP48 slice in the report: Number of Slices: 20 out of 24576 0% Number of Slice Flip Flops: 35 out of 49152 0% Number of IOs: 109 Number of bonded IOBs: 109 out of 640 17% Number of GCLKs: 1 out of 32 3% Number of DSP48s: 1 out of 512 0% but when i use the same widths on my code i get 3 or 1+adder in luts? but you are right in when i change the width of the vectors to 17bit it works just like it should and uses only 1 DSP48 slice. thanks for replying, kind regards, Tim Jonathan Bromley schreef: > On 4 Jan 2007 06:13:00 -0800, "Tim Verstraete" > <tim.verstraete@barco.com> wrote: > > > >i have this piece of code where i want to use the multiply/add > >functionality of the DSP48 slice of a V4, i want to infer it instead of > >instantiate (to be portable but also to try it out) and i have found > >following example code: > > > [snip much code] > > >but in this code is does not find the right DSP48 functionality and > >uses a 18x18 multiplier and LUT/FF adder ... even when using the use_48 > >constraint on the p_out signal and when using the use_dsp48 on the > >component it generates 3 DSP48 slices instead of just 1 (or 2 if it > >does not see the the fact that they can be placed in one). What i'm i > >doing wrong, am i missing something? > > I'm not 100% sure, but I suspect it's because you are using > std_logic_unsigned and consequently implying 18x18 > UNSIGNED multipliers, whereas the DSP48 blocks have > 18x18 SIGNED multipliers. > > The easy way to check this theory is to tweak the design so > that all the inputs are 17 bits instead of 18 bits wide. If, > as I suspect, this then gives you just the one DSP48, then > I'm right and either you need to make everything signed > or you need to reconsider how to do the DSP. > > Apologies if this is a wild goose chase. > -- > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > jonathan.bromley@MYCOMPANY.com > http://www.MYCOMPANY.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated.Article: 114094
ok, your right, now i know why it works on this code and not mine, in the template i used the following libraries: LIBRARY ieee; USE ieee.std_logic_1164.ALL; use ieee.std_logic_arith.all; use ieee.std_logic_signed.all; and in mine i used library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; and yes it has to do with the unsigned/signed library ... thanks for pointing that out and making me look again at that part of the code ... kind regards, Tim Tim Verstraete schreef: > indeed, that is also what i thought and when i use it on the template: > > LIBRARY ieee; > USE ieee.std_logic_1164.ALL; > use ieee.std_logic_arith.all; > use ieee.std_logic_signed.all; > > entity multadd is > generic ( > a_width : integer :=18; > b_width : integer :=18; > c_width : integer :=35 > ); > port ( > ce : in std_logic; > reset : in std_logic; > clk : in std_logic; > a : in std_logic_vector((a_width - 1) downto 0); > b : in std_logic_vector((b_width - 1) downto 0); > c : in std_logic_vector((c_width - 1) downto 0); > p_out : out std_logic_vector((c_width - 1) downto 0) > ); > end multadd; > > architecture rtl of multadd is > > signal a_reg : std_logic_vector((a_width - 1) downto 0); > signal b_reg : std_logic_vector((b_width - 1) downto 0); > signal c_align : std_logic_vector((c_width - 1) downto 0); > signal c_reg : std_logic_vector((c_width - 1) downto 0); > signal m_reg : std_logic_vector((a_width + b_width - 1) downto 0); > > begin > > multadd_proc : process(clk) > begin > if (clk'event and clk = '1') then > if (reset = '1') then > a_reg <= (others => '0'); > b_reg <= (others => '0'); > c_align <= (others => '0'); > c_reg <= (others => '0'); > m_reg <= (others => '0'); > p_out <= (others => '0'); > elsif (ce = '1') then > a_reg <= a; > b_reg <= b; > c_align <= c; > c_reg <= c_align; > m_reg <= a_reg * b_reg; > p_out <= m_reg + c_reg; > end if; > end if; > end process; > > end rtl; > > i use the 18x18bit and i get only one 1 DSP48 slice in the report: > > Number of Slices: 20 out of 24576 0% > Number of Slice Flip Flops: 35 out of 49152 0% > Number of IOs: 109 > Number of bonded IOBs: 109 out of 640 17% > Number of GCLKs: 1 out of 32 3% > Number of DSP48s: 1 out of 512 0% > > but when i use the same widths on my code i get 3 or 1+adder in luts? > but you are right in when i change the width of the vectors to 17bit it > works just like it should and uses only 1 DSP48 slice. > > thanks for replying, > > kind regards, > > Tim > > Jonathan Bromley schreef: > > > On 4 Jan 2007 06:13:00 -0800, "Tim Verstraete" > > <tim.verstraete@barco.com> wrote: > > > > > > >i have this piece of code where i want to use the multiply/add > > >functionality of the DSP48 slice of a V4, i want to infer it instead of > > >instantiate (to be portable but also to try it out) and i have found > > >following example code: > > > > > [snip much code] > > > > >but in this code is does not find the right DSP48 functionality and > > >uses a 18x18 multiplier and LUT/FF adder ... even when using the use_48 > > >constraint on the p_out signal and when using the use_dsp48 on the > > >component it generates 3 DSP48 slices instead of just 1 (or 2 if it > > >does not see the the fact that they can be placed in one). What i'm i > > >doing wrong, am i missing something? > > > > I'm not 100% sure, but I suspect it's because you are using > > std_logic_unsigned and consequently implying 18x18 > > UNSIGNED multipliers, whereas the DSP48 blocks have > > 18x18 SIGNED multipliers. > > > > The easy way to check this theory is to tweak the design so > > that all the inputs are 17 bits instead of 18 bits wide. If, > > as I suspect, this then gives you just the one DSP48, then > > I'm right and either you need to make everything signed > > or you need to reconsider how to do the DSP. > > > > Apologies if this is a wild goose chase. > > -- > > Jonathan Bromley, Consultant > > > > DOULOS - Developing Design Know-how > > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > > jonathan.bromley@MYCOMPANY.com > > http://www.MYCOMPANY.com > > > > The contents of this message may contain personal views which > > are not the views of Doulos Ltd., unless specifically stated.Article: 114095
jjlindula@hotmail.com wrote: > Hello, I have a question about using the SerialLite MegaCore Function > to create a high-speed data link between two or more Stratix FPGA's. I > want to know, do I simply tie the two FPGA's TX/RX pins together, or > are there any devices that are required to link the two FPGA's > together? I've been looking over the SerialLite II MegaCore Function > User Guide on page 3-17 they have a Figure that has two FPGA's > connected together and I was thinking, is it that simple, just tie the > TX & RX lines together? > > thanks, > joe Hello again, I wanted to post the answer from Altera: Customer need not any other active device between two FPGA during we realize SerialLite II. The max distance is depended on FPGA transceiver performance and application entironment. On four layer FR-4 PCB backplane, we can guarantee 40-inch and two connector. If adopt SMA connector and cable, the distance will become much longer. Thanks, OwenArticle: 114096
On 4 Jan 2007 07:14:21 -0800, "Tim Verstraete" <tim.verstraete@barco.com> wrote: [Also posted to comp.lang.vhdl] >ok, your right, now i know why it works on this code and not mine, in >the template i used the following libraries: > >LIBRARY ieee; >USE ieee.std_logic_1164.ALL; >use ieee.std_logic_arith.all; >use ieee.std_logic_signed.all; > >and in mine i used > >library IEEE; >use IEEE.STD_LOGIC_1164.ALL; >use IEEE.STD_LOGIC_ARITH.ALL; >use IEEE.STD_LOGIC_UNSIGNED.ALL; And that is PRECISELY why I keep banging on about why STD_LOGIC_(UN)SIGNED is such a very, very bad thing. If you had used only STD_LOGIC_ARITH or (better) NUMERIC_STD, then you would have been forced into declaring the objects as SIGNED or UNSIGNED, and you would know what you were doing. Having an arbitrary numeric representation imposed on std_logic_vector by a use clause is IMO certifiably insane. Thanks for providing more ammunition for my rant :-) -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 114097
"Jonathan Bromley" <jonathan.bromley@MYCOMPANY.com> wrote in message
news:3pspp2ll9o3ugnjb9glib8phm1aggforbr@4ax.com...
> On Thu, 4 Jan 2007 12:06:55 -0000, "Symon"
> <symon_brewer@hotmail.com> wrote:
>
>>However, one question. Do you mean 'jam applicator'? Jelly's something you
>>put in trifle
> Only in England. Scots speak of "jelly pieces" (=jam butties to you).
Weird, I've been here a few years now and not heard that one. I think "jam
sarnie" is the local vernacular I'm used to. I believe all this terminology
is compliant with the EEC standard for Jams, Jellies and Marmalades (and
sweetened chestnut purée):
http://eur-lex.europa.eu/LexUriServ/site/en/oj/2002/l_010/l_01020020112en00670072.pdf
Jam is like Jelly but created by a team of engineers: You can have it
yesterday, tomorrow, but not today :-)
-Ben-
Article: 114098Tom J wrote: > Up to now, I've only been modifying the compiler produced MPD files. I > assume from your post that I should be generating files of my own as > well/instead. Is there a reference for these files? When to use them, > what goes in them, their format, etc.? Pardon me for replying to my own post, but as FYI for everyone I've found the following Xilinx reference manual that details the usage and format of the MHS, MPD, PAO, BBD, MSS, MDD, MLD and XBD files: Platform Specification Format Reference Manual http://www.xilinx.com/ise/embedded/edk7_1docs/psf_rm.pdfArticle: 114099
Frustration is what you get when you use PPC. If you want to have little more performance than MB then this route is inevitable. I also have problems with delays in my NPI DMA engine. For some reason short transactions are delayed. I am using 64 word transactions from asyncronous source. I fill all the 64 words in the NPI FIFO then I fire addr request (which initiates xfer). For shorter transactions I put BE to 0x0 for the doublewords that should not be written. Maybe this BE is the reason for delays. PS: If anyone wants a partially working GSRD2 design for Virtex-4 Mini Module I can send it. Cheers, Guru cpmetz@googlemail.com wrote: > Well, we seem to have the same problem. I did some cache-tests as > proposed, and everything works fine in my design; at least when no > DMA-transfers of the LocalLink-Interface are issued. So I apologize for > the PPC-bashing, it was a sign of my frustration :-) > > Anyone had issues with the MPMC2 under heavy load from different ports? > > Cheers, > Christian. > > Guru schrieb: > > > I use MPMC2 memory controller with my peripheral connected to NPI port > > (DMA write capable). When I enable caches the PPC does not read the > > addr 0x00000000 properly, but when caching is disabled it works OK. I > > am not clearing the caches before using it. > > I have two Avnet Virtex-4 Mini Modules with ES FPGAs. > > > > Is it possible to put a memory address at the end (or the beginnig) of > > cached area; e.g. caching first 128MB and DDR memory start at > > 0x07800000? Can this work? > > > > Why is there no specs for bits 1-8 of CCR0? What do the bit 1 and 3 do? > > > > Cheers, > > > > Guru > > > > > > Erik Widding wrote: > > > cpmetz@googlemail.com wrote: > > > > currently I think they should have left the caches out. > > > > > > This would have been a really bad idea. Everything would go so slowly, > > > and the caches take up a tiny amount of area compared to an equivalent > > > number of blockrams. > > > > > > > In my design > > > > (something with MPMC, some local-link-DMA's and Gig-Ethernet), > > > > everytime I activate the instruction caches I get Program-Exceptions > > > > (jump to offset 0x700 in the vector table), sporadic resets and so on. > > > > I suspect that in my case the I-side plb (also taken from the > > > > mpmc-example) is too aggresive for the cache. Or whatever. Tried > > > > everything mentioned in the erratas... Sometimes it gets better, > > > > sometimes not... Played around with priorities in the MPMC... > > > but > > > If you disable the caches you will also change how the processor > > > interacts with the PLB bus. With caches disabled there will be no > > > bursting on the bus. With caches enabled some (or in some modes all) > > > transactions will result in bursting an entire cacheline. > > > > > > I would suspect the problem has much more to do with the memory > > > controller - possibly it won't do a burst read correctly in all > > > circumstances (i.e. design flaw). The timings may not be set > > > correctly. The next possibility is a power distribution or signal > > > integrity problem. With the cache enabled you will be operating the > > > dram in a burst mode which will both increase noise and power draw. > > > Maybe there isn't enough margin in the design. > > > > > > If you want to test the memory controller, disable the Icache, enable > > > the Dcache in an appropriate mode, and write a memory test that is > > > guaranteed to force burst reads at addresses that will result in > > > continually reloading the same cacheline with different data. You will > > > have to look at the data sheet for the processor to determine the > > > cacheline to physical address mapping. > > > > > > What you pick for the data will allow you to determine where/what the > > > problem is. You should be able to pick patterns that will allow you to > > > determine if the memory controller won't burst on the PLB side, or the > > > external port, and whether the timings are marginal or not. These > > > problems aren't fun to track down. > > > > > > Before getting too carried away I would suggest that you look at the > > > setup of the clock tree and phases of the clocks/data. If the > > > controller works reliably in single transfers, but not bursts, it could > > > be an insufficient hold time, as the bus will capacitively hold the > > > data if it is not being overwritten. Looking at the address/data > > > patterns that make the memory tests fail can give good insight. > > > > > > I can second the voice of Peter Ryser from Xilinx, the caches do work > > > in V4, even with ES silicon. > > > > > > > > > Regards, > > > Erik. > > > > > > --- > > > Erik Widding > > > President > > > Birger Engineering, Inc. > > > > > > (mail) 100 Boylston St #1070; Boston, MA 02116 > > > (voice) 617.695.9233 > > > (fax) 617.695.9234 > > > (web) http://www.birger.com
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