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Hello As I'd mentioned in one of my previous mails, I'm working on intrinsic evolution. I'd like to know if its possible to generate netlists in EDIF format from C itself for circuits, or will it be too complicated? Regards quadArticle: 114301
Hi chaps I'm fairly sure I can power down the IO buffers of a Coolrunner II with the internal logic powered, but I'm looking to see if anyone does this or has done it just for confirmation. >From the datasheet: -------------------------------------------------------- Mixed Voltage, Power Sequencing, and Hot Plugging As mentioned in I/O Banking, CoolRunner-II CPLD parts support mixed voltage I/O signals. It is important to assign signals to an I/O bank with the appropriate I/O voltage. Driving a high voltage into a low voltage bank can result in negative current flow through the power supply pins. The power applied to the VCCIO and VCC pins can occur in any order and the CoolRunner-II CPLD will not be damaged. ***For best results, we recommend that VCCINT be applied before VCCIO.*** This will ensure that the internal logic is correct before the I/Os are active. CoolRunner-II CPLDs can reside on boards where the board is inserted into a "live" connector (hot plugged) and the parts will be well-behaved as if powering up in a standard way. --------------------------------------------------------- Highlight mine. That implies I can power (should!) the internal logic before powering the IOs, but can I do that indefinitely? Any comments? Cheers PeteSArticle: 114302
On 10 Jan 2007 08:05:18 -0800, "fpgauser" <fpgaengineerfrankfurt@arcor.de> wrote: >Anybody allready designed a VHDL model of a stepper motor to simulate >in modelsim ? Do you really mean a model of a _stepper motor_? If so, you will need to decide how you map from the physical properties and operating conditions of the motor - shaft angle, externally applied torque etc - to VHDL data types. And you will need to decide how fast to sample and update your model in order to mimic its continuous-time behaviour in the discrete-time VHDL simulator. It's not even so simple to decide how to model the electrical inputs to such a motor. On the other hand, if you simply want to assume that the motor is very lightly loaded and is driven by on/off digital signals, you may be able to write a very crude discretized model that looks at the electrical input, decides what the settled shaft angle should be for that input, and causes the shaft angle to progress towards that position over time. I suspect, though, that you will still need to model the motor's speed in some way. For unusual applications like this, it's important to specify the level of modelling accuracy you require - it makes a huge difference to the difficulty of creating a model. Note that the mixed-signal simulator people solved these things a long time ago; if you have a complete mixed-signal simulator then you will probably get quite a few such models bundled with it. Finally, since you are working in ModelSim, it is left as a trivial exercise for the reader to write a little Tk graphical widget that will display the motor's position visually as the simulation proceeds :-) -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 114303
Hi all, I am new to CPU design and confused with two CPU term. That is interlock and stall. What's their difference? Does interlock and stall all do insert NOP and remove the data dependency? I have copied a sentence from a CPU document "The interlock is responsible for detecting read-after-write hazards and stalling the pipeline until the hazard has been resolved. This avoids the need to insert nop directives between dependent instructions, thus keeping code size to a minimum, as well as simplifying assembler-level programming." Best regards, DavyArticle: 114304
On Wed, 10 Jan 2007 18:41:44 -0700, Kevin Neilson <kevin_neilson@removethiscomcast.net> wrote: >Has anyone ever been able to get Modelsim to model transport delays in >Verilog? Verilog simulators, by default, use inertial delays, so if you >have an assignment such as this: > >assign #4 sig_out = sig_in; > >then any pulse on sig_in that is less than 4ns will get swallowed. >Modeling transport delays prevents this from happening. Modelsim claims >to model transport delays using the +transport_int_delay option for >vsim, but this just doesn't seems to work. I think you'll find that this option applies only to interconnect delays that have been backannotated from an SDF file. The Verilog language defines continuous driver delays and net delays to be inertial, and I was under the impression that simulators aren't supposed to disobey that. If you want transport delay in your own Verilog model, use intra-assignment nonblocking delays - try tnis... always @(sig_in) sig_out <= #4 sig_in; (Of course, sig_out needs to be a variable now, not a net.) -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 114305
PeteS wrote: <snip> > Highlight mine. That implies I can power (should!) the internal logic > before powering the IOs, but can I do that indefinitely? I'd say yes. but you may want to also check the IccINT, as I presume your motivation is to actually save power. With VccIO 'removed' you may need to ensure all pins are true CMOS levels ( within 500mV of GND ) . Check it by varying the IO float voltage,and measuring the IccINT -jgArticle: 114306
quad wrote: > Hello > As I'd mentioned in one of my previous mails, I'm working on intrinsic > evolution. I'd like to know if its possible to generate netlists in > EDIF format from C itself for circuits, or will it be too complicated? > Regards > quad Ohh.... I think it will be too complicated to generate EDIF netlist from C. We can look at the things this way.....Generating EDIF from C is like first generate VHDL/Verilog code from C and then generate EDIF from VHDL/Verilog RTL. Now generating EDIF from RTL itself is a big task as this is nothing but synthesis. Anyways, there's no word like 'Impossible' in some dictionaries. Regards,Article: 114307
Hi, > I am new to CPU design and confused with two CPU term. That is > interlock and stall. What's their difference? Does interlock and stall > all do insert NOP and remove the data dependency? > > I have copied a sentence from a CPU document "The interlock is > responsible for detecting read-after-write hazards and stalling the > pipeline until the hazard has been resolved. This avoids the need to > insert nop directives between dependent instructions, thus keeping code > size to a minimum, as well as simplifying assembler-level programming." In this use, interlock is refering the logic that tracks dependencies between instructions, and then stalls (pauses the pipeline from the decode stage backwards) when a dependency is detected that cannot be resolved by bypassing. There are other causes of stall that are not related to the interlock, such as stalls that occur on cache misses. Cheers, JonArticle: 114308
Not set in stone yet but one off prices are likely to be GBP=A325-30, US$ 40-50 on current exchange, for the base level versions with the XC3S100E. If it starts to ship in reasonable numbers it is likely we will drop that price back a bit. Certainly discounts will be there for orders of 10+ even at the initial production run rate. The 3 versions we have done are 32,36 and 40 pins. We will probably do a 28pin and maybe 48pins as well. Anything up to 42 pins is easy as we don't change the core design. We just hook up more signals to the bus switches than provide the 5V protection. Beyond that we add another bus switch but there is area available in the bigger pinouts. CFCARD merely there to show size for those wondering. We are aiming for these to be a stock item towards the end of Feb but that is subject to usual spanners in the works. John Adair Enterpoint Ltd. -jg wrote: > Dave Pollum wrote: > > Not from John,but -- http://www.enterpoint.co.uk/ > > John, have you set prices yet for the Craignell boards? > > -Dave Pollum > > Thanks, but on the home page Craignell Modules does not appear, > and google for Craignell Modules finds nothing, also news has only > quite old infos, and not until I take a guess, and dig into > BoardProducts > do I see Craignell mentioned, and finally here find a link > > http://www.enterpoint.co.uk/component_replacements/craignell.html > > Tip for John: > Post photos in two resolutions: Lower for fast loading, and then > click-on > any photo, to allow higher res. > > There seem to be 3 variants, but all labeled FD2 ?, and these all seem > to have two > 'Pin1 Square pad convention' - also no photo of the PCB rear ? > I can see a compact flash card, but no mention of how that relates to > Craignell Modules - is there a CF socket on the rear ? >=20 > -jgArticle: 114309
"wallge" <wallge@gmail.com> writes:
> I would like to superimpose some text into a video stream coming from a
> camera into my fpga.
> Lets say I would like to print the values of several registers to the
> screen as simple ascii text. This text would be superimposed over the
> incoming video stream. Does anyone know if there exists a core, or some
> free vhdl floating around somewhere to do this kind of thing?
> I have seen some cores that do VGA timing generation, then insert pixel
> values values from a look up table (but these dont do text from what I
> can tell, and must be controlled by a microprocessor).
>
What format is your incoming video in?
Assuming it's got something like an LVALID and FVALID (and DVALID if
the clk is not the same as the pixel clock), I would use a BRAM as a
character frame buffer, decode the registers and stick the cahracters
into that. Then another BRAM can have an array of bits indexed by
character (make them 8x8 for ease :-) that can be used by a process
which keeps track of the location of the pixel and which of the
character locations you are in.
You could have a small state machine run at the end of each frame to
update the character frame buffer with the values you want for next
time around during the vblank. Or double buffer.
Or do you really want to have something which looks like
ENTITY reg_to_screen
(
clk
reset
registervalue (31 downto 0)
xloc, yloc
vsync, hsync
video_out);
which you can then instantiate a number of times and then combine the
video_out signals together? If so, you'll end up duplicating the
character->pixels map unnecesarily.
There's some thoughts for you :-)
Cheers,
Martin
--
martin.j.thompson@trw.com
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html
Article: 114310quad wrote: > Hello > As I'd mentioned in one of my previous mails, I'm working on intrinsic > evolution. I'd like to know if its possible to generate netlists in > EDIF format from C itself for circuits, or will it be too complicated? > Regards > quad You can of course write a C-program that generates an EDIF netlsit. This is not very hard, as EDIF is a straight-forward ASCII-format. The standard is openly available and you can look at EDIF-files from standard examples in you FPGA toolkit. For circuits with a high degree of regularity or with many sophisticated parameters it makes sense to do so. But I would recommend you first to do some examples directly in VHDL/Verilog first so that you get a feeling, which structures are well suited for the tools. Regards, AndreasArticle: 114311
Hi Davy,
"Davy" <zhushenli@gmail.com> wrote in message
news:1168508109.724917.173270@i39g2000hsf.googlegroups.com...
> Hi all,
>
> I am new to CPU design and confused with two CPU term. That is
> interlock and stall. What's their difference? Does interlock and stall
> all do insert NOP and remove the data dependency?
The data dependency is a property of the program being executed, and is
never "removed" except by maybe changing the program.
In a machine where each instruction completes before the following
instruction starts, data dependencies don't cause any problems. However,
when a machine is pipelined, data dependencies and anti-dependencies can
lead to "hazards".
An interlock circuit detects these hazards. An interlock circuit may stall
one or more stages of the processor pipeline, often introducing a NOP-like
"bubble", to avoid the hazard and ensure correct program execution.
Note that there are other ways to manage hazards that do not involve an
interlock circuit, and that stalling the processor is only the simplest,
most basic way to avoid hazards. You may wish to read Hennessy and Patterson
for a proper description of more advanced techniques.
Cheers,
-Ben-
Article: 114312Hi Davy, Interlock in this case refers to 'dependencies solver'. It might be a simple stall logic or could be register renaming logicArticle: 114313
"Davy" <zhushenli@gmail.com> writes: > Hi all, > > I am new to CPU design and confused with two CPU term. That is > interlock and stall. What's their difference? Does interlock and stall > all do insert NOP and remove the data dependency? I am not a CPU guru, and here are some my cents. Hope they are useful. 1. "stall" is a term for pipeline, and "interlock" is a method to "stall" pipeline. 2. Both interlock and stall DO NOT insert NOP. It is the work done by compiler. Compiler could insert some NOPs in executable to avoid data hazard. > > I have copied a sentence from a CPU document "The interlock is > responsible for detecting read-after-write hazards and stalling the > pipeline until the hazard has been resolved. This avoids the need to > insert nop directives between dependent instructions, thus keeping code > size to a minimum, as well as simplifying assembler-level > programming." Interlock logic could lock the pipeline when data hazard is detected to make sure the right result. So, compiler or assembler do not insert NOPs to avoid hazard, so that code size is minimized. > > Best regards, > Davy > -- Yao Qi GNU/Linux DeveloperArticle: 114314
Hi, I was currently using picoblaze with RS-232 with the FPGA running at 50 MHz and it worked fine. I now need to run it at 62.5 MHz. From the information I hve gathered, to attain a baud rate of 115200, I would need a clock frequency of 115200 * 16 = 1843200 Hz or something close to that. In the picobalze hdl file, there is a counter that counts 27 cycle at 50 MHz to obtain 1851851 Hz and it seems to work fine with the RS-232. So I figure 33 cycles at 62.5 MHz to obtain 1893939 Hz should also work but I keep getting garbage on the terminal program on the computer. I have tried 32 cycles as well as 34 cycles without any luck. I was wondering if anybody has tried this before and can shed some light on the matter. Thanks a lot, AmishArticle: 114315
UARTS are good for a bit of a frequency mismatch but going from .47% error to 2.75% error appears to be too much for your system to handle. Consider dividing 62.5 MHz by 34 instead to get .27% error. It shouldn't be important that 1838235 Hz is less than 1843200 Hz but that it's much closer than 1893939 Hz. "axr0284" <axr0284@yahoo.com> wrote in message news:1168533692.658912.327530@i56g2000hsf.googlegroups.com... > Hi, > I was currently using picoblaze with RS-232 with the FPGA running at > 50 MHz and it worked fine. I now need to run it at 62.5 MHz. From the > information I hve gathered, to attain a baud rate of 115200, I would > need a clock frequency of 115200 * 16 = 1843200 Hz or something close > to that. > > In the picobalze hdl file, there is a counter that counts 27 cycle at > 50 MHz to obtain 1851851 Hz and it seems to work fine with the RS-232. > So I figure 33 cycles at 62.5 MHz to obtain 1893939 Hz should also work > but I keep getting garbage on the terminal program on the computer. I > have tried 32 cycles as well as 34 cycles without any luck. > > I was wondering if anybody has tried this before and can shed some > light on the matter. Thanks a lot, > AmishArticle: 114316
Hello Actually we have a timeframe constraint of about 3 months for the project. So wondering if generation of EDIF from C is possible within that timeframe, considering that this is just a module in the whole project. Would it be a better idea to pass parameters from C and use JHDL (www.jhdl.org) to generate the netlist directly? Can JHDL code be made generic for all kinds of circuits? Regards QuadArticle: 114317
Hello, I have been looking at my FIFO designs and considering if they are backward compatible from Virtex4 to Spartan. I have been using the FWFT First_Word_Fall_Through feature on the Virtex4 and when I compared waveforms of this with those from a CoreGen FIFO got different results. I am still using ISE 7.1.04 and the CoreGen models were Version 5. I did not see any FWFT switches on my CoreGen wizard. Are there any FWFT features in ISE 8.2? Also it seemed that without the FWFT feature, the Virtex4 FIFO required 4 clock cycles from the wr_en to the rd_en signals, while the CoreGen and the Virtex4 FIFO with FWFT on requires only 3. Brad Smallridge brad at AiVision dot comArticle: 114318
> Really > what I want is a function that would > convert the value of a register into say, hex or base 10 ascii text, > and then count the number of > rows/columns of video coming in, and insert black or white pixels into > the video stream as appropriate to make those characters appear > (superimposed) on the output video stream. Yeah. I might be able to help although I don't know what you are using. Xilinx? Spartans? Virtex? VHDL? Verilog? Can we assume that you already have a VGA display that is outputting? And so can we assume that you have row and column registers in your design? Brad Smallridge AiVision dot comArticle: 114319
I have tried that and I still get garbage. This is weird. I am wondering if the rest of the UART has something to do with this. Maybe additional changes need to be made. Amish John_H wrote: > UARTS are good for a bit of a frequency mismatch but going from .47% error > to 2.75% error appears to be too much for your system to handle. Consider > dividing 62.5 MHz by 34 instead to get .27% error. It shouldn't be > important that 1838235 Hz is less than 1843200 Hz but that it's much closer > than 1893939 Hz. > > > "axr0284" <axr0284@yahoo.com> wrote in message > news:1168533692.658912.327530@i56g2000hsf.googlegroups.com... > > Hi, > > I was currently using picoblaze with RS-232 with the FPGA running at > > 50 MHz and it worked fine. I now need to run it at 62.5 MHz. From the > > information I hve gathered, to attain a baud rate of 115200, I would > > need a clock frequency of 115200 * 16 = 1843200 Hz or something close > > to that. > > > > In the picobalze hdl file, there is a counter that counts 27 cycle at > > 50 MHz to obtain 1851851 Hz and it seems to work fine with the RS-232. > > So I figure 33 cycles at 62.5 MHz to obtain 1893939 Hz should also work > > but I keep getting garbage on the terminal program on the computer. I > > have tried 32 cycles as well as 34 cycles without any luck. > > > > I was wondering if anybody has tried this before and can shed some > > light on the matter. Thanks a lot, > > AmishArticle: 114320
Is it just me or is the documentation for the RocketIO (MGT) for the Xilinx Virtex4 very bad? I'm trying to find duty cycle requirements for the MGT clock. Is it OK to use a clock with a 40% duty cycle? Also, if anyone can point me to some better RocketIO (MGT) documentation for the hardware guys I'd appreciate it. I already have ug076. Thanks, DaleArticle: 114321
I think the issue might be in my code. I'll have to debug it. Amish axr0284 wrote: > I have tried that and I still get garbage. This is weird. I am > wondering if the rest of the UART has something to do with this. Maybe > additional changes need to be made. > Amish > > John_H wrote: > > UARTS are good for a bit of a frequency mismatch but going from .47% error > > to 2.75% error appears to be too much for your system to handle. Consider > > dividing 62.5 MHz by 34 instead to get .27% error. It shouldn't be > > important that 1838235 Hz is less than 1843200 Hz but that it's much closer > > than 1893939 Hz. > > > > > > "axr0284" <axr0284@yahoo.com> wrote in message > > news:1168533692.658912.327530@i56g2000hsf.googlegroups.com... > > > Hi, > > > I was currently using picoblaze with RS-232 with the FPGA running at > > > 50 MHz and it worked fine. I now need to run it at 62.5 MHz. From the > > > information I hve gathered, to attain a baud rate of 115200, I would > > > need a clock frequency of 115200 * 16 = 1843200 Hz or something close > > > to that. > > > > > > In the picobalze hdl file, there is a counter that counts 27 cycle at > > > 50 MHz to obtain 1851851 Hz and it seems to work fine with the RS-232. > > > So I figure 33 cycles at 62.5 MHz to obtain 1893939 Hz should also work > > > but I keep getting garbage on the terminal program on the computer. I > > > have tried 32 cycles as well as 34 cycles without any luck. > > > > > > I was wondering if anybody has tried this before and can shed some > > > light on the matter. Thanks a lot, > > > AmishArticle: 114322
"Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message news:12qcuru8aagv82d@corp.supernews.com... > I did not see any FWFT switches on my CoreGen wizard. > Are there any FWFT features in ISE 8.2? > Yes.Article: 114323
Jonathan Bromley wrote: > On Wed, 10 Jan 2007 18:41:44 -0700, Kevin Neilson > <kevin_neilson@removethiscomcast.net> wrote: > >> Has anyone ever been able to get Modelsim to model transport delays in >> Verilog? Verilog simulators, by default, use inertial delays, so if you >> have an assignment such as this: >> >> assign #4 sig_out = sig_in; >> >> then any pulse on sig_in that is less than 4ns will get swallowed. >> Modeling transport delays prevents this from happening. Modelsim claims >> to model transport delays using the +transport_int_delay option for >> vsim, but this just doesn't seems to work. > > I think you'll find that this option applies only to interconnect > delays that have been backannotated from an SDF file. The Verilog > language defines continuous driver delays and net delays to be > inertial, and I was under the impression that simulators aren't > supposed to disobey that. > > If you want transport delay in your own Verilog model, use > intra-assignment nonblocking delays - try tnis... > > always @(sig_in) sig_out <= #4 sig_in; > > (Of course, sig_out needs to be a variable now, not a net.) That is wonderful. It totally works. I wish I'd known this before. My Palnitkar book makes no reference to this (unsurprisingly) that I can see though I did find a reference in a book by Bhasker. I would like to be able to adjust the delay on-the-fly, in order to model pad/trace delays that change over time, but I don't think that's possible. I suppose maybe I could get a switchable delay doing something like this: always@(sig_in, dly_sel) sig_out <= dly_sel ? #4 sig_in : #5 sig_in; -KevinArticle: 114324
The method you just described sounds similar to what is done with MGT protocols. Send a special K character that can either be processed to waste time or thrown away to catch up. For small unknown differences that is a great idea. As for the FIFO solution I mentioned earlier, our group is using it to cross clock domains. We are using a NACK to control the sender and are also using extensive calculations to ensure that all FIFOs can handle a given data valid rate from the sender (because part of our system requirements is that we need to gurantee a minimum throughtput). ---Matthew Hicks "Peter Alfke" <alfke@sbcglobal.net> wrote in message news:1168489015.772863.289540@i39g2000hsf.googlegroups.com... > One solution is to have the transmitter include padding, extra bits or > words that the receiver recognizes and can, if necessary, "throw away" > = skip over. That way, the receiver does not need a back communication > to the transmitter. The price is of course a loss of throughput. > There is no free lunch. > Peter Alfke > > On Jan 10, 7:18 pm, "Rob" <robns...@frontiernet.net> wrote: >> As John stated, make sure you do the analysis and assure yourself you can >> use a FIFO, and if so, that it is large enough. We ran into the very >> problem--transmit clock faster than recieve clock--and our FIFO wasn't >> big >> enough--ooops! Furthermore, it was an ASIC--double oops!! The solution >> was >> to force the transmitter to use a slightly lower clock. We weren't off >> by >> much, less than 1%, but it was enough at times to cause problems. Had we >> not been able to slow the transmitter we would have been screwed!! >> >> "John_H" <newsgr...@johnhandwork.com> wrote in >> messagenews:12qak264aekr04b@corp.supernews.com... >> >> > Do you know what "large enough" is given the speeds of your two clock >> > domains? If your downstream clock domain is always slower than your >> > upstream time domain, you cannot get a FIFO large enough. >> >> > If you can determine the maximum sustained upstream rate (less than or >> > equal to the upstream clock frequency) and know the minimum sustained >> > downstream clock frequency, you can determine the FIFO size that will >> > guarantee a system that communicates all the information. If your >> > output >> > frequency isn't fast enough to keep up - ever - you're hosed from the >> > start. >> >> > Keep in mind there will be a maximum delay encountered when the FIFO >> > reaches full. >> >> > "Matthew Hicks" <mdhic...@uiuc.edu> wrote in message >> >news:eo3h81$id4$1@news.ks.uiuc.edu... >> >> Peter, >> >> >> Would your Asynchronous FIFO core handle this situation correctly >> >> given a >> >> large enough FIFO? >> >> >> ---Matthew Hicks >> >> >> "Peter Alfke" <p...@xilinx.com> wrote in message >> >>news:1168449451.035500.190590@p59g2000hsd.googlegroups.com... >> >>>I wrote a TechXclusives paper a while ago, on this exact subject: >> >>> You can click on the (ridiculously long) URL: >> >> >>>http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?iLanguageID=1&cate... >> >> >>> When the transmit clock is faster than the receive clock, there is of >> >>> course the danger of "overrunning" the receiver, and thus losing >> >>> data... >> >>> Peter Alfke, Xilinx >> >> >>> On Jan 10, 8:12 am, "Matthieu Cattin" <matthieu.cat...@cern.ch> >> >>> wrote: >> >>>> Signal can change on each rising edge or less often. >> >> >>>> "John_H" <newsgr...@johnhandwork.com> wrote in >> >>>> messagenews:12qa3g2otrg95e1@corp.supernews.com... >> >> >>>> > How often does the signal change relative to the two clocks? >> >> >>>> > "Matthieu Cattin" <matthieu.cat...@cern.ch> wrote in message >> >>>> >news:eo30bh$c3j$1@cernne03.cern.ch... >> >>>> >> Hi all, >> >> >>>> >> I have to transfert signals from a clock domain to another. >> >>>> >> First clock domain is fixed, but the second can be faster or >> >>>> >> slower >> >>>> >> than >> >>>> >> the first one. >> >> >>>> >> Does somebody can give me some help. >> >> >>>> >> Thanks >> >>>> >> Matthieu >
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