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thanks "motty =D0=B4=B5=C0=A3=BA " > skyworld wrote: > > well, the 312MHz clock is a input to FPGA. I do need four phases to > > sample the data so that data jitter could be reduce. It is very > > interesting that DCM could not output clk90 and clk270 when set it to > > high speed mode -- i got this information from Xilinx FAE and simulated > > this with ModelSim, but their datasheet and user guide doesn't mention > > this. My design has based on these four pahse clock and DCM > > performance and my PCB is ready for this. I have to find a way to solve > > this. > > > > by the way, what do you mean by that "IDELAY"? thanks. > > > > The DCM's limitations are explained in the Virtex 4 Switching > Characteristics data sheet which is found on their website. I've found > that you have to dig deeper on all technology to find real world > behavior. The User Guide is not the definitive answer. It really only > glosses over all the available features -- which are a lot! More > detail is found in other documentation and application notes. I would > never build a PCB based on just the user guide. Sorry. > > The Virtex 4 development boards are a VERY good investment. You can > try out all the features and figure out what you need. > > You can read about IDELAY is the User Guide to begin with. Then you'd > have to investigate the Switching Characteristics of IDELAY. And their > is also a ChipSync User Guide that REALLY goes in to detail about the > IDELAY.Article: 114501
Possibly not quite what you want but worth considering is our Broaddown4. It would need a FPGA programmed to support PCI-E (do you want conventional PCI) but it can support up to 3 more FPGAs that can be dynamically reprogrammed from the first FPGA. For convenional PCI our Broaddown2(Spartan-3) can act as a front end with a Swinyard1 module fitted to give anything up to a single Virtex-4 LX160 or SX55. Info on all these products here http://www.enterpoint.co.uk/boardproducts.html. John Adair Enterpoint Ltd. sheikh.m.farhan@gmail.com wrote: > Hi, > I am looking for a PCI card with an FPGA on it with reasonable capacity > of gates (15 million gates). I need to use this board as a hardware > accelerator in a PC environment. My exact requirements for the PCI card > are: > 1. should have a PCI controller/ bridge on it so that I dont have to > put PCI core on the FPGA. > 2. the FPGA should be configurable through PCI (that means the > programming pins of the FPGA should be routed to the PCI). > 3. seperate IO and data bus are preferred from/to the FPGA. > > > I will be using this hardware accelerator for speeding up DSP > algorithms. The application running on windows will have several such > DSP bitstreams and the user will be selecting the DSP bitstreams and > downloading it on the FPGA through PCI. Data will be pumped into the > FPGA through PCI using the data bus for processing while the status and > command operations will be managed through the IO pins. Once the > processing is done, the data will be read back by the application using > the same data bus. > > ANYONE KNOWS ANY SUCH BOARD FULFILLING MY REQUIREMENTS? > > Boards I have explored are: > 1. PCIS3BASE from cesys.com (supports only data bus) > 2. PCI Proto Board from techniprise.com (smaller FPGA) > > > regards > FahanArticle: 114502
In vhdl is it possible to run a process on both edges of a clock? I tried running one if-statement on the rising edge, and one on the negative but get an timing error. It won't synthesize. Most dual edge stuff is done at the IO pads where it is separated into single edge clock domains inside the FPGA. It might simulate, if you post your code we'll look at it, if you're still interested. Brad Smallridge AiVisionArticle: 114503
See http://groups.google.com/group/comp.arch.fpga/browse_thread/thread/5ed87d5b3adc5ead/20e5340d46a12b7b#20e5340d46a12b7b for this thread and see http://groups.google.com/group/comp.arch.fpga/browse_thread/thread/3cb7b9b1613a642e/1e5104ae5a6af54c#1e5104ae5a6af54c for the original thread (just one message; you can't seem to reply in it any more): "Running an application from external memory in Xilinx". As a followup, it seems that I don't know what allows debugging to successfully start once GDB is started and Run is selected. Is it something stupid like having to get the XMD prompt back in the XMD window? After multiple tries of reprogramming the board and relaunching XMD, then GDB, I finally have success and execution stops at the first breakpoint at main() and I'm ready to debug. This shouldn't be such a pain. If it's something stupid like having to get the XMD prompt back in the XMD window, a message should be printed out for new users. We shouldn't have to read manuals for this. We should have to read manuals only maybe to find out how to turn off the "novice user" messages once we are familiar with using the tool. I also redid "Update Bitstream with Processor Data" for the pointlessness of it (?). I kept getting "Program stopped at fffffffb" in the bottom framing of GDB and a blank screen, until it finally worked. Maybe it was the fiddling around in the XMD window that helped, disconnecting and reconnecting and then finally leaving it with the XMD prompt, but I'm still not sure. But if someone could point out a manual section where it explains this or maybe implies it by illustration that you have to read and interpret carefully, I'd like to know that. Jhlw wrote: > Hello rbal, > > What I did when creating a new application was to also > copy the linker script from "TestApp_Memory" and then > configure that as my linker script. That used the BRAM. > Then I used "Generate Link Script" and the size of the > boot section was 0x00000010. Then I just used the combo > box to select SRAM. So make sure that you create > TestApp_Memory when you use BSB to set up your > system. > Later, after you successfully load your code with GDB, > it seems to make a difference between clicking on the > Run icon (small pic of running man) and using the drop- > down menu Run command. If you don't click on the icon, > but click on the menu Run command, it seems to work > and stop on the breakpoint at the beginning of main, > otherwise the GDB window goes blank and the message > at the bottom of the window frame says "stopped". > > Regards, > -James > > rbal wrote: > > >Jhlw wrote: > > > Hello All, > > > > > > I figured out how to run an application from external memory in Xilinx. > > > I have EDK ver 8.2.01i and an ML403 board. > > > What you do is "Mark to init BRAMs" on the default bootloop app in > > > the Applications window pane, update your bitstream and then load > > > it into the board using iMPACT. > > > Change your linker script using "Generate Link Script" for your > > > large application and set the .text section to SRAM. Rebuild your > > > app. > > > > > > > I have done upto this in ML402 board.But I am not able to run program > > from external memory. > > > > > You also have to set the .boot section (0x00000010) to SRAM. > > > > How to set the .boot section? Have I to create a new section and > > select memory as SRAM.But it shows "0 bytes" and I couldn't select the > > address - 0x00000010.And I am not able to run application from external > > memory.Pls.advice me.Thanks > > > > Regards, > > R.BalArticle: 114504
Hi, I need to generate a 70MHz clock from 210MHz. Is there any way to generate it rather than using a DCM. Thanks, SudheerArticle: 114505
It's very simple: Take two Logic Cells (each a LUT and a Flip-flop) and feed both Q outputs to the inputs of both LUTs. Imagine any one (of many possible) sequence on the two Q outputs that repeats after 3 states. Then implement the required logic in each LUT. I don't want to make it too trivially simple for you. A little thinking strengthens the brain. Peter Alfke On Jan 17, 9:20 pm, "K. Sudheer Kumar" <ksudheerku...@gmail.com> wrote: > Hi, > > I need to generate a 70MHz clock from 210MHz. Is there any way to > generate it rather than using a DCM. > > Thanks, > > SudheerArticle: 114506
Hi Clark, the link does not seem to be working.......... Thanks Farhan cpope wrote: > Try www.edt-inc.com > > -Clark > > <sheikh.m.farhan@gmail.com> wrote in message > news:1169036835.705100.143430@a75g2000cwd.googlegroups.com... > > Hi, > > I am looking for a PCI card with an FPGA on it with reasonable capacity > > of gates (15 million gates). I need to use this board as a hardware > > accelerator in a PC environment. My exact requirements for the PCI card > > are: > > 1. should have a PCI controller/ bridge on it so that I dont have to > > put PCI core on the FPGA. > > 2. the FPGA should be configurable through PCI (that means the > > programming pins of the FPGA should be routed to the PCI). > > 3. seperate IO and data bus are preferred from/to the FPGA. > > > > > > I will be using this hardware accelerator for speeding up DSP > > algorithms. The application running on windows will have several such > > DSP bitstreams and the user will be selecting the DSP bitstreams and > > downloading it on the FPGA through PCI. Data will be pumped into the > > FPGA through PCI using the data bus for processing while the status and > > command operations will be managed through the IO pins. Once the > > processing is done, the data will be read back by the application using > > the same data bus. > > > > ANYONE KNOWS ANY SUCH BOARD FULFILLING MY REQUIREMENTS? > > > > Boards I have explored are: > > 1. PCIS3BASE from cesys.com (supports only data bus) > > 2. PCI Proto Board from techniprise.com (smaller FPGA) > > > > > > regards > > Fahan > >Article: 114507
This is not a hard problem if you don't care about duty cycle. I'll leave that for you to logic out, but if you need 50% duty cycle then there are tricks. Peter Alfke from Xilinx wrote an excellent article about clock dividers titled "Unusual Clock Dividers." It was published the Xilinx's Xcell Journal. I believe issue 33, but it appears Xilinx has gotten rid of that article as it's archives don't go back far at all anymore. You could probably find it through some googling, but this brings up another point: Why would Xilinx remove it's archives? It's not like the material was dated. That particular article has been of use to me several times. Peter wrote a great article. I'd like to see it come back. -Arlen K. Sudheer Kumar wrote: > Hi, > > I need to generate a 70MHz clock from 210MHz. Is there any way to > generate it rather than using a DCM. > > Thanks, > > SudheerArticle: 114508
It can be done if invert the first clock and use that. I would still adivse against it. There really isn't a need to use both edges of a clock, it just least to buggy hard to read code. If you need a faster clock use a DCM and speed it up. ---Matthew Hicks "John" <null@null.com> wrote in message news:eea186e.-1@webx.sUN8CHnE... > In vhdl is it possible to run a process on both edges of a clock? I tried > running one if-statement on the rising edge, and one on the negative but > get an timing error.Article: 114509
Hi Peter, Thanks for your suggestion. I would appreciate your providing me a copy of your article "Unusual Clock Dividers". Sudheer. Peter Alfke wrote: > It's very simple: > Take two Logic Cells (each a LUT and a Flip-flop) and feed both Q > outputs to the inputs of both LUTs. > Imagine any one (of many possible) sequence on the two Q outputs that > repeats after 3 states. > Then implement the required logic in each LUT. > I don't want to make it too trivially simple for you. A little thinking > strengthens the brain. > Peter Alfke > > On Jan 17, 9:20 pm, "K. Sudheer Kumar" <ksudheerku...@gmail.com> > wrote: > > Hi, > > > > I need to generate a 70MHz clock from 210MHz. Is there any way to > > generate it rather than using a DCM. > > > > Thanks, > > > > SudheerArticle: 114510
sudheer schrieb: > Hi Peter, > > Thanks for your suggestion. I would appreciate your providing me a copy > of your article "Unusual Clock Dividers". > > Sudheer. dear Sudheer, isnt goodle your friend too? http://www.nalanda.nitc.ac.in/industry/appnotes/xilinx/documents/xcell/xl33/xl33_30.pdf AnttiArticle: 114511
kelvins wrote: > DEAR ALL, > > As I am a beginner in ARM AHBA bus protocol. I cant > understand why AHBA bus need to limit 1Kbyte boundary? > (As 1KByte (256 word) boundary crossing within a burst is Illegal.) Probably to minimize the size of the adders needed for address calculation, but I'm guessing. Is the limit really 1K? Thought it was bigger. Cheers, JonArticle: 114512
I wonder if thats only from Europe or is that something at Xilinx server, all login attemps time-out today :( AnttiArticle: 114513
"gallen" <arlencox@gmail.com> wrote in message news:1169101376.940807.115180@v45g2000cwv.googlegroups.com... > > You could probably find it through some googling, but this brings up > another point: Why would Xilinx remove it's archives? It's not like > the material was dated. > Stop whining and start searching! :-) http://web.archive.org/web/20050404010919/www.xilinx.com/xcell/xl33/xl33_30.pdf HTH, Syms.Article: 114514
Hi, I plan to interface a 250MHz ADC with an Spartan 3E-1600. The ADC gives out 8 data lines and 1 clock line, all via LVDS. The data should be captured an put into a blockram. The OFFSET IN constraint, which I want to meet, says, that the DATA should be available 0.97ns before the CLOCK. So far I have the data-lines into their IBUFDS (8 times) and into the data-input of the BRAM. Clock goes into a IBUFGDS, into the DCM, into a BUFG and into the clock of the BRAM. DCM_FEEDBACK is fed from the BUFG as well. I have learned that from "UG331", the "Spartan-3 User Guide".1] So I set the DCM to "SOURCE_SYNCHRONOUS" and the phase shift to 0, for testing. I get in the Timing Analysis: Slack: -2.134ns = 0.97ns setup - (4.5ns datapath - 1.4 ns clockpath) So i set the PS to 120, just for curiousity: Exactly the same results. The phaseshifting is accounted, in the DATASHEET the internal clock (which is correctly infered from the external clock on the input of the DCM) is displayed with a phase from 1.875ns, but this is not reflected in the constraints. Am I missing something? Thanks a lot, Christian 1] It says there: "The SOURCE_SYNCHRONOUS setting essentially zeros out any phase difference between the incoming clock and the deskewed output clock from the DCM. The FPGA application must then adjust the clock timing using either the Fixed or Dynamic Fine Phase Shift mode."Article: 114515
> I wonder if thats only from Europe or is that something at Xilinx > server, all login attemps time-out today :( Same here. ChristianArticle: 114516
Sorry, try http://www.edt.com/gen_products.html <sheikh.m.farhan@gmail.com> wrote in message news:1169099439.983075.46930@s34g2000cwa.googlegroups.com... > Hi Clark, > the link does not seem to be working.......... > > Thanks > Farhan > > cpope wrote: > > Try www.edt-inc.com > > > > -Clark > > > > <sheikh.m.farhan@gmail.com> wrote in message > > news:1169036835.705100.143430@a75g2000cwd.googlegroups.com... > > > Hi, > > > I am looking for a PCI card with an FPGA on it with reasonable capacity > > > of gates (15 million gates). I need to use this board as a hardware > > > accelerator in a PC environment. My exact requirements for the PCI card > > > are: > > > 1. should have a PCI controller/ bridge on it so that I dont have to > > > put PCI core on the FPGA. > > > 2. the FPGA should be configurable through PCI (that means the > > > programming pins of the FPGA should be routed to the PCI). > > > 3. seperate IO and data bus are preferred from/to the FPGA. > > > > > > > > > I will be using this hardware accelerator for speeding up DSP > > > algorithms. The application running on windows will have several such > > > DSP bitstreams and the user will be selecting the DSP bitstreams and > > > downloading it on the FPGA through PCI. Data will be pumped into the > > > FPGA through PCI using the data bus for processing while the status and > > > command operations will be managed through the IO pins. Once the > > > processing is done, the data will be read back by the application using > > > the same data bus. > > > > > > ANYONE KNOWS ANY SUCH BOARD FULFILLING MY REQUIREMENTS? > > > > > > Boards I have explored are: > > > 1. PCIS3BASE from cesys.com (supports only data bus) > > > 2. PCI Proto Board from techniprise.com (smaller FPGA) > > > > > > > > > regards > > > Fahan > > > >Article: 114517
To your question, if you want to be 100% compatible (and maybe get your slave to pass in various verification suites such as e/Specman, SystemC etc.) then yes, you have to do exactly as you suggested. If you are doing a proprietry system and * you know exactly how all the slaves will behave (e.g. because you designed them yourself) * you or nobody else is ever likely to try and reuse your code inanother design then who cares, do whatever you want ( but your not 100% AMBA) If your are doing INCR bursts it's not such a problem. Whenever the address is modulo 1K just change HTRANS from SEQ to NSEQ. You don't have to physically insert a wait state, just insert the NSEQ on the fly. If you are doing fixed length bursts (INCR4, INCR8, INCR16) it's a bit more difficult (but probably more efficient). Here you need to know at burst start whether you will cross a 1K boundary. If so, just change the current burst type to INCR and insert an NSEQ as above on the 1K boundary. As to why ARM did it, no idea really. But, * it gives you smaller (and faster) logic in the HSEL address decoder * most memory maps are segmented anyway * slaves only need to monitor for (HTRANS == NSEQ) && (HSEL == '1') && (HREADY == '1') to know whether they are selected. After that they can generate the remaining addresses themselves internally. So it's nothing really worth complaining about too much. Hope this helps, C.Article: 114518
On 18 Jan 2007 02:40:26 -0800, "Antti" <Antti.Lukats@xilant.com> wrote: >I wonder if thats only from Europe or is that something at Xilinx >server, all login attemps time-out today :( > >Antti I have no such problem logging in from Spain ZaraArticle: 114519
Jhlw wrote: > XMD, then GDB, I finally have success and execution > stops at the first breakpoint at main() and I'm ready to > debug. This shouldn't be such a pain. If it's something If I'm not mistaken, if you hit the "step out of" button at this point it will run to completion. -JeffArticle: 114520
"Zara" <me_zara@dea.spamcon.org> wrote in message news:p0suq2l401ochgao95lmuh5um38k73njh3@4ax.com... > On 18 Jan 2007 02:40:26 -0800, "Antti" <Antti.Lukats@xilant.com> > wrote: > >>I wonder if thats only from Europe or is that something at Xilinx >>server, all login attemps time-out today :( >> >>Antti > I have no such problem logging in from Spain > > Zara Guys, It's back up. I couldn't login earlier, but now I can. HTH, Syms. (UK)Article: 114521
Charles, NG wrote: > To your question, if you want to be 100% compatible (and maybe get your > slave to pass in various verification suites such as e/Specman, SystemC > etc.) then yes, you have to do exactly as you suggested. If you are > doing a proprietry system and > * you know exactly how all the slaves will behave (e.g. because you > designed them yourself) > * you or nobody else is ever likely to try and reuse your code inanother > design > then who cares, do whatever you want ( but your not 100% AMBA) > > If your are doing INCR bursts it's not such a problem. Whenever the > address is modulo 1K just change HTRANS from SEQ to NSEQ. You don't have > to physically insert a wait state, just insert the NSEQ on the fly. If > you are doing fixed length bursts (INCR4, INCR8, INCR16) it's a bit more > difficult (but probably more efficient). Here you need to know at burst > start whether you will cross a 1K boundary. If so, just change the > current burst type to INCR and insert an NSEQ as above on the 1K boundary. > > As to why ARM did it, no idea really. But, > * it gives you smaller (and faster) logic in the HSEL address decoder > * most memory maps are segmented anyway > * slaves only need to monitor for (HTRANS == NSEQ) && (HSEL == '1') && > (HREADY == '1') to know whether they are selected. After that they can > generate the remaining addresses themselves internally. > So it's nothing really worth complaining about too much. > > Hope this helps, > C. > Correct. In addition, this design rule also prevent a burst from going across multiple AHB slaves. Section 3.8 Address decoding of AMBA spec 2.0 mentioned that the minimum size of an AHB slave is 1KB. By having this rule that limit the burst within the 1kB boundary, we can prevent a situation where a burst going across two slaves, with the second slave get a burst with first HTRANS showing as SEQ instead of NSEQ. regards, JosephArticle: 114522
Probably due to SP1 rollout of ISE 9.1. Must be an interesting peak in web stats when something like this goes live. John Adair Enterpoint Ltd. Symon wrote: > "Zara" <me_zara@dea.spamcon.org> wrote in message > news:p0suq2l401ochgao95lmuh5um38k73njh3@4ax.com... > > On 18 Jan 2007 02:40:26 -0800, "Antti" <Antti.Lukats@xilant.com> > > wrote: > > > >>I wonder if thats only from Europe or is that something at Xilinx > >>server, all login attemps time-out today :( > >> > >>Antti > > I have no such problem logging in from Spain > > > > Zara > > Guys, > It's back up. I couldn't login earlier, but now I can. > HTH, Syms. (UK)Article: 114523
John Adair schrieb: > Probably due to SP1 rollout of ISE 9.1. Must be an interesting peak in > web stats when something like this goes live. > > John Adair > Enterpoint Ltd. > > Symon wrote: yeah. funny Xilinx is delaying information - 9.1 was just now announced and SP1 availability hasnt announced at all yet. it seems that in 9.1 there is finally SPI indirect programming added to impact! AnttiArticle: 114524
Hi, I studied this article. It is very interesting, and the resources consumption is very low. For a general purpose, I think Anydivider can help. In this case, just enter "3", and then get the verilog code and the waveform. For more features, please visit http://www.topweaver.com/doc/tad/tad.htm Download http://www.topweaver.com/download.htm TAD "Antti =D0=B4=B5=C0=A3=BA " > sudheer schrieb: > > > Hi Peter, > > > > Thanks for your suggestion. I would appreciate your providing me a copy > > of your article "Unusual Clock Dividers". > > > > Sudheer. > dear Sudheer, > > isnt goodle your friend too? > > http://www.nalanda.nitc.ac.in/industry/appnotes/xilinx/documents/xcell/xl= 33/xl33_30.pdf >=20 > Antti
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