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blisca wrote: > Hi to all > > i'm a beginner tryin to build some application with a scraped xc2v3000 > > after generating a bit file with the ISE,i try to configure the FPGA ;iMPACT > recognizes it but it looks that there is no erase or write option active > > consider that: > my board is home made > the device is a virtex2 that as you know better than me it has a 1,5V > core,but my programming cable (digilent) is rated down to 1,8V Virtex 2-FPGAs, as well as all other (currently available) FPGAs from Xilinx are SRAM-based. There's no flash memory to "erase" or "write" inside the FPGA. It loses its configuration when you power it off. Of course that means you have to load the FPGA with iMPACT (or a configuration PROM, or external microcontroller, if you have something like that on the board) every time you power up the board, otherwise the FPGA won't do anything. HTH, Sean -- My email address is only valid until the end of the month. Go figure what the address is going to be after that...Article: 114701
Phil Hays wrote: > > There are multiple ways to avoid the unstable cases. A few that come to > mind with little effort: > > 1) Force the previous carry wrap around input into the LSB until the carry > wrap around output from the MSB is stable. This has the side effect of > making the result (positive or negative zero) depend on the previous > computation. (I think that the CDC6600 used this method) > > 2) If the carry look ahead shows all propagate bits are '1', then generate > a carry wrap around input into the LSB = '1' regardless of the carry wrap > around output from the MSB or any generate bits. This has the side effect > of producing only positive zeros for any add unless both operands were > negative zeros. > > 3) Force a carry wrap around input of '0' until the carry wrap around > output is stable. This has the side effect of never producing a positive > zero output for any add unless both operands were positive zeros. (Hand > computed examples often use this method) > > 4) Force a carry wrap around input of '1' until the carry wrap around > output is stable. This has the side effect of producing only positive > zeros any add unless both operands were negative zeros. > > Any method that must decide between two correct answers may take forever > to come to one of the two answers. > > This post started with the question how ones' complement is best done on FPGAs (Xilinx) From the discussion we learned that interconnecting the carry-out and carry-in is a bad idea, as this can become unstable when A and ~A are added. (Thanks for clarifying this!) With your suggestions in mind I've tried to come up with a couple of alternatives to build a 16 bit ones' complement adder, requiring a single clock cycle adding the operands A and B : 1. Make a chain of two 16 bit two's complement adders both calculating A+B. Use the carry-out of one of the adders as carry-in for the other adder. This is like building a 32bit adder calculating A&B + B&A. The 16 most significant bits are used as the result. 2. Use a single 16 bit two's complement adder with end-around carry. If we put a flip flop triggered on the falling edge in the carry loopback path we can avoid the instability problems. On the rising edge this flip flop should be set to zero, on the falling edge it clocks in the carry-out. 3. Instantiate two adders. One calculates A+B+0 and the other A+B+1. Then add a 2:1 multiplexer and use the carry-out of A+B+0 to select the right sum. If the carry-out is zero, multiplex A+B+0 onto the output, otherwise multiplex the result of A+B+1 to the output I guess 1 & 2 will reach similar speeds, but 2 uses less hardware. Option 3 seems interesting as it could be faster then the other alternatives. I would be happy to hear your ideas about this! Koen.Article: 114702
HI Nagaraj, Look at the User Guide for GTP: http://direct.xilinx.com/bvdocs/userguides/ug196.pdf There is a whole migration section that covers the differences too. Also if you contact your FAE, they might be able to provide you with more details. Thanks Duth nagaraj wrote: > Hi, > > I m looking for differences between rocketio MGT and GTP (both > architectural as well as the way they are used). > > please reply if anybody knows anything in this regard. > > > Thanks, > NagarajArticle: 114703
http://direct.xilinx.com/bvdocs/userguides/ug196.pdf Ever used Google? ;-)Article: 114704
HI Eilert, Tim is correct. Modular design and Incremental design was too flawed and that is why partitions is supposed to solve. The documentation is currently being worked on right now. It will be available soon in the Synthesis and Simulation Design Guide and possibly in a solution record as well. The flow is extremely simple. No more pims or anything. The key is to ensure that you have designed a good hierarchal design. Once you have build the design correctly, then you can just use PN and right click on each module and ask to preserve it. That is all. Then the tools take care of the rest. The chapter in the Dev Sys Ref Guide goes over how to do this in Tcl. If you need more information, please contact your FAE and they can assist you with getting more collateral on this new flow. Also two things. This does not do a lot of preservation if you change timing constraints. It works mainly for HDL changes only. Also right now it works with XST. Synplicity support is coming soon. Thanks Duth backhus wrote: > Hi Tim, > I read about partitions in the Tcl chapter of the ISE9 documentation, > but haven't seen any further explanation about that flow yet. Do you > have a link? > best regards > Eilert > > Tim Verstraete schrieb: > > i think they were replaced with the partitions flow (ISE8.2i)? or am i > > wrong? > > > > backhus schreef: > >> Hi, > >> while Iwere reading some chapters of the new ISE9 Development System > >> Reference guide I happened to notice that the chapters about Incremental > >> Design and Modolar Design are gone. > >> > >> What happened? Have these approaches been dropped? If so, I would like > >> to know the reasons. Is there some new (better) approach? Or have these > >> chapters just moved to some yet unpublished ISE9 document? (I know they > >> are still available in the ISE8 doc files.) > >> > >> Best regards > >> Eilert > >Article: 114705
stephen.craven@gmail.com wrote: > Is it possible to infer BRAMs (or any dual-port RAM) that has differing > port widths? Not right now - 9.1i. It is coming soon.. > > I can find no mention of this in the XST guide. > > StephenArticle: 114706
hey thanks for reply... i have both the user guides with me.... and am going through it.... but im looking for hearing from somebody who has worked on it. if anybody has used v4 MGT then pls giv me u r mail id so that we can discuss. Thanks, nagarajArticle: 114707
Eric Smith <eric@brouhaha.com> writes: > "bgshea" <bgshea@gmail.com> writes: >> I'm looking for POSITIVE feedback on Xilinx ISE. > > As compared to what? > > Xilinx ISE is the best development software for Xilinx FPGAs that > I've ever used. If by ISE we mean the GUI (as I think we do) then I disagree... The best development environment I have ever used for Xilinx devices is Emacs (with vhdl-mode) and a command-line build script :-) I had problems with ISE crashing when reading files of network drives, which is what drove me to build scripts, but I'd not go back now! I still have to use the chipscope core inserter from the GUI though. When that works off the command-line, we'll really be there! -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 114708
John Adair <g1@enterpoint.co.uk> wrote: >For those asking first photo of DIL FPGA modules Craignell1/2/3 are now >on our website. Modules have a very tiny packaged Spartan-3E and we >have made them 5V tolerant and capable of reaching 5V CMOS levels with >pullup resistors. How is the solder pads parallell to the dip holes wired?, I assumed first directly to dip terminals, but then the pcb photo seems to suggest otherwise. Can the 5V tolerant I/O directions be set per pin or is it required to be set in chunks of 4,8,16 bits etc.. ? Btw, any chance for a metric ruler in the photo? ;) Thanks for a good product anyway.Article: 114709
Sean Durkin <news_jan07@durkin.de> wrote in message 51m2p6F1k95ubU1@mid.individual.net... > blisca wrote: > > Hi to all > > > > i'm a beginner tryin to build some application with a scraped xc2v3000 > > > > after generating a bit file with the ISE,i try to configure the FPGA ;iMPACT > > recognizes it but it looks that there is no erase or write option active > > > > consider that: > > my board is home made > > the device is a virtex2 that as you know better than me it has a 1,5V > > core,but my programming cable (digilent) is rated down to 1,8V > Virtex 2-FPGAs, as well as all other (currently available) FPGAs from > Xilinx are SRAM-based. There's no flash memory to "erase" or "write" > inside the FPGA. It loses its configuration when you power it off. > > Of course that means you have to load the FPGA with iMPACT (or a > configuration PROM, or external microcontroller, if you have something > like that on the board) every time you power up the board, otherwise the > FPGA won't do anything. > ok,right,no external memory,so nothing to erase and de-flagging the verify option the fpga is successfully programmed maybe i'm too drunk after soldered tiny wires with cheap lens on the bottom of this BGA so i did this almost senseless question thank you againArticle: 114710
Hi all, I'm newbie in FPGA, and want to build my own FPGA board. Actually, I already have my own development board (which is Spartan-3E Starter Kit), but I would feel so guilty if I don't build my own board =P Actually, which part of the FPGA datasheet that is everyone read to determine which power regulator IC that matches the FPGA ? I've already read the Spartan-3E's power requirement. All that I can get is that I will need 1.2V, 2.5V, and 3.3V regulator (which can power up in any order), but I don't find current rating for it. The datasheet said that I should consult to XPower for the exact current requirement. Does anyone do the same thing (measure the current and do simulation in XPower) before determining the power regulator IC ? Or there are some guidelines for typical applications ? Thank you very much for your help -danielArticle: 114711
pbgbbrsh@ludd.invalid schrieb: > John Adair <g1@enterpoint.co.uk> wrote: > >For those asking first photo of DIL FPGA modules Craignell1/2/3 are now > >on our website. Modules have a very tiny packaged Spartan-3E and we > >have made them 5V tolerant and capable of reaching 5V CMOS levels with > >pullup resistors. > > How is the solder pads parallell to the dip holes wired?, I assumed first > directly to dip terminals, but then the pcb photo seems to suggest otherwise. > > Can the 5V tolerant I/O directions be set per pin or is it required to be set > in chunks of 4,8,16 bits etc.. ? > > Btw, any chance for a metric ruler in the photo? ;) > > Thanks for a good product anyway. all ios are bidir without setting dir, they level shift is bidir quickswitch AnttiArticle: 114712
CP132 package 6.5x6.5 mm for S3E/S3 is already there. See it on our Craignell modules here http://www.enterpoint.co.uk/component_replacements/craignell.html. The only thing with 0.5mm ball grids is the pcb technology you need to use to achieve a design. Getting the alignment correct in assembly is also fun. As to S3AN it would be nice but may not be practical depending on the approach taken by Xilinx in implementing the loading mechanism. We will all have to wait until the marketeers are ready to show you more. John Adair Enterpoint Ltd. Antti wrote: > Austin Lesea schrieb: > > > Antti, > > > > No problem. We have to release our software on a regular schedule, so > > there is no holding it back. > > > > I would caution that whatever is revealed in the software may be updated > > or changed in the future, so the recommendation to work with our FAEs > > (if you really want to use a product before its release) is still valid. > > > > Austin > Huh. > tnx. > > I just pointed out to some info that is revealed by the WP 9.1, things > that are to my understanding command knowledge as of today. > > The fact that actual product release announce are not in sync with > software updates is a bit confusing. For me at least, but I guess that > explains why I failed so miserable on brainbench online examps for: > "SCM: Software Configuration Management". > > At the moment I can only say that S3AN looks like REALLY REALLY nice > FPGA! A real nice one. > And I can only whish that package options would include > VQ64 > DIP40 > QFN48 > ;) kidding. > but really, a package with outline 8by8 mm or less would be really > nice. > Altera is currently leading in this regard the MAX II has 0.5mm 100 > ball BGA with measueres 6by6mm ! > > thats a real dream package. > ok, I can little relax the specs, S3AN in 8bx8 mm microFPGA would be > close to a truedream as well. > > AnttiArticle: 114713
John Adair schrieb: > CP132 package 6.5x6.5 mm for S3E/S3 is already there. See it on our > Craignell modules here > http://www.enterpoint.co.uk/component_replacements/craignell.html. > > The only thing with 0.5mm ball grids is the pcb technology you need to > use to achieve a design. Getting the alignment correct in assembly is > also fun. > > As to S3AN it would be nice but may not be practical depending on the > approach taken by Xilinx in implementing the loading mechanism. We will > all have to wait until the marketeers are ready to show you more. > > John Adair > Enterpoint Ltd. > > Antti wrote: > > Austin Lesea schrieb: > > > > > Antti, > > > > > > No problem. We have to release our software on a regular schedule, so > > > there is no holding it back. > > > > > > I would caution that whatever is revealed in the software may be updated > > > or changed in the future, so the recommendation to work with our FAEs > > > (if you really want to use a product before its release) is still valid. > > > > > > Austin > > Huh. > > tnx. > > > > I just pointed out to some info that is revealed by the WP 9.1, things > > that are to my understanding command knowledge as of today. > > > > The fact that actual product release announce are not in sync with > > software updates is a bit confusing. For me at least, but I guess that > > explains why I failed so miserable on brainbench online examps for: > > "SCM: Software Configuration Management". > > > > At the moment I can only say that S3AN looks like REALLY REALLY nice > > FPGA! A real nice one. > > And I can only whish that package options would include > > VQ64 > > DIP40 > > QFN48 > > ;) kidding. > > but really, a package with outline 8by8 mm or less would be really > > nice. > > Altera is currently leading in this regard the MAX II has 0.5mm 100 > > ball BGA with measueres 6by6mm ! > > > > thats a real dream package. > > ok, I can little relax the specs, S3AN in 8bx8 mm microFPGA would be > > close to a truedream as well. > > > > Antti John, please read http://www.xilinx.com/bvdocs/packages/cp132.pdf or measure on your board CP132 is 8 by 8 the smallest kinda FPGA is today MAXII in true 6 by 6 (outer dimensions!) but, well CP132 is package too :) AnttiArticle: 114714
Martin Thompson wrote: > If by ISE we mean the GUI (as I think we do) then I disagree... > > The best development environment I have ever used for Xilinx devices > is Emacs (with vhdl-mode) and a command-line build script :-) A man after my own heart.. > I had problems with ISE crashing when reading files of network drives, > which is what drove me to build scripts, but I'd not go back now! Do you mind sharing your scripts? I have some makefiles I leeched off someone them hacked up, however I still haven't worked out simulation properly.. -- Daniel O'Connor software and network engineer for Genesis Software - http://www.gsoft.com.au "The nice thing about standards is that there are so many of them to choose from." -- Andrew Tanenbaum GPG Fingerprint - 5596 B766 97C0 0E94 4347 295E E593 DC20 7B3F CE8CArticle: 114715
Hi Corer, "Corer" <corer@somewhere.net> wrote in message news:a4ath.72319$wP1.59658@newssvr14.news.prodigy.net... > Thanks for the info... I think I tried driving it from > 50MHz and didn't make any appreciable difference. > Could it be my oscillator is that bad? > Are you using j8 connector? > Do you see anything wrong with my vhdl? (first > message in this thread) > > I do not really know whether it is at all possible, > but could share your code, so I could try and run > it on my nexys? It would be just great. > > I tried to look at http://www.derepas.com/fabrice/hard/ > it doesn't seem to work (at least right now). I'll try again > later Not my page, hopefully you will be able to view it later. I tried it this evening and it seems to be up. Doubt your oscillator is bad if you are seeing anything. Try a simple divide by 2 or 4 circuit and check the output with your scope. I am using J8. Have you stipulated a constraint of 100MHz input for the mClk pin to see if your design can run at that speed? 10ns clock period doesn't leave much room to play with. Thing that immediately strikes me with your code is that the vertical count is not synchronized to the horizontal count. Best to make the Vcount a function of Hcounts. If your maths were not 100%, or a pulse or 2 got lost, then the HSync and VSync signals can get back into sync again at the end of each frame. RedArticle: 114716
kunil wrote: > Hi all, > > I'm newbie in FPGA, and want to build my own FPGA board. Actually, I > already have my own development board (which is Spartan-3E Starter > Kit), but I would feel so guilty if I don't build my own board =P > > Actually, which part of the FPGA datasheet that is everyone read to > determine which power regulator IC that matches the FPGA ? > > I've already read the Spartan-3E's power requirement. All that I can > get is that I will need 1.2V, 2.5V, and 3.3V regulator (which can power > up in any order), but I don't find current rating for it. The datasheet > said that I should consult to XPower for the exact current requirement. > > Does anyone do the same thing (measure the current and do simulation in > XPower) before determining the power regulator IC ? Or there are some > guidelines for typical applications ? > > Thank you very much for your help Choosing power supplies for parts is as much art as science, especially in the world of programmable logic where the load can vary due to upgraded / 'fixed' functionality. Unless you are certain of your power requirements, then provide a supply that can handle the worst case requirements. What *those* are depend on the core [which also determines the number of DCMs] and number of IO pins. 1.2V -> Core 2.5V -> DCMs, JTAG chain 3.3V -> IO I usually use a linear regulator for the DCM power. Cheers PeteS > -danielArticle: 114717
>> Now all you need is a Gerber-driven solder paste dot printer! They >> exist, and news of an affordable unit for prototyping would be interesting. >Following up myself, the Essemtec CDS6700 solder paste printer seems to >cost around $25,000. Not quite affordable ;-) Makes me wonder what it would cost to build x-y table and reuse a inkjet cartridge ;)Article: 114718
Antti <Antti.Lukats@xilant.com> wrote: >pbgbbrsh@ludd.invalid schrieb: >> John Adair <g1@enterpoint.co.uk> wrote: >> >For those asking first photo of DIL FPGA modules Craignell1/2/3 are now >> >on our website. Modules have a very tiny packaged Spartan-3E and we >> >have made them 5V tolerant and capable of reaching 5V CMOS levels with >> >pullup resistors. >> >> How is the solder pads parallell to the dip holes wired?, I assumed first >> directly to dip terminals, but then the pcb photo seems to suggest otherwise. >> >> Can the 5V tolerant I/O directions be set per pin or is it required to be set >> in chunks of 4,8,16 bits etc.. ? >> >> Btw, any chance for a metric ruler in the photo? ;) >> >> Thanks for a good product anyway. >all ios are bidir without setting dir, they level shift is bidir >quickswitch Any limit in frequency, ampere-load, capacitance?Article: 114719
>which is a WINE port. One user reports some ISE 8.2 compatibility. Of >course, what we really need is a Mac port of the Xilinx tools. Won't the linux-32bit version run under Mac OS X ..? ISE runs on FreeBSD and Mac OS X is based FreeBSD.Article: 114720
Hi Pete, Some comments in line:- "PeteS" <PeterSmith1954@googlemail.com> wrote in message news:1169556506.624001.4310@l53g2000cwa.googlegroups.com... > > Choosing power supplies for parts is as much art as science, especially > in the world of programmable logic where the load can vary due to > upgraded / 'fixed' functionality. > Only if you're a rubbish scientist! C'mon, it's not all that difficult! :-) > > Unless you are certain of your power requirements, then provide a > supply that can handle the worst case requirements. What *those* are > depend on the core [which also determines the number of DCMs] and > number of IO pins. > > 1.2V -> Core > 2.5V -> DCMs, JTAG chain > 3.3V -> IO > Aha, some science. Very good! ;-) > > I usually use a linear regulator for the DCM power. > If you're feeding the regulator straight from a battery or a mains/transformer type circuit, the linear regulator works fine. Toasty too! However, if the linear regulator's fed from a switcher, then I suggest filtering out the switching noise with a passive network instead. The control bandwidth of linear regulators is maybe 100kHz tops. A nice LC filter gets rid of crud over a much wider bandwidth. That's science, not art! :-) HTH, Syms.Article: 114721
On a sunny day (23 Jan 2007 13:11:20 GMT) it happened pbgbbrsh@ludd.invalid wrote in <45b60978$0$487$cc7c7865@news.luth.se>: >>> Now all you need is a Gerber-driven solder paste dot printer! They >>> exist, and news of an affordable unit for prototyping would be interesting. > >>Following up myself, the Essemtec CDS6700 solder paste printer seems to >>cost around $25,000. Not quite affordable ;-) > >Makes me wonder what it would cost to build x-y table and reuse a inkjet >cartridge ;) Maybe with a DVD inkjet printer (like Epson R200), should hold a Eurocard 100x160. DVD is 120mm wide, it is in a tray that slides through the printer, no length limit. Costs 80 Euro to try...Article: 114722
Well I read the wrong dimenson. It's still bl**dy small. But if want to be totally accurate, and not in any way to ignore the significance of the part, Altera do describe the Max-II as a CPLD so I guess the 8x8 CP132 packaged S3E might be the smallest packaged FPGA. John Adair Enterpoint Ltd. Antti wrote: > John Adair schrieb: > > > CP132 package 6.5x6.5 mm for S3E/S3 is already there. See it on our > > Craignell modules here > > http://www.enterpoint.co.uk/component_replacements/craignell.html. > > > > The only thing with 0.5mm ball grids is the pcb technology you need to > > use to achieve a design. Getting the alignment correct in assembly is > > also fun. > > > > As to S3AN it would be nice but may not be practical depending on the > > approach taken by Xilinx in implementing the loading mechanism. We will > > all have to wait until the marketeers are ready to show you more. > > > > John Adair > > Enterpoint Ltd. > > > > Antti wrote: > > > Austin Lesea schrieb: > > > > > > > Antti, > > > > > > > > No problem. We have to release our software on a regular schedule, so > > > > there is no holding it back. > > > > > > > > I would caution that whatever is revealed in the software may be updated > > > > or changed in the future, so the recommendation to work with our FAEs > > > > (if you really want to use a product before its release) is still valid. > > > > > > > > Austin > > > Huh. > > > tnx. > > > > > > I just pointed out to some info that is revealed by the WP 9.1, things > > > that are to my understanding command knowledge as of today. > > > > > > The fact that actual product release announce are not in sync with > > > software updates is a bit confusing. For me at least, but I guess that > > > explains why I failed so miserable on brainbench online examps for: > > > "SCM: Software Configuration Management". > > > > > > At the moment I can only say that S3AN looks like REALLY REALLY nice > > > FPGA! A real nice one. > > > And I can only whish that package options would include > > > VQ64 > > > DIP40 > > > QFN48 > > > ;) kidding. > > > but really, a package with outline 8by8 mm or less would be really > > > nice. > > > Altera is currently leading in this regard the MAX II has 0.5mm 100 > > > ball BGA with measueres 6by6mm ! > > > > > > thats a real dream package. > > > ok, I can little relax the specs, S3AN in 8bx8 mm microFPGA would be > > > close to a truedream as well. > > > > > > Antti > > John, > > please read > http://www.xilinx.com/bvdocs/packages/cp132.pdf > > or measure on your board CP132 is 8 by 8 > the smallest kinda FPGA is today MAXII in true 6 by 6 (outer > dimensions!) > > but, well CP132 is package too :) > AnttiArticle: 114723
Hi Using xilinx EDK we have implemented a PowerPC program reading data from a vhdl module that is connected through a PLB IPIF FIFO. Reading a single data element of 64bit from the FIFO takes 60 clockcycles. Reading 8 times in a row takes 672 clockcycles. All clockcycles are measured using Xtime and taking overhead into account. We find the number of clockcycles very high, expecting it to take only a couple of clockcycles to read an element from the fifo. Are we overestimating the speed of the plb ipif? best regards RuneArticle: 114724
Symon wrote: > Hi Pete, > Some comments in line:- > > "PeteS" <PeterSmith1954@googlemail.com> wrote in message > news:1169556506.624001.4310@l53g2000cwa.googlegroups.com... > > > > Choosing power supplies for parts is as much art as science, especially > > in the world of programmable logic where the load can vary due to > > upgraded / 'fixed' functionality. > > > Only if you're a rubbish scientist! C'mon, it's not all that difficult! :-) Snort - see my comment. The current requirements across the entire range of devices can vary by factors of 5 or more. Certainly one can simulate a board, but keep in mind that the FPGA on a real board is only a small part of the power system. I *do* add up the entire system, and then leave some overhead. For a straight FPGA, one is rather in the dark because there's very little guidance in the data sheets as to current consumption (quite reasonably, in a way, as it depends on internal switching) and then one has to be careful about current across the entire temperature range. So is it science? To the extent I can actually get solid numbers, yes. Beyond that, it's art ;) > > > > Unless you are certain of your power requirements, then provide a > > supply that can handle the worst case requirements. What *those* are > > depend on the core [which also determines the number of DCMs] and > > number of IO pins. > > > > 1.2V -> Core > > 2.5V -> DCMs, JTAG chain > > 3.3V -> IO > > > Aha, some science. Very good! ;-) > > > > I usually use a linear regulator for the DCM power. > > > If you're feeding the regulator straight from a battery or a > mains/transformer type circuit, the linear regulator works fine. Toasty too! The DCM supply is usually not a current hog, so for most situations a linear even from 5V is ok. I feed linear regulators all over the place from switchers, and only in the most sensitive caes (which *can* include the DCM if I have to ensure ultra low jitter) do I add extra filtering beyond normal bypassing and perhaps a series inductor. > However, if the linear regulator's fed from a switcher, then I suggest > filtering out the switching noise with a passive network instead. The > control bandwidth of linear regulators is maybe 100kHz tops. A nice LC > filter gets rid of crud over a much wider bandwidth. That's science, not > art! :-) > Science is about figuring out why existing things work. Engineering is the art of figuring out new things ;) Cheers PeteS > HTH, Syms.
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