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Hi Austin, Thank you for the heads up on bitstream encryption. I have one more concern about loading random garbage while looking closer at the bitstream format. I'm no electrical engineer, so this is purely from a software standpoint. It seems every "standard" pip is controlled by a bit pattern of two bits over (4+4) bits in the bitstream, with one bit chosen in the first set and another chosen in the second set. I'm just guessing that this one-hot encoding means that there's no mux for this connexion. Couldn't you get electrical contention just by ANDing two valid bit patterns, such as: (0,0,0,1, 1,0,0,0) and (1,0,0,0, 0,1,0,0) ? This would considerably raise the chances of electrical problems. Now I'm also left wondering why you aren't compressing the bitstream data by a factor of two by encoding the one-hot position in each set on only two bits (possibly "uncompressing" the bitstream on the fly to internal SRAM, but therefore disallowing invalid patterns from being loaded ?). But I guess that's another problem entirely. JBArticle: 114776
Hi Brian, On the XESS website you can find a very good description how to use Xilinx's tools with makefiles. This is a direct link: http://www.xess.com/appnotes/makefile.html I found this description very helpful to build my own scripts. Since one year I use makefiles for most of my projects and I don't have all these problems related to the ISE GUI. HTH MichalArticle: 114777
Daniel O'Connor <darius@dons.net.au> writes: > Martin Thompson wrote: >> If by ISE we mean the GUI (as I think we do) then I disagree... >> >> The best development environment I have ever used for Xilinx devices >> is Emacs (with vhdl-mode) and a command-line build script :-) > > A man after my own heart.. > :-) U get strange looks from people when they see me avoiding the mouse! >> I had problems with ISE crashing when reading files of network drives, >> which is what drove me to build scripts, but I'd not go back now! > > Do you mind sharing your scripts? I have some makefiles I leeched off > someone them hacked up, however I still haven't worked out simulation > properly.. > Simulation I use vhdl-mode for, it scans my entire set of files and builds me a complete makefile. Anyone who hasn't spent 2 or 3 weeks attempting to get up the learning curve of emacs/vhdl-mode has missed out IMHO. Two of my colleagues (who are distinctly mouse and windows types) are converted to Emacs for vhdl writing (purely down to the power of vhdl-mode). I used to use Codewright, which I thought was pretty hot, but it's not a patch on emacs, especially for VHDL. The rest of my scripts are simple bat files in windows, I just make a "working directory", copy in the EDF, UCF and any other NGD files I might need, then run NGCbuild, map, par etc. I have a few other bits ont he end for our internal use which generate a C-file with the bitstream as an array, and embed the time of compile into the UserID register. Hope that helps! Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 114778
"bgshea" <bgshea@gmail.com> writes: <snip> > So, I ask Martin, as he posted a method of using build scripts, if you > could even if in part, post some of what you use, that might benefit > the community here. I would certainly build on those scripts and post > them back. I've posted some details upthread somewhere, I don't think my employer would like me to post the raw scripts I'm afraid. I have this makefile from my home linux system, which I have used in the past also... It's not as well tested, but it met my needs at the time. You'll notice this was from when I was playing with myhdl... It has targets for stopping at various points along the compile, as well as a PROG target which creates an impact script and then runs it. So all I have to do when I've hacked my code is "make prog" and then go and make a cuppa (my aging dual-celeron box takes a while!) Hope this helps someone! Cheers, Martin ##### Makefile starts here TOP=osc SOURCES=osc.py dco.py .PHONY: myhdl .PHONY: bits .PHONY: synth .PHONY: sim .PHONY: clean .PHONY: prog prog: work/$(TOP).bit @echo "setPreference -pref StartupCLock:AUTO_CORRECTION" > work/impact.cmd @echo "setMode -bs" >> work/impact.cmd @echo "setCable -port auto" >> work/impact.cmd @echo "Identify" >> work/impact.cmd @echo "setAttribute -position 1 -attr configFileName -value $(TOP).bit" >> work/impact.cmd @echo "Program -p 1 " >> work/impact.cmd @echo "quit" >> work/impact.cmd cd work && impact -batch impact.cmd sim: work/$(TOP).v iverilog -v tb.v && vvp -v a.out +lxt cat work/$(TOP)_sim.results bits:work/$(TOP).bit work/$(TOP).bit:work/$(TOP).ncd cd work && xflow -config bitgen.opt -p xc3s200-ft256-4 $(TOP).ncd | tee logfile_par.log par: work/$(TOP).ncd work/$(TOP).ncd: work/$(TOP).ngc $(TOP).ucf cp $(TOP).ucf work/ cd work && xflow -implement fast_runtime -p xc3s200-ft256-4 $(TOP).ngc | tee logfile_par.log synth:work/$(TOP).ngc work/$(TOP).ngc: work/$(TOP).v cp $(TOP).ucf work/ chmod u+w work/$(TOP).ucf cp xst_verilog.opt work/ chmod u+w xst_verilog.opt cd work && xflow -synth xst_verilog -p xc3s200-ft256-4 $(TOP).v | tee logfile_syn.log clean: rm -rf work/* work/$(TOP).v: $(SOURCES) @echo MyHDL Verilogging $< python2.4 $< mv $(@F) work ############ Makefile ends here ####### -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 114779
Sean Durkin <news_jan07@durkin.de> writes: > I think the main problem is that Xilinx releases new ISE versions in a > predefined schedule, as Austin mentioned in Antti's thread about > non-volatile Xilinx-FPGAs. A new ISE release comes out regularly, not > when it's done. But on the other hand, it doesn't make sense to release > a new version, when there's nothing new in it. The marketing department > has to brag about it being another 30% faster than the previous release, > having gazillions of new features, and so on. I don't suppose they'd want to advertise 30% less bugs would they? Even though most engineers would rather see it :-) Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 114780
Hello friends, I Have just started going through ethernet.my doubt is what is the main functionality of Ethernet MAC??? In switch controller implementation on FPGA does 4 tranceivers require 4 Ethernet MAC's???if so why??Because the source and the destination systems will have ethernet controller and MAC built in???please answer these questions.It's haunting me. Thanks. Regards, Hema.Article: 114781
Hello friends, I Have just started going through ethernet.my doubt is what is the main functionality of Ethernet MAC??? In switch controller implementation on FPGA does 4 tranceivers require 4 Ethernet MAC's???if so why??Because the source and the destination systems will have ethernet controller and MAC built in???please answer these questions.It's haunting me. Thanks. Regards, Hema.Article: 114782
Ben Jackson <ben@ben.com> wrote: >On 2007-01-23, stephen.craven@gmail.com <stephen.craven@gmail.com> wrote: >> Does anyone know if it is possible to permanently harm a Xilinx FPGA >> internally through a bad (accidental or malicious) bitstream? >One totally unobvious one is: >http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=22471 >Running without an MGT hooked up for 400 hours might cause it to permanently >fail! What's MGT?Article: 114783
On a sunny day (23 Jan 2007 20:47:59 GMT) it happened pbFJKD@ludd.invalid wrote in <45b6747f$0$486$cc7c7865@news.luth.se>: >>>>> Now all you need is a Gerber-driven solder paste dot printer! They >>>>> exist, and news of an affordable unit for prototyping would be interesting. >>> >>>>Following up myself, the Essemtec CDS6700 solder paste printer seems to >>>>cost around $25,000. Not quite affordable ;-) >>> >>>Makes me wonder what it would cost to build x-y table and reuse a inkjet >>>cartridge ;) > >>Maybe with a DVD inkjet printer (like Epson R200), should hold a Eurocard 100x160. >>DVD is 120mm wide, it is in a tray that slides through the printer, no length limit. >>Costs 80 Euro to try... > >Do you think the solderpaste would get through the ink channels ..? >Maybe it's viscosity is too high. Yes that may be a big problem. Maybe something could be done to make the paste more suitable.Article: 114784
Martin Thompson wrote: > I don't suppose they'd want to advertise 30% less bugs would they? > Even though most engineers would rather see it :-) Exactly. But that's a common problem in all of the industry nowadays. Look at digital cameras. They advertise more and more megapixels, but noone ever says something like "30% less image noise than the previous model". So you get more and more pixels, but the actual image quality (which in my thinking should be the deciding factor) deteriorates from generation to generation. Same with TV: HDTV is all the hype, but what does a higher resolution help if you use a crappy lossy video compression codec for transmission and a display that doesn't have a decent deinterlacing circuit and smears motions over 50 frames? Advertising improved quality somehow implies that you didn't do a good job before, so all the hype is about things that weren't there before, not things (like bugs) that were removed. That's what marketing thinks, at least. But I believe most engineers think differently. I guess most of us would be happy to have less features, but being sure they all work all right. And I'm talking here about the products we design as well as the products we use. cu, Sean -- My email address is only valid until the end of the month. Go figure what the address is going to be after that...Article: 114785
Hi Rob, Yes the bram are dual port but that's not the issue here. In your scheme, I'll be overwriting some data of the previous line before I reread them ... Look at the content of block a. I'll need 1 full line time to reread it but I'll fill it with new data in only half line time ... Sylvain On Jan 23, 4:20 am, "Rob" <robns...@frontiernet.net> wrote: > Sylvain > > I'm not familiar with Xilinx's memory architecture; but if their memory blocks have the option of being run in dual-port mode it could make this problem much easier to deal with. > > In the past I've taken advantage of other mfg's mixed-port read-during-write mode. This mode is used when a RAM has one port reading and the other port writing to the same address location with the same clock. The memory block outputs the old data at the specified address when there is a simultaneous read during write to the same port. You then could set up two blocks (one for each half of the image) a line deep. > > First fill the memory blocks with line 1 > > fill block a > > *reset wraddr_a back to addr 0 and wait for block b to fill > > fill block b > > reset wraddr_b back to addr 0 > > now you read through the two blocks simultaneously while writing to the same address for block_a > > reset wraddr_b back to addr 0 > > repeat * > > You'll have two pointers for each memory block, one read and one write pointer. > > I haven't done any work with DVI so I may be missing something specific to that interface. If so, my apologies. > > Take care, > > Rob > > "Sylvain Munaut <Some...@SomeDomain.com>" <246...@gmail.com> wrote in messagenews:1169454808.249472.167130@a75g2000cwd.googlegroups.com... > > > Here's my problem : > > > A have a video module (that I can't really change), that outputs a > > 3840x2400 image, by outputing two consecutive pixels at once (like > > dual-link DVI). The problem is that the screen to display that doesn't > > want dual-link DVI, it wants two independant DVI stream, one for the > > left part of the screen and another for the right part of the screen. > > (two "stripes" of 1920x2400). > > > I'm trying to come up with a solution to "transform" one into another, > > without using a frame buffer nor storing more than 1 line of video. > > (At 3840, in color, that already is 6 Xilinx BRAMs and I'm a little > > short of those ...). > > > According to my calculations, It should even be possible to only store > > half a line, but I prefer to have a 1 line delay than half a line > > delay. > > My problem is that I can't find how to do it ... Storing in BRAM has > > proven to be an addressing nightmare to store and reread simultaneously > > without overwriting data I haven't re-read yet ... (since I don't read > > in the same order that I write). > > > Does anyone has done something similar or has a genius idea ? Because > > I'm missing something here, that should be simple and I just don't see > > it ... > > > SylvainArticle: 114786
Hi John, Yes this addressing scheme works, and I actually though of that (well, didn't formalize it that much, I just did the firstfew steps on paper). But since I hit a problem since I must write two pixel in parallel and the location of those pixel changes, I couldn't use simple a twice as large BRAM. But ... now that I think of it, since I read and write at the same location, I can use the same port to do both. Then use the second port to work on the second pixel. Then, putting 3x2 BRAM in parallel in 4096x4 mode gives me my storage space for 4096 pixels x 3 x 8b. Great ! Thanks a lot, now I don't even have to figure the math by myself, I just have to type it in VHDL ;)Article: 114787
Hi. I want to install uClinux on a Spartan 3 XC3S1000. Now I need auto-config.in file to compile uClinux distro! But...How to generate this file "auto-config.in"? What I need? I'm using EDK 8.1i sp2 on Windows XP. ThanksArticle: 114788
Hello, does anyone of you use this configuration (see subject) to run Chipscope Pro and with a Virtex4 development board? In my case, Windows does not even show there correct device name in the "device manager". Reinstalling of Chipscope Pro also didn=B4t help. Bye HelmutArticle: 114789
Do I use not gates to make a small clock delay, for example
module my_module (osc,a,b,c);
input osc;
output a,b,c;
reg a, b, c;
always @ (osc)
begin
a = osc;
b = a;
c = b;
end
Will this give me delayed clocks?
Article: 114790<anesserm> wrote in message news:45b7452f$1_3@mk-nntp-2.news.uk.tiscali.com... > Do I use not gates to make a small clock delay, for example > > module my_module (osc,a,b,c); > input osc; > output a,b,c; > reg a, b, c; > always @ (osc) > begin > a = osc; > b = a; > c = b; > end > > Will this give me delayed clocks? > Only if you disable logic optomizations in your synthesis tool....which in most cases is generally 'not' what you want to do. PLL (Altera), DCM (Xilinx) or re-examining the design as to why you think you need a delayed clock is a better approach. Kevin JenningsArticle: 114791
Hello Helmut, I've faced such a problem - xilinx has changed the device driver on the new usb program devices. if you are using a new usb program device (the one that is connected to the jtag) and your ise ver is older than 8.2 you would probably face this problem. so either update the ISE version or download the cable's driver from xilinx web. regards, Guy Helmut wrote: > Hello, > > does anyone of you use this configuration (see subject) to run > Chipscope Pro and with a Virtex4 development board? > > In my case, Windows does not even show there correct device name in the > "device manager". > Reinstalling of Chipscope Pro also didn=B4t help. >=20 > Bye HelmutArticle: 114792
In my university project i had a little touch with ethernet mac. can you rephrase your question?... i didn't understand the problem.. perhaps i could help.. Guy hema wrote: > Hello friends, > > I Have just started going through ethernet.my doubt is what is the main functionality of Ethernet MAC??? In switch controller implementation on FPGA does 4 tranceivers require 4 Ethernet MAC's???if so why??Because the source and the destination systems will have ethernet controller and MAC built in???please answer these questions.It's haunting me. > > Thanks. Regards, Hema.Article: 114793
In comp.arch.fpga wallge <wallge@gmail.com> wrote: >I am the main hardware designer for the company I work for. I inherited >a lot of old, badly written, poorly documented >VHDL designs and vendor tool project files. Over the course of the time >that I have worked here, I have been trying to take care to go back and >document things and better organize them, to make them easier to use >and reuse, along with trying to write well-documented, reusable new >code. >I don't have any training as a software engineer or code "maintainer" >(I'm an EE). I was wondering if there was a good >resource out there (maybe a website or book on amazon) that would clue >me into some good code writing and maintenance strategies that I >wouldn't have learned in school. I know that there are a lot of >software engineering resources available, but it would be nice if there >was something more specific to hardware design (HDL Code) reuse and >maintenance. Use a good version control system. (Test it before accepting it. Make sure all relevant systems can handle it) Use one source code management system if possible. Decide on benefit/cost on clearing up various sources. (Could start with just describing what it does in general)Article: 114794
A switch receive, store and then re-send the packet. (Well, in a store and forward architecture ... it could resen don the fly some packet but that's beside the point). So essentially it has a "network card" at each of it's port and therefore requires a MAC, that will talk to the PHY and ensure the "on-wire" protocol is respected, check checksum, interpacket gap, send pause frames, ... As a switch needs some "intelligence" to do it's job, it needs this. You can probably use simplified MAC in some aspect but that stills statys a MAC ... (Medium Access Controller -> control what's going on on the wire). Sylvain On Jan 24, 10:35 am, hema <ashu_19_1...@yahoo.com> wrote: > Hello friends, > > I Have just started going through ethernet.my doubt is what is the main functionality of Ethernet MAC??? In switch controller implementation on FPGA does 4 tranceivers require 4 Ethernet MAC's???if so why??Because the source and the destination systems will have ethernet controller and MAC built in???please answer these questions.It's haunting me. > > Thanks. Regards, Hema.Article: 114795
Sean Durkin <news_jan07@durkin.de> wrote: > Advertising improved quality somehow implies that you didn't do a good > job before, so all the hype is about things that weren't there before, > not things (like bugs) that were removed. > That's what marketing thinks, at least. I think the mentality is that you need new features to get new customers. Fixing old issues keeps old customers happy, but that's not good for growth. -aArticle: 114796
John McCaskill posted on 23 Jan 2007 09:51:58 -0800: "Take a look at the "Reuse Methodology Manual" by Keating and Bricaud." I have read only a tiny proportion of this book. Which parts could actually teach someone something useful, if the reader does not already understand the importance of the points (e.g. I do not think that I would count "Use Functions" and "Use Loops and Arrays" from Chapter 5 as being in this category)? Regards, Colin Paul GlosterArticle: 114797
> Only if you disable logic optomizations in your synthesis tool....which in > most cases is generally 'not' what you want to do. PLL (Altera), DCM > (Xilinx) or re-examining the design as to why you think you need a delayed > clock is a better approach. Is there a way to fool the optimizer? > > Kevin Jennings > >Article: 114798
Hello Guy, thanx a lot for your fast answer. I already use ISE 8.2i Sp2 and ChipScopePro 8.2i. For Win2k and WinXp you don=B4t have to install any additional drivers. The "Online Configuration Problem Solver" gave this answer: Not all Operating Systems are supported by the Xilinx cables, although the iMPACT software may run on the system. If a custom operating system is being used and compiling the cable drivers are not working a supported operating system may be required. This can be done by dual-booting the workstation or by using emulation software. And i got a link to http://www.jungo.com This company provides the driver for the Platform Cable USB. But I also couldn=B4t figure out, how there website could help me. There is no hint, that Win2k3 is not supported. But nothing says it will run either! Did you switch to a XP machine like plan to do if all else fails?Article: 114799
On 24 Jan., 10:52, pbF...@ludd.invalid wrote: > What's MGT? You mean besides "Milingimbi airport, Australia"? Kolja Sulimma
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