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idp2 wrote: > That is only one of my always blocks that works with cal_ram_di. I > have two others but they are based ont the conditions if(~done > &stepCnt==1) and if(~done & stepCnt ==2)...is that what is causing the > problem?? Probably. The synthesis tool probably found an occassion where two or more if-conditions are possible met at the same time, hence the signal is assigned in two different places, and the tool doesn't know which of the assigments is to be carried out. > If so how do I fix that? As a general rule: Each signal should only be assigned in one single always-block, or process-construct in VHDL, not in several, or you almost always run into the kind of problem you're having now. You need to have ONE block of instructions that covers the assignment of "cal_ram_di" for all possible cases, and "cal_ram_di" should only be read in other always-blocks, never be assigned. Maybe a little insight into synthesis tools might help here. What a synthesis tool does (after checking the syntax and so on) is search your code for certain templates. These templates you can find in the ISE-documentation. For example, if the tool finds something like counter <= counter + 1 it recognizes this as a counter (it "infers" a counter), determines the bit width and then picks a more or less predefined schematic for a x-bit-upward-counter out of a library that comes with the tool. That is a schematic of interconnected gates or whatever that in combination make up a counter. Just like there are templates for counters, there are templates for things such as state machines, multiplexers, multipliers and so on. If you look at the synthesis report, you can see a table of all the things the tool found in your code. Another important template is the one for flip-flops and registers. Basically, every signal that is assigned inside a clocked process in VHDL or a always @(posedge clk)-block in Verilog infers a flip-flop (if it's a single-bit-signal) or a set of flip-flops called register (if it's several bits wide). The code snippet you posted basically (don't really know Verilog) looks to me like a register with an enable, i.e. the register transfers the input value to the output if (~done & stepCnt == 0) AND (cal_cnt == 0). The output of the register is called "cal_ram_di". What you probably did is create several registers with different enable signals (one is enabled when ~done & stepCnt == 1, one when ~done & stepCnt == 2 and so on), and all of their outputs are assigned to the same signal "cal_ram_di". Now what happens if in two different always-blocks different values are assigned to "cal_ram_di"? Which should it really use? That's the problem you're having. So, to sum it up: 1. Assignments for ONE signal should only happen in ONE place (ONE always-block, process, whatever) 2. Have a look at the synthesis report, see what ISE finds in your code, and try to make sense of it. 3. Have a look at the RTL-schematic ISE produces to get a feeling what the hardware you get in the end looks like. You might start with some simple circuits, just to see what combinations of flip-flops, gates and so on gets synthesized when you write your code this way or the other. Hope that helps, SeanArticle: 113976
Look at http://direct.xilinx.com/bvdocs/publications/ds064.pdf pin-outs on page 6 Peter Alfke On Dec 31, 10:18 am, <highZ> wrote: > Hello, there are some pins on xilinx xc9536 which are called global > clock1/2/3 > global reset, etc, where are these explained?Article: 113977
On Sun, 31 Dec 2006 23:14:29 +0100, Sean Durkin <news_jan07@durkin.de> wrote: >idp2 wrote: >> That is only one of my always blocks that works with cal_ram_di. I >> have two others but they are based ont the conditions if(~done >> &stepCnt==1) and if(~done & stepCnt ==2)...is that what is causing the >> problem?? >Probably. The synthesis tool probably found an occassion where two or >more if-conditions are possible met at the same time, hence the signal >is assigned in two different places, and the tool doesn't know which of >the assigments is to be carried out. If only synthesis tools were that smart. Independent of the condition the register is assigned, you will get this error if two always blocks assign a register. Just don't do it. One solution is to move all the assignment into a combinational always block ie one which generates the D input of the flops to be assigned. Then you can add multiple independent if conditions more easily and assign the d input to the register in a clocked always block. ie always @(*) begin if (some condition) cal_ram_di_d = first; if (some other condition) cal_ram_di_d = second; end always @(posedge clk) cal_ram_di <= cal_ram_di_d;Article: 113978
hi,
Can anyone tell me how to repair the xilinx download cable?
I have ever bought two USB cables from xilinx, they have been running
well. But one day, when I plug the JTAG flyers in/out my evaluation board,
it can not be recognized by the computer any more. The power led still be
green, which indicate the power is on, but the software can not connect the
cable. I suppose I have damaged the cable because of power on-line plugin.
The board is Okay, because it can still be download and debug by other
cables.
Email: sunlei@bit.edu.cn
Article: 113979> Look at > http://direct.xilinx.com/bvdocs/publications/ds064.pdf > pin-outs on page 6 This is true, page 6 shows which pins are which. But what I was asking is different -- what is the reason for these pins, when do we use them, what do they do? For example, I can connect an oscillator to any IO pin, which can then be used in statements like always @ (posedge input-pin) > Peter AlfkeArticle: 113980
My rule is: Use the smallest possible number of different clock signals (one is best) and use the tight global clock distribution to avoid hold-time issues altogether, and also to achieve highest performance. And, last not least, simplify the debugging process. The problems you will encounter and the time to resolve them, are both proportional to the number of different clocks you are using. But maybe it's a third-power relationship ;-) Peter Alfke On Jan 1, 1:27 pm, <highZ> wrote: > > Look at > >http://direct.xilinx.com/bvdocs/publications/ds064.pdf > > pin-outs on page 6This is true, page 6 shows which pins are which. But what I was > asking is different -- what is the reason for these pins, when do > we use them, what do they do? > > For example, I can connect an oscillator to any IO pin, which > can then be used in statements like > > always @ (posedge input-pin) > > > Peter AlfkeArticle: 113981
Hi all, I want to load my PPC program in an external SRAM connected to the PLB bus on the PPC. But I fail to find any suitable IP with in EDK. For now I have bypassed the PPC and use a mux which either lets the PPC control the SRAM or the FPGA fabric. Since the program gets loaded at start up the PPC is hold in reset until the program is loaded. However, I would like to have a general PLB master function which can access the PPC address space from the FPGA fabric. Does such an IP exist or am I missing something about EDK IPs which makes this possible? Cheers, /RickArticle: 113982
On 2007-01-01, Rick North <dontreplytothisaddy@hotmail.com> wrote: > > However, I would like to have a general PLB master function which can > access the PPC address space from the FPGA fabric. Knowing Xilinx, this is called "plb_ipif". Mind you, I haven't even looked, but if they had what you want, that's what they'd call it! I bet the "Create Peripheral" wizard (under the Hardware menu of XPS) will even connect it for you. -- Ben Jackson AD7GD <ben@ben.com> http://www.ben.com/Article: 113983
H-Z, Dedicated pins are used to offer some benefit that would not be available from a general purpose pin. For example, a clock should have less delay than any other signal, or else you would need to worry that the clock might arrive after the data. Thus dedicated clock pins have lower skew than other pins. By using the dedicated clocks, the internal routing is never an issue. If you used some other general purpose resource for a clock, then setup and hold times must be met everywhere that signal might go and get used. A reset pin might have additional logic on it, to prevent glitching if a clock occurs simultaneous with the reset. It is all in the data sheets, and user's guides: really. AustinArticle: 113984
> Dedicated pins are used to offer some benefit that would not be > available from a general purpose pin. For example, a clock should have > less delay than any other signal, or else you would need to worry that > the clock might arrive after the data. Thus dedicated clock pins have > lower skew than other pins. By using the dedicated clocks, the internal > routing is never an issue. If you used some other general purpose > resource for a clock, then setup and hold times must be met everywhere > that signal might go and get used. > > A reset pin might have additional logic on it, to prevent glitching if a > clock occurs simultaneous with the reset. > > It is all in the data sheets, and user's guides: really. Which one, there are many datasheets for the 9500 familiy and for each specific one. I had a glance at all of them and couldn't see all these things. What exactly does 'reset' do in the first place, well I will see again if I can find it. Thanks > > AustinArticle: 113985
Does anyone know what is needed to work with surface mount ic's, what sort of starting price tag are we talking about? (Assuming I have ready made boards, i.e. only the soldering phase is required)Article: 113986
Vitaliy, There was a paper presented at MAPLD bridging Matlab using the library David talked about. The abstract of the paper is posted at: http://www.klabs.org/mapld06/abstracts/225_hoy_a.html I expected to see the paper there too, but did not see it. You can contact the conference organizer and see if or when it will be available. Cheers, Jim Lewis VHDL Evangelist > Vitaliy wrote: >> Hello, >> >> I have seen this question many times in the newsgroups but I did not >> see a clear answer. >> I have to perform various operations on arrays of data (such as >> multiplication, addition, finding mean, etc.). I have code written in >> Matlab and would like to translate it to vhdl. I understand that such >> subroutines as imagesc, imwrite, etc. might not be possible to >> translate to vhdl and will need to be written (or similar functions >> might be already implemented in vhdl). Is there anyway of directly >> translating Matlab code directly to vhdl? Can this be done using >> Simulink (Xilinx System Generator)? I don't have System Generator at >> home and Xilinx doesn't seem to have evaluation version (asking for >> Product Serial Number). Or maybe my question should be: can this be >> done in Simulink to start with? >> I have Xilinx FPGA/ISE. And if this can not be done using System >> Generator, is there anything else that can be used? >> >> Please let me know if my requirements are not very clear. > > At the moment there is no such thing. There are several Simulink based > tools out there which help you get to hardware. You have to pay for > these though, and you will really have no "golden" code if you go this > route. > > I have written VHDL packages: > http://www.vhdl.org/vhdl-200x/vhdl-200x-ft/packages/files.html > Which follows the rules in Matlab, so creating this program should be > possible.Article: 113987
On 2007-01-02, <highZ> <> wrote: >> It is all in the data sheets, and user's guides: really. > > Which one, there are many datasheets for the 9500 familiy and > for each specific one. I had a glance at all of them and couldn't > see all these things. What exactly does 'reset' do in the first > place, well I will see again if I can find it. Thanks If you're really so unwilling to read the datasheets, you are doomed. -- Ben Jackson AD7GD <ben@ben.com> http://www.ben.com/Article: 113988
smount wrote: > Does anyone know what is needed to work with surface mount > ic's, what sort of starting price tag are we talking about? > (Assuming I have ready made boards, i.e. only the soldering > phase is required) > > How long's your piece of string? Specifically, what type of SMT package are you using? If SOIC, PLCC etc., you can do it with just a fine-tip soldering iron. Poeple have reported doing BGA's in a toaster, but I haven't tried it myself. Is this a one-off hobbyest situation, or volume production?Article: 113989
John Retta wrote: > To discover the unconstrained paths in a design, run trce with the -u > option. > > Regarding the original posting, as well as the followup "design runs > with chipscope, but fails to run without", there are lots of specific > causes for this, all falling into the category of unconstrained, or > misconstrained > path. > > Debugging obscure timing problems is a lot like debugging obscure logic > problems. The secret is to add test circuitry that helps isolate the > problem > area. Once isolated, problem and solution eventually will surface. > > The statement that the design is marginal was a correct one. I think > by adding chipscope, it pushed the design from margininally not working > to marginally working. Unfortunately, temp, voltage and process variation > will ensure that some units will wind up working only intermittantly. > > I would start out looking at -u option report. That will tell if there are > really unconstrained paths in design. Then look at any asynchronous > interfaces, clk domain crossings, etc. These are the big culprits in > route specific marginal operation. > Thanks for your comments. There are a few clk domain crossings in the design, though all clocks are derived from the same input clk. There are also some asynchronous interfaces and over the next few days I will look through all of these. Thanks John and Phil for the -u option. I wasn't aware of that previously. Happy New Year to all of you! /JohanArticle: 113990
On Tue, 02 Jan 2007 00:47:14 -0800, David R Brooks <davebXXX@iinet.net.au> wrote: >Is this a one-off hobbyest situation, or volume production? Ooh, you've lit the touch-paper on one of my hobby-horses (and mixed metaphors, but hey, it's the New Year): hobby, hobbyer, hobbyest: progressively increasing levels of similarity to a hob :-) hobbyist: someone who indulges in a hobby But David is right: PQFP/PLCC/SOIC can be done with a soldering iron ***and some good-quality liquid or, better, gel flux***. BGA is definitely beyond my hobby skills, but I too have seen reports of people using domestic toasting-ovens - note another linguistic barrier here: in the UK, a "toaster" is likely to be something that has slots to accept bread in a vertical plane, which is unlikely to be helpful for soldering BGA devices on to a board! Even if you could assemble BGA at home, you would then have to worry about inspection or test. As far as I'm aware, JTAG testing software is still not widely used by amateurs, and X-ray inspection tools are even rarer. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 113991
highZ wrote: > > Dedicated pins are used to offer some benefit that would not be > > available from a general purpose pin. For example, a clock should have > > less delay than any other signal, or else you would need to worry that > > the clock might arrive after the data. Thus dedicated clock pins have > > lower skew than other pins. By using the dedicated clocks, the internal > > routing is never an issue. If you used some other general purpose > > resource for a clock, then setup and hold times must be met everywhere > > that signal might go and get used. > > > > A reset pin might have additional logic on it, to prevent glitching if a > > clock occurs simultaneous with the reset. > > > > It is all in the data sheets, and user's guides: really. > > Which one, there are many datasheets for the 9500 familiy and > for each specific one. I had a glance at all of them and couldn't > see all these things. What exactly does 'reset' do in the first > place, well I will see again if I can find it. Thanks I probably spend up to 1/2 my working life (and some of my supposedly non-working life) , perhaps more, reading datasheets to understand and effectively use devices. For this particular part and issue (I use the XC9536XL in 3 designs and I avail myself of the GCLKs for various reasons) all is indeed explained in the following places: 1. The family datasheet (XC9500 series) has the overview and timings, which can vary with package. 2. The device datasheet (XC9536) 3. The various application notes available on the Xilinx site. If you wish to do this stuff successfully, you have to be willing to absorb an inordinate amount of data from datasheets. If you don't wish to do the work of looking, reading and *understanding*, then our help would be futile anyway. Cheers PeteS > > > > > AustinArticle: 113992
On 2007-01-01, SunLei <iamsunlei@gmail.com> wrote: > hi, > > Can anyone tell me how to repair the xilinx download cable? > > I have ever bought two USB cables from xilinx, they have been running > well. But one day, when I plug the JTAG flyers in/out my evaluation board, > it can not be recognized by the computer any more. The power led still be > green, which indicate the power is on, but the software can not connect the > cable. I suppose I have damaged the cable because of power on-line plugin. The power led is actually controlled by the software in the FX2 microcontroller in the USB cable. So the microcontroller is probably at least partially working. You might have some luck if you try to force an update of the CPLD inside the USB cable. You can find out how to do this by looking at the following URL: http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&sGlobalNavPick=&sSecondaryNavPick=&getPagePath=20429 /AndreasArticle: 113993
<smount> wrote in message news:4599cdbe$1_4@mk-nntp-2.news.uk.tiscali.com... > Does anyone know what is needed to work with surface mount > ic's, what sort of starting price tag are we talking about? > (Assuming I have ready made boards, i.e. only the soldering > phase is required) > Hi, Try this Google search:- solder group:comp.arch.fpga author:freidin Philip gives a list of links you'll find interesting. HTH, Syms. p.s. On the subject of US vs. UK toasting techniques, IMO the problem in the US is not the toaster machines, it's the post-toasting technology. The toast just gets piled up on a plate. The US seems to be a veritable toast rack desert, so the toast always ends up soggy. I guess that's why it's IHOP and not IHOT! :-)Article: 113994
Jonathan Bromley wrote: > On Tue, 02 Jan 2007 00:47:14 -0800, David R Brooks > <davebXXX@iinet.net.au> wrote: > > >Is this a one-off hobbyest situation, or volume production? > > Ooh, you've lit the touch-paper on one of my hobby-horses > (and mixed metaphors, but hey, it's the New Year): > > hobby, hobbyer, hobbyest: > progressively increasing levels of similarity to a hob :-) > > hobbyist: > someone who indulges in a hobby > > But David is right: PQFP/PLCC/SOIC can be done with > a soldering iron ***and some good-quality liquid or, > better, gel flux***. BGA is definitely beyond my > hobby skills, but I too have seen reports of people > using domestic toasting-ovens - note another linguistic > barrier here: in the UK, a "toaster" is likely to be > something that has slots to accept bread in a vertical > plane, which is unlikely to be helpful for soldering > BGA devices on to a board! > > Even if you could assemble BGA at home, you would > then have to worry about inspection or test. As far > as I'm aware, JTAG testing software is still not widely > used by amateurs, and X-ray inspection tools are > even rarer. > -- > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > jonathan.bromley@MYCOMPANY.com > http://www.MYCOMPANY.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated. In addition to what others have said, a really nice soldering station can set you back a bit, but if you're doing small SM resistors/caps etc., then *two* fine pitch irons will ease your pain a lot. Most of the high end stations have multiple irons from a single controller including tweezer irons for such things, but it's usually beyond the needs or price range for a hobbyist. If you're getting older (as I most certainly am), then a magnifier with light (at least) will be welcome boon - it would probably be welcome anyway :) Cheers PeteSArticle: 113995
Hello I've started working on Xilinx Virtex II PRo FPGA kit for a project. Is there a way to configure bitstreams or netlists programmatically using C (i'm not looking at JBits!) so that i can configure the LUTs,IOBs according to my circuit needs? I also need to invoke iMPACT several times in my code to evaluate the fitness of my circuit. Will OLE automation be a solution to this problem? Any other alternatives or suggestions please! Regards quadruplesArticle: 113996
cpope wrote: > Try a USB dock like: > http://www.tigerdirect.com/applications/SearchTools/item-details.asp?EdpNo=1597389&CatId=604 > > -Clark It does *not* work for me using parallel cable IV with Impact. Cheers, GuenterArticle: 113997
Hi all I'm having trouble finding pcb layout recomendations on the altera and xilinx web sites for lead free bga's. I'm wanting to use an altera F256 package and I can find all I need for the leaded version but nothing for the rohs packages. Does anyone know where I should be looking or what changes to the leaded footprints I should make? all the best in 07 ColinArticle: 113998
Addressed to the XILINX insiders: I have made me myself a small pcb which is basically a replica of the simple Xilinx JTAG download cable. This JTAG interface works well with Xilinx CPLDs and also with Altera FPGAs and CPLDs (after some pin mapping on the printer port side, of course, making it look like a Byteblaster cable to the Altera tools). However, if I try to program a Spartan XC3S400 on a board coming from http://www.siphec.com the JTAG id is read wrong and programming fails. After some experiments and talking to the developers at Siphec it turned out that a resistor in the order of 560 Ohms to ground on the TCK line will solve the problem. At the first glance one might think that this resistor works as kind of cable termination reducing reflections on the clock line. The strange thing is: The positive effect of the resistor takes place ONLY if the resistor is mounted close to the 74HC125, i.e. BEFORE the JTAG cable connection to the aimed board. If the resistor is soldered to the aimed board near the fpga(where it could work as a termination) programming will fail as well. This all looks very mysterious to me! Is there some special TCK conditioning necessary for the Spartans that I am not aware of and that lets them behave different to other fpgas/cplds ?? TIA for your help Ulrich BangertArticle: 113999
As I said, I did look, but coudn't find > If you don't wish to do the work of looking, reading and > *understanding*, then our help would be futile anyway. > > Cheers > > PeteS
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Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z