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Thomas - You have no timing constraints in your .ucf file. At a minimum, you should put in period constraints for your clocks. RR thomas.neitzel@gmail.com wrote: > Greetings to all ! > > I started programming with VHDL two months ago. Now I want to > implement a project on a Spartan 3 (XC3S50 VQ100). The software I´m > using is the ISE Webpack 8.2.03i (Application Version: I.34). > This project is later supposed to be a bit error testing instance in > combination with an Microcontroller that is used to read out an > compare the sended and received data from the block RAMs of the > Spartan 3. I tested the components I used as standalone-designs and > they all seem to function but when I try to make one pice of all > designs the FPGA doesn´t show any expected behaviour at all-even some > simple LED I integrated in the design to indicate if the clock is > active don't start flashing. > > Although i know it's probably not the smartest way to ask for help but > as I need this project to function for my thesis i have no other ideas > than posting the whole code - any words are very appreciated (the > comments are in german and not so important)!!! > > p.s.: It would also help if someone would just copy and paste this > code into a new projektfile to find out if it´s running(simplest > indication: the State LED_Z0 should be on and the LED_Z1 should be > flashing) on his hardware. > > #UCF - File : > ********************************************************************** > ****************************** > > NET "CLK_IN" LOC = "P36" | IOSTANDARD = LVTTL ; #Takt vom > Meltemi-Board (66 MHz) > > NET "CLK_fromMC" LOC = "P39" | IOSTANDARD = LVTTL ;#Takt com MC > NET "DATA_toMC<0>" LOC = "P30" | IOSTANDARD = LVTTL > ;#Datenleitungen > NET "DATA_toMC<1>" LOC = "P32" | IOSTANDARD = LVTTL ; > NET "DATA_toMC<2>" LOC = "P34" | IOSTANDARD = LVTTL ; > NET "DATA_toMC<3>" LOC = "P35" | IOSTANDARD = LVTTL ; > NET "MC_READY" LOC = "P43" | IOSTANDARD = LVTTL ;#MC ist fertig mit > Auslesen > NET "MC_READ" LOC = "P44" | IOSTANDARD = LVTTL ;#MC soll mit > Auslesen beginnen > > NET "INDICATION_MUXtoMC<1>" LOC = "P47" | IOSTANDARD = LVTTL ; > NET "INDICATION_MUXtoMC<0>" LOC = "P59" | IOSTANDARD = LVTTL ; > > NET "LED_Z0" LOC = "P72" | IOSTANDARD = LVTTL ; > NET "LED_Z1" LOC = "P50" | IOSTANDARD = LVTTL ; > NET "LED_Z2" LOC = "P55" | IOSTANDARD = LVTTL ; > ###############LVDS-Kanäle############################### > NET "LVDS_Nr" LOC = "P88" | IOSTANDARD = LVDSEXT_25 ;#r: receive > NET "LVDS_Ns" LOC = "P90" | IOSTANDARD = LVDSEXT_25 ;#s: send > NET "LVDS_Pr" LOC = "P87" | IOSTANDARD = LVDSEXT_25 ; > NET "LVDS_Ps" LOC = "P89" | IOSTANDARD = LVDSEXT_25 ; > > ################TASTER#################################### > NET "BUTTON" LOC = "P21" | IOSTANDARD = LVTTL ;#USERSTART > > --Topmodule -File: > ********************************************************************** > ************************ > > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > use IEEE.STD_LOGIC_ARITH.ALL; > use IEEE.STD_LOGIC_UNSIGNED.ALL; > > library UNISIM; > use UNISIM.VComponents.all; > > entity TOPMODULE is > generic( > WAIT_WIDTH_USERSTART : positive := 28; > WAIT_WIDTH_MC_READY : positive := 10; > CNT_WIDTH : positive := 25 > ); > Port ( CLK_IN : in STD_LOGIC; > MC_READY : in STD_LOGIC; > BUTTON : in std_logic; > LVDS_Pr : in STD_LOGIC; --receive > LVDS_Nr : in STD_LOGIC; > LVDS_Ps : out STD_LOGIC;--send > LVDS_Ns : out STD_LOGIC; > LED_Z0 : out STD_LOGIC; > LED_Z1 : out STD_LOGIC; > LED_Z2 : out STD_LOGIC; > DATA_toMC : out STD_LOGIC_VECTOR (3 downto 0); > MC_READ : out STD_LOGIC; > CLK_fromMC : in std_logic; > INDICATION_MUXtoMC : out std_logic_vector(1 downto 0) > ); > end TOPMODULE; > > architecture Behavioral of TOPMODULE is > > component STATE_MACHINE > port(CLKX1 : in std_logic; > USER_START : in std_logic; > ADDRESS_CONTROL_FINISH : in std_logic; > MC_READY : in std_logic; > BRAM1_EN_toMUX : out std_logic; --Ausgangssignale zu BRAM1 > BRAM1_EN_SEND : out std_logic; > BRAM1_RESET_toMUX : out std_logic; > BRAM1_RESET_SEND : out std_logic; > BRAM2_EN_RECEIVE : out std_logic; --Ausgangssignale zu BRAM2 > BRAM2_EN_toMUX : out std_logic; > BRAM2_RESET_toMUX : out std_logic; > BRAM2_WRITE_EN : out std_logic; > MUX_RESET : out std_logic; > DES_EN : out std_logic; > SER_NEN : out std_logic; > SER_RESET : out std_logic; > ADDR_CONTROL_RESET_NEN : out > std_logic;--ADDRESS_CONTROL_RESET_(and)NotENable > MC_READ : out std_logic; > LED_Z0 : out std_logic; --die LEDs signalisieren den aktuellen > Zustand > LED_Z2 : out std_logic--; > ); > end component; > > component ADDRESS_CONTROL > generic( > ADDRESS_WIDTH : positive := 10 > ); > Port ( CLKX1 : in std_logic; > RESET_NEN : in STD_LOGIC; > ADDR_BRAM1 : out STD_LOGIC_VECTOR (9 downto 0); > ADDR_BRAM2 : out STD_LOGIC_VECTOR (9 downto 0); > FINISH : out std_logic > ); > end component; > > component SER16to1 > Port ( CLKX8 : in std_logic; --8facher Takt (bezogen auf den Takt > des 16 Bit breiten Datenbus) > CLKX8_180 : in std_logic; --8facher Takt invertiert > RESET : in std_logic; --Reseteingang > NotENABLE : in std_logic; > DATA_PARALLEL : in std_logic_vector(15 downto 0); > ODATA_LVDSP : out std_logic; > ODATA_LVDSN : out std_logic); > end component; > > component DES1to16 > Port ( ENABLE : in std_logic; --mit DCM_LOCKED verbinden > IDATA_LVDSP : in std_logic; > IDATA_LVDSN : in std_logic; > CLKX8 : in STD_LOGIC; > CLKX8_180 : in STD_LOGIC; > CLKX1 : in STD_LOGIC; > DATA_OUT : out STD_LOGIC_VECTOR (15 downto 0) > ); > end component; > > component MUX > generic( > DATA_WIDTH: positive := 4;--Breite des Datenbusses > ADRESS_WIDTH_toMC: positive := 12; > CONTROL_WIDTH: positive := 2--Anzahl der Steuerleitungen > ); > Port ( DATA1 : in STD_LOGIC_VECTOR (3 downto 0);--Daten von BRAM1 > DATA2 : in STD_LOGIC_VECTOR (3 downto 0);--Daten von BRAM2 > DATA_OUT : out STD_LOGIC_VECTOR (3 downto 0);--Datenbus zum > Mikrocontroller > ADRESS1 : out std_logic_vector(11 downto 0);--Adressbusse zu den > BRAMs > ADRESS2 : out std_logic_vector(11 downto 0); > RESET : in std_logic;--asynchrones Resetsignal von der > State-Machine > INDICATION : out STD_LOGIC_VECTOR(1 downto 0);--Kontrollbus > zum Mikrocontroller > CLK_extMC : in STD_LOGIC;--Auslesetakt für die BRAMs (vom > Mikrocontroller generiert) > CLK_fromMC :out STD_LOGIC > ); > end component; > > component BRAM_SEND > port( > DATA_toMUX : out std_logic_vector(3 downto 0); -- Port A 4-bit > Data Output > DATA_toSER : out std_logic_vector(15 downto 0); -- Port B > 16-bit Data Output > ADDRESS_MUX: in std_logic_vector(11 downto 0); -- Port A 12-bit > Address Input > ADDRESS_SEND: in std_logic_vector(9 downto 0); -- Port B 10-bit > Address Input > CLK_MUX : in std_logic; -- Port A Clock > CLKX1 : in std_logic; -- Port B Clock > EN_toMUX : in std_logic; -- Port A RAM Enable Input > EN_SEND : in std_logic; -- PortB RAM Enable Input > RESET_toMUX : in std_logic; -- Port A Synchronous Set/Reset > Input > RESET_SEND : in std_logic -- Port B Synchronous Set/Reset Input > ); > end component; > > component BRAM_RECEIVE > port( > DATA_toMUX : out std_logic_vector(3 downto 0); -- Port A 4-bit > Data Output > DATA_fromDES : in std_logic_vector(15 downto 0); -- Port B > 16-bit Data Intput > ADDRESS_MUX: in std_logic_vector(11 downto 0); -- Port A 12-bit > Address Input > ADDRESS_RECEIVE: in std_logic_vector(9 downto 0); -- Port B > 10-bit Address Input > CLK_MUX : in std_logic; -- Port A Clock > CLKX1_PS : in std_logic; -- Port B Clock (PS: phase-shifted) > Verzögerung des DUTs > EN_toMUX : in std_logic; -- Port A RAM Enable Input > EN_RECEIVE : in std_logic; -- PortB RAM Enable Input > RESET_toMUX : in std_logic; -- Port A Synchronous Set/Reset > Input > WRITE_ENABLE : in std_logic > ); > end component; > > > component GENERATE_CLOCK > Port ( CLKIN_IN : in std_logic; --Oszillator mit 66 MHz > (meltemi: P36) > CLKDV_OUT : out std_logic; --33 Mhz Takt > CLKFX_OUT : out std_logic; --264 MHz Takt > CLKFX180_OUT : out std_logic > ); > end component; > > > signal CLKX1, CLKX8, CLKX8_180 : std_logic; > signal ADDRESS_CONTROL_FINISH, BRAM1_EN_SEND, BRAM1_RESET_toMUX, > BRAM1_RESET_SEND : std_logic; > signal BRAM2_EN_RECEIVE, BRAM2_RESET_toMUX, BRAM2_WRITE_EN, MUX_RESET > : std_logic; > signal DES_EN, SER_NEN, SER_RESET, ADDR_CONTROL_RESET_NEN : std_logic; > signal ADDR_BRAM1, ADDR_BRAM2 : std_logic_vector(9 downto 0); > signal DATA_toSER16to1, DATA_fromDES1to16 : std_logic_vector(15 downto > 0); > signal DATA_toMUX_BRAM_S, DATA_toMUX_BRAM_R : std_logic_vector(3 > downto 0); > signal ADDRESS_BRAM_SEND, ADDRESS_BRAM_RECEIVE : std_logic_vector(11 > downto 0); > signal BRAM1_EN_toMUX, BRAM2_EN_toMUX : std_logic; > > signal USERSTART : std_logic := '0'; > > signal CLK_fromMC_buffered : STD_LOGIC; > > > --Taster : > --Tatser1 : > signal SHIFT_PB1 : STD_LOGIC_VECTOR (3 downto 0) := "0000"; > signal BUTTON_DEBOUNCED1 : std_logic := '0'; > signal LEVEL1 : std_logic := '0'; > > > --CLK-Indication : > signal CNT : std_logic_vector(CNT_WIDTH-1 downto 0) := (others => > '0'); constant MAX_CNT : std_logic_vector(CNT_WIDTH-1 downto 0) := > (others => '1'); > signal LEVEL : std_logic := '0'; > > > begin > > inst_GC : GENERATE_CLOCK > port map( > CLKIN_IN => CLK_IN, --externer Takt > CLKDV_OUT => CLKX1, --33 Mhz Takt > CLKFX_OUT => CLKX8, --264 MHz Takt > CLKFX180_OUT => CLKX8_180--CLKX8 um 180° phasenverschoben > > ); > > inst_SM : STATE_MACHINE > port map( > CLKX1 => CLKX1, > USER_START => USERSTART, > ADDRESS_CONTROL_FINISH => ADDRESS_CONTROL_FINISH, > MC_READY => MC_READY,--MC herausgenommen > BRAM1_EN_toMUX => BRAM1_EN_toMUX, --Ausgangssignale zu BRAM1 > BRAM1_EN_SEND => BRAM1_EN_SEND, > BRAM1_RESET_toMUX => BRAM1_RESET_toMUX, > BRAM1_RESET_SEND => BRAM1_RESET_SEND, > BRAM2_EN_RECEIVE => BRAM2_EN_RECEIVE, --Ausgangssignale zu BRAM2 > BRAM2_EN_toMUX => BRAM2_EN_toMUX, > BRAM2_RESET_toMUX => BRAM2_RESET_toMUX, > BRAM2_WRITE_EN => BRAM2_WRITE_EN, > MUX_RESET => MUX_RESET, > DES_EN => DES_EN, > SER_NEN => SER_NEN, > SER_RESET => SER_RESET, > ADDR_CONTROL_RESET_NEN => > ADDR_CONTROL_RESET_NEN,--ADDRESS_CONTROL_RESET_(and)NotENable > MC_READ => MC_READ, > LED_Z0 => LED_Z0, --die LEDs signalisieren den aktuellen Zustand > LED_Z2 => LED_Z2 > ); > > inst_AC : ADDRESS_CONTROL > port map( > CLKX1 => CLKX1, > RESET_NEN => ADDR_CONTROL_RESET_NEN, > ADDR_BRAM1 => ADDR_BRAM1, --BRAM_SEND > ADDR_BRAM2 => ADDR_BRAM2, --BRAM_RECEIVE > FINISH => ADDRESS_CONTROL_FINISH > ); > > inst_SER : SER16to1 > port map( > CLKX8 => CLKX8, --8facher Takt (bezogen auf den Takt des 16 Bit > breiten Datenbus) > CLKX8_180 => CLKX8_180, --8facher Takt invertiert > RESET => SER_RESET, --Reseteingang > NotENABLE => SER_NEN, > DATA_PARALLEL => DATA_toSER16to1, > ODATA_LVDSP => LVDS_Ps, > ODATA_LVDSN => LVDS_Ns > ); > > inst_DES : DES1to16 > port map( > ENABLE => DES_EN, --mit DCM_LOCKED verbinden > IDATA_LVDSP => LVDS_Pr, > IDATA_LVDSN => LVDS_Nr, > CLKX8 => CLKX8, > CLKX8_180 => CLKX8_180, > CLKX1 => CLKX1, > DATA_OUT => DATA_fromDES1to16 > ); > > inst_MUX : MUX > port map( > DATA1 => DATA_toMUX_BRAM_S,--Daten von BRAM1 > DATA2 => DATA_toMUX_BRAM_R,--Daten von BRAM2 > DATA_OUT => DATA_toMC,--Datenbus zum Mikrocontroller > ADRESS1 => ADDRESS_BRAM_SEND,--Adressbusse zu den BRAMs > ADRESS2 => ADDRESS_BRAM_RECEIVE, > RESET => MUX_RESET,--asynchrones Resetsignal von der > State-Machine INDICATION => > INDICATION_MUXtoMC,--Kontrollbus zum Mikrocontroller > CLK_extMC => CLK_fromMC--Auslesetakt für die BRAMs (vom > Mikrocontroller generiert) > ); > > inst_BRAM_S : BRAM_SEND --BRAM1 > port map( > DATA_toMUX => DATA_toMUX_BRAM_S, -- Port A 4-bit Data Output > DATA_toSER => DATA_toSER16to1, -- Port B 16-bit Data Output > ADDRESS_MUX => ADDRESS_BRAM_SEND, -- Port A 12-bit Address Input > ADDRESS_SEND => ADDR_BRAM1, -- Port B 10-bit Address Input > CLK_MUX => CLK_fromMC_buffered, -- Port A Clock > CLKX1 => CLKX1, -- Port B Clock > EN_toMUX => BRAM1_EN_toMUX, -- Port A RAM Enable Input > EN_SEND => BRAM1_EN_SEND, -- PortB RAM Enable Input > RESET_toMUX => BRAM1_RESET_toMUX, -- Port A Synchronous > Set/Reset Input > RESET_SEND => BRAM1_RESET_SEND -- Port B Synchronous Set/Reset > Input > ); > > inst_BRAM_R : BRAM_RECEIVE > port map( > DATA_toMUX => DATA_toMUX_BRAM_R, -- Port A 4-bit Data Output > DATA_fromDES => DATA_fromDES1to16, -- Port B 16-bit Data > Intput > ADDRESS_MUX => ADDRESS_BRAM_RECEIVE, -- Port A 12-bit Address > Input > ADDRESS_RECEIVE => ADDR_BRAM2, -- Port B 10-bit Address Input > CLK_MUX => CLK_fromMC_buffered, -- Port A Clock > CLKX1_PS => CLKX1, -- Port B Clock (PS: phase-shifted) > Verzögerung des DUTs > EN_toMUX => BRAM2_EN_toMUX, -- Port A RAM Enable Input > EN_RECEIVE => BRAM2_EN_RECEIVE, -- PortB RAM Enable Input > RESET_toMUX => BRAM2_RESET_toMUX, -- Port A Synchronous > Set/Reset Input > WRITE_ENABLE => BRAM2_WRITE_EN > ); > > > > --CLK-Indication : > CLK_indication: process(CLKX1) > begin > if (CLKX1'event and CLKX1 = '1') then > if CNT = MAX_CNT then > LEVEL <= not LEVEL; > CNT <= (others => '0'); > else > CNT <= CNT +1; > end if; > end if; > end process; > > LED_Z1 <= LEVEL; > --LED_Z1 <= '1'; > ----Taster1 : > DEBOUNCE1: process(CLKX1) > begin > if (CLKX1'event and CLKX1 = '1') then > -- Use a shIFt register to filter switch contact bounce > SHIFT_PB1(2 downto 0) <= SHIFT_PB1(3 downto 1); > SHIFT_PB1(3) <= BUTTON; > if SHIFT_PB1(3 downto 0) = "0000" then > BUTTON_DEBOUNCED1 <= '0'; > else > BUTTON_DEBOUNCED1 <= '1'; > end if; > end if; > end process; > > SWITCH1: process(BUTTON_DEBOUNCED1) > begin > if (BUTTON_DEBOUNCED1'event and BUTTON_DEBOUNCED1 = '1') then > LEVEL1 <= not LEVEL1; > end if; > end process; > > USERSTART <= LEVEL1; > > > end Behavioral; > > --GENERATE_CLOCK-FILE : > ********************************************************************** > *********** > > library ieee; > use ieee.std_logic_1164.ALL; > use ieee.numeric_std.ALL; > library UNISIM; > use UNISIM.Vcomponents.ALL; > > --konfiguriert für einen Eingangstakt der Frequenz 66 MHz > > entity GENERATE_CLOCK is > port ( CLKIN_IN : in std_logic; --Oszillator mit 66 MHz > (meltemi: P36) > CLKDV_OUT : out std_logic; --33 Mhz Takt > CLKFX_OUT : out std_logic; --264 MHz Takt > CLKFX180_OUT : out std_logic > );-- = '1' -> DCM eingeschwungen > end GENERATE_CLOCK; > > architecture BEHAVIORAL of GENERATE_CLOCK is > > component BUFG > port ( I : in std_logic; > O : out std_logic); > end component; > > component IBUFG > port ( I : in std_logic; > O : out std_logic); > end component; > > -- Period Jitter (unit interval) for block DCM_INST = 0.17 UI > -- Period Jitter (Peak-to-Peak) for block DCM_INST = 0.63 ns > component DCM > generic( CLK_FEEDBACK : string := "1X"; > CLKDV_DIVIDE : real := 2.0; > CLKFX_DIVIDE : integer := 1; > CLKFX_MULTIPLY : integer := 4; ---sonst 4 !!! > CLKIN_DIVIDE_BY_2 : boolean := FALSE; > CLKIN_PERIOD : real := 10.0; > CLKOUT_PHASE_SHIFT : string := "NONE"; > DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS"; > DFS_FREQUENCY_MODE : string := "LOW"; > DLL_FREQUENCY_MODE : string := "LOW"; > DUTY_CYCLE_CORRECTION : boolean := TRUE; > FACTORY_JF : bit_vector := x"8080"; > PHASE_SHIFT : integer := 0; > STARTUP_WAIT : boolean := FALSE; > DSS_MODE : string := "NONE"); > port ( CLKIN : in std_logic; > CLKFB : in std_logic; > RST : in std_logic; > PSEN : in std_logic; > PSINCDEC : in std_logic; > PSCLK : in std_logic; > DSSEN : in std_logic; > CLK0 : out std_logic; > CLK90 : out std_logic; > CLK180 : out std_logic; > CLK270 : out std_logic; > CLKDV : out std_logic; > CLK2X : out std_logic; > CLK2X180 : out std_logic; > CLKFX : out std_logic; > CLKFX180 : out std_logic; > STATUS : out std_logic_vector (7 downto 0); > LOCKED : out std_logic; > PSDONE : out std_logic); > end component; > > signal CLKDV_BUF : std_logic; > signal CLKFB_IN : std_logic; > signal CLKFX_BUF : std_logic; > signal CLKFX180_BUF : std_logic; > signal CLKIN_IBUFG : std_logic; > signal CLK0_BUF : std_logic; > signal GND1 : std_logic; > > begin > GND1 <= '0'; > CLKDV_BUFG_INST : BUFG > port map (I=>CLKDV_BUF, > O=>CLKDV_OUT); > > CLKFX_BUFG_INST : BUFG > port map (I=>CLKFX_BUF, > O=>CLKFX_OUT); > > CLKFX180_BUFG_INST : BUFG > port map (I=>CLKFX180_BUF, > O=>CLKFX180_OUT); > > CLKIN_IBUFG_INST : IBUFG > port map (I=>CLKIN_IN, > O=>CLKIN_IBUFG); > > CLK0_BUFG_INST : BUFG > port map (I=>CLK0_BUF, > O=>CLKFB_IN); > > DCM_INST : DCM > generic map( CLK_FEEDBACK => "1X", > CLKDV_DIVIDE => 2.0, > CLKFX_DIVIDE => 1, > CLKFX_MULTIPLY => 4, > CLKIN_DIVIDE_BY_2 => FALSE, > CLKIN_PERIOD => 15.1515, > CLKOUT_PHASE_SHIFT => "NONE", > DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", > DFS_FREQUENCY_MODE => "HIGH", > DLL_FREQUENCY_MODE => "LOW", > DUTY_CYCLE_CORRECTION => TRUE, > FACTORY_JF => x"8080", > PHASE_SHIFT => 0, > STARTUP_WAIT => TRUE) > port map (CLKFB=>CLKFB_IN, > CLKIN=>CLKIN_IBUFG, > DSSEN=>GND1, > PSCLK=>GND1, > PSEN=>GND1, > PSINCDEC=>GND1, > RST=>'0', > CLKDV=>CLKDV_BUF, > CLKFX=>CLKFX_BUF, > CLKFX180=>CLKFX180_BUF, > CLK0=>CLK0_BUF, > CLK2X=>open, > CLK2X180=>open, > CLK90=>open, > CLK180=>open, > CLK270=>open, > LOCKED=>open, > PSDONE=>open, > STATUS=>open); > > > end BEHAVIORAL; > > --STATE_MACHINE-FILE : > ********************************************************************** > ************** > > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > use IEEE.STD_LOGIC_ARITH.ALL; > use IEEE.STD_LOGIC_UNSIGNED.ALL; > > library UNISIM; > use UNISIM.VComponents.all; > > entity STATE_MACHINE is > port(CLKX1 : in std_logic; > USER_START : in std_logic; > ADDRESS_CONTROL_FINISH : in std_logic; > MC_READY : in std_logic; > BRAM1_EN_toMUX : out std_logic; --Ausgangssignale zu BRAM1 > BRAM1_EN_SEND : out std_logic; > BRAM1_RESET_toMUX : out std_logic; > BRAM1_RESET_SEND : out std_logic; > BRAM2_EN_RECEIVE : out std_logic; --Ausgangssignale zu BRAM2 > BRAM2_EN_toMUX : out std_logic; > BRAM2_RESET_toMUX : out std_logic; > BRAM2_WRITE_EN : out std_logic; > MUX_RESET : out std_logic; > DES_EN : out std_logic; > SER_NEN : out std_logic; > SER_RESET : out std_logic; > ADDR_CONTROL_RESET_NEN : out > std_logic;--ADDRESS_CONTROL_RESET_(and)NotENable > MC_READ : out std_logic; > LED_Z0 : out std_logic; > LED_Z2 : out std_logic--; > ); > end STATE_MACHINE;--Moore-Automat > > architecture Behavioral of STATE_MACHINE is > > type STATES is (Z0, Z1, Z2); > signal STATE: STATES := Z0; > signal NEXT_S: STATES := Z0; > > > signal STATE_Z0, STATE_Z2 : std_logic; > > > begin > > STATE_MEMORY: process(CLKX1) > begin > if CLKX1'event and CLKX1 = '1' then--eventuell Flanke ändern? > STATE <= NEXT_S; > end if; > end process; > > DEFINE_NEXT_STATE: process(USER_START, ADDRESS_CONTROL_FINISH, > MC_READY ,STATE) > begin > case STATE is > when Z0 => if USER_START = '1' then > NEXT_S <= Z1; > else > NEXT_S <=Z0; > end if; > when Z1 => if ADDRESS_CONTROL_FINISH = '1' then > NEXT_S <= Z2; > else > NEXT_S <=Z1; > end if; > when Z2 => if MC_READY = '1' then > NEXT_S <= Z0; > else > NEXT_S <=Z2; > end if; > end case; > end process; > > SET_OUTPUTS: process(STATE) > begin > case STATE is > when Z0 => BRAM1_EN_toMUX <= '0'; > BRAM1_EN_SEND <= '0'; > BRAM1_RESET_toMUX <= '1'; > BRAM1_RESET_SEND <= '1'; > BRAM2_EN_RECEIVE <= '0'; > BRAM2_EN_toMUX <= '0'; > BRAM2_RESET_toMUX <= '1'; > BRAM2_WRITE_EN <= '0'; > MUX_RESET <= '1'; > DES_EN <= '0'; > SER_NEN <= '1'; > SER_RESET <= '1'; > ADDR_CONTROL_RESET_NEN <= '1'; > MC_READ <= '0'; > when Z1 => BRAM1_EN_toMUX <= '0'; > BRAM1_EN_SEND <= '1'; > BRAM1_RESET_toMUX <= '1'; > BRAM1_RESET_SEND <= '0'; > BRAM2_EN_RECEIVE <= '1'; > BRAM2_EN_toMUX <= '0'; > BRAM2_RESET_toMUX <= '1'; > BRAM2_WRITE_EN <= '1'; > MUX_RESET <= '1'; > DES_EN <= '1'; > SER_NEN <= '0'; > SER_RESET <= '0'; > ADDR_CONTROL_RESET_NEN <= '0'; > MC_READ <= '0'; > when Z2 => BRAM1_EN_toMUX <= '1'; > BRAM1_EN_SEND <= '0'; > BRAM1_RESET_toMUX <= '0'; > BRAM1_RESET_SEND <= '1';--eventuall ändern ! > BRAM2_EN_RECEIVE <= '0'; > BRAM2_EN_toMUX <= '1'; > BRAM2_RESET_toMUX <= '0'; > BRAM2_WRITE_EN <= '0'; > MUX_RESET <= '0'; > DES_EN <= '0'; > SER_NEN <= '1'; > SER_RESET <= '1'; > ADDR_CONTROL_RESET_NEN <= '1'; > MC_READ <= '1'; > end case; > end process; > > INDICATE_STATE: process(STATE) > begin > case STATE is > when Z0 => STATE_Z0 <= '1'; > STATE_Z2 <= '0'; > when Z1 => STATE_Z0 <= '0'; > STATE_Z2 <= '0'; > when Z2 => STATE_Z0 <= '0'; > STATE_Z2 <= '1'; > end case; > end process; > > > LED_Z0 <= STATE_Z0; --die LEDs signalisieren den aktuellen Zustand > LED_Z2 <= STATE_Z2; > > end Behavioral; > > ADDRESS_CONTROL-FILE : > ********************************************************************** > ********** > > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > use IEEE.STD_LOGIC_ARITH.ALL; > use IEEE.STD_LOGIC_UNSIGNED.ALL; > > > entity ADDRESS_CONTROL is > generic( > ADDRESS_WIDTH : positive := 10 > ); > Port ( CLKX1 : in std_logic; > RESET_NEN : in STD_LOGIC; > ADDR_BRAM1 : out STD_LOGIC_VECTOR (ADDRESS_WIDTH-1 downto > 0); > ADDR_BRAM2 : out STD_LOGIC_VECTOR (ADDRESS_WIDTH-1 downto > 0); > FINISH : out std_logic > ); > end ADDRESS_CONTROL; > > architecture Behavioral of ADDRESS_CONTROL is > > signal FINISH_FLAG : std_logic; > signal CNT : std_logic_vector(ADDRESS_WIDTH-1 downto 0); > constant MAX_ADDRESS : std_logic_vector(ADDRESS_WIDTH-1 downto 0) := > "1111111111"; > > begin > > CHANGE_ADDRESS: process(CLKX1) > begin > if CLKX1'event and CLKX1 = '1' then > if RESET_NEN = '1' then > CNT <= (others => '0'); > FINISH_FLAG <= '0'; > else > if CNT = MAX_ADDRESS then > FINISH_FLAG <= '1'; > else > CNT <= CNT + 1; > FINISH_FLAG <= '0'; > end if; > end if; > end if; > end process; > > ADDR_BRAM1 <= CNT; > ADDR_BRAM2 <= CNT; > > FINISH <= FINISH_FLAG; > > end Behavioral; > > --SER-FILE : > ********************************************************************** > ****************************** > > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > use IEEE.STD_LOGIC_ARITH.ALL; > use IEEE.STD_LOGIC_UNSIGNED.ALL; > > library UNISIM; > use UNISIM.VComponents.all; > > entity SER16to1 is > Port ( CLKX8 : in std_logic; --8facher Takt (bezogen auf den Takt > des 16 Bit breiten Datenbus) > CLKX8_180 : in std_logic; --8facher Takt invertiert > RESET : in std_logic; --Reseteingang > NotENABLE : in std_logic; > DATA_PARALLEL : in std_logic_vector(15 downto 0); > ODATA_LVDSP : out std_logic; > ODATA_LVDSN : out std_logic); > end SER16to1; > > architecture Behavioral of SER16to1 is > > signal DATA_POS_EDGE, DATA_NEG_EDGE, DOUBLE_R_DATA : std_logic; > signal CNT, CNT0: std_logic_vector(2 downto 0):= (others => '0'); > > begin > > OFDDRRSE_inst : FDDRRSE --double datarate > port map ( > Q => DOUBLE_R_DATA, -- Data output (connect directly to > top-level port) > C0 => CLKX8, -- 0 degree clock input > C1 => CLKX8_180, -- 180 degree clock input > --Commonly, the Digital Clock Manager > --(DCM) generates the two clock signals by mirroring an > --incoming signal, then shifting it 180 degrees. This approach > --ensures minimal skew between the two signals. > CE => '1', -- Clock enable input > D0 => DATA_POS_EDGE, -- Posedge data input > D1 => DATA_NEG_EDGE, -- Negedge data input > R => NotENABLE, -- Synchronous reset input > S => '0' -- Synchronous preset input > ); > > OBUFDS_inst : OBUFDS --LVDS-Output > generic map( > IOSTANDARD => "LVDSEXT_25")--Standard: siehe Datasheet > S.62(Tabelle 36) > port map ( > O => ODATA_LVDSP, -- Diff_p output (connect directly to > top-level port) > OB => ODATA_LVDSN, -- Diff_n output (connect directly to > top-level port) > I => DOUBLE_R_DATA -- Buffer input > ); > > --******************************************************************** > *** -- Prozess: COUNT --Article: 113676
I have an old and obsolete design that I wish to upgrade to newer technology. Part of the design information for a 22V10 PAL has been lost and I am left with a file with the extension .dcf. Looking in the file, it appears to contain what is probably a fuse map and some vectors. I am not sure how the fuse details map onto the physical fuses to recover the boolean equations in the device. Can anyone advise me or guide me to a file/site that gives a proper definition of the format. Regards, Paul DixonArticle: 113677
"Sylvain Munaut <SomeOne@SomeDomain.com>" <246tnt@gmail.com> writes: > > --------------------------------------------------------------------------- > > xdlanalyze.pl: > > > > > > Shows statistics about an XDL file (or NCD file) as in the following > > example: (I'm not aware of any Xilinx command that will print this kind > > of (hierarchical) information about a place and routed design, please > > enlighten me if I've missed something.) > > Interesting, I didn't find it either and write my own tool that does > exactly > the same thing, just a few weeks ago ;) > Funnily enough - so did I! Must be the time of year for it :-) Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 113678
This thread is getting more amusing the longer it gets. :) Mike <222> wrote in message news:4587ed26$1_1@mk-nntp-2.news.uk.tiscali.com... > > "Andreas Ehliar" <ehliar@isy.liu.se> wrote in message > news:em8oe2$2j0$1@news.lysator.liu.se... >> On 2006-12-19, <222> <222> wrote: >> > Why do you say that my input is never used, what about >> > >> > always @ (in) ? >> >> If I run your design through leda (a linter for VHDL and >> Verilog) I get the following two warnings: >> >> * Signal cnt is missing in the sensitivity list > > What is a sensitivity list, please add it as appropriate so that > I can recompile the program. > > >> * An asynchronous feedback loop was detected on cnt. > > Please, can you correct the feedback, I have no idea where > this feedback is coming from, thanks. > > >> >> What it boils down to is that if you have an @() statement >> with only signals in it (no posedge or negedge) the synthesizer >> will infer combinatorial logic from it. And the synthesizer will >> not care about the sensitivity list at all basically. (It will > > There currently is no sensitivity list, hence I assume combinational > logic is what we want. > > >> handle it like you wrote always @* in Verilog 2001 more or >> less.) >> >> If you want something to synthesize, restrict yourself to >> always @(*) and always @(posedge clocksignal). >> >> If you want an asynchronous reset you can also use something like >> always @(posedge clocksignal or posedge resetsignal). >> >> (Or negedge as appropriate.) >> >> Otherwise you will most likely get a design that will not >> work in the same way as your simulation. >> >> >> /Andreas > >Article: 113679
Hello all, I would like to multiply by 4 a USB chip 12MHz clock. The phase shift is not important. I cannot use LatticeXP PLL because minimum input clock frequency is 25MHz. There is a way to work around this problem? I would like to save space and money avoiding an external oscillator. Thanks, Dan.Article: 113680
"Mike Lewis" <someone@micrsoft.com> wrote in message news:RYmdndDB8vc1gRXYnZ2dnUVZ_uuqnZ2d@magma.ca... > This thread is getting more amusing the longer it gets. :) Does anyone else suspect that '222' is actually a Turing machine configured to teach itself Verilog programming by holding pseudo-natural-language conversations on Usenet? It's certainly neither an engineer nor anyone who's ever going to be one. WillArticle: 113681
Mike Lewis wrote: > This thread is getting more amusing the longer it gets. :) > > Mike > He should start another one...again. <222> Your absolute lack of understanding is astounding. Even after people have given more help than you deserve, you continue to post things that make no sense. "out = !out is that not an assignment ?" Yes, it is. Too bad you are not using it. I dare you to try and draw the hardware you are attempting to make. Becuase what you have so far is awesome. I am incorporating it into my current design. It is basically a neural-computer that posts to forums in search of answers for every single issue for everything in life. Otherwise, I may have to read a manual or book to learn something. always @(anything_i_dont_understand_immediately) post_to_forum = 1'b1; always @(always) //is this a verilog construct...hmmmmmm, I wish. rtfm = 1'b0; Here is how I suggest you code you counter: always @(when_you_should) divide_my_clock_by_10 There has to be some synthesis tool that will infer correctly from here. Oh, and keep making the same signal equal to two different values at the same time. That will always work out for you. Wired-OR is your friend too. Sorry if this is a mean post, but some people aren't cut out for this stuff.Article: 113682
Hi, I am pretty new to the arena of interrupt handling and would need some help. I am currently using microblaze v4.00a and with Xilinx platform studio 7.1 to develop some UART handling routines. what I am not sure, is 1) whether the important registers (eg, stack pointers and other registers) are saved during an interrupt handling, or do I have to explicitly save them myself. I dun think this is handled by the microblaze and am wondering if the mb-gcc C compiler would be smart enough to do the same. kindly advice. thanks! ChrisArticle: 113683
First of all thanks for your replies ! I read a lot about debugging strategies and I did it similar as suggested. By now I corrected the error but I couldn=B4t define the exact position of the bug. I think it has something to do with the .ucf-file. I will now add the clocking period. So I can be sure that the interaction between the part is acting as suspected. Now I want to use 2 DCMs to produce three phase-shifted and period-delayed clocks(receiving-part) and three clocks that aren=B4t. For the delay I used a counting-structure combined with BUFGCEs. I also though about usind a shift register but I think it would cause more skew. Has anyone a better idea? Here=B4s the code: DELAY_CLK_PS: process(CLKX8) begin if CLKX8'event and CLKX8 =3D '1' then if DELAY_PS_EN =3D '1' then if CNT =3D MAX_CNT then U2_CLKX1_PS_ENABLE <=3D '1'; U2_CLKX8_PS_ENABLE <=3D '1'; U2_CLKX8_180_PS_ENABLE <=3D '1'; else U2_CLKX1_PS_ENABLE <=3D '0'; U2_CLKX8_PS_ENABLE <=3D '0'; U2_CLKX8_180_PS_ENABLE <=3D '0'; CNT <=3D CNT + 1; end if; else U2_CLKX1_PS_ENABLE <=3D '0'; U2_CLKX8_PS_ENABLE <=3D '0'; U2_CLKX8_180_PS_ENABLE <=3D '0'; CNT <=3D (others =3D> '0'); end if; end if; end process;Article: 113684
recently I had xst misunderstand generic ( K1 : std_logic_vector(19 downto 0) := x"3eeee"; ); ... constant K2 : std_logic_vector(19 downto 0) := not (K1) + 1; somehow K2 ended up being incorrect ... while modelsim did it like I expected it. constant K2 : std_logic_vector(19 downto 0) := x"00000" - K1; works fine ... Antti wrote: > Quiz: > > what is DCM CLKFX output frequncy if the CLKFX Divisor is set to 3 in > MHS file and input clock is 150MHz? > > snippet from MHS file > -------------------- > BEGIN dcm_module > PARAMETER C_CLKFX_DIVIDE = 3 > ... > END > -------------------- > > > Answer: > > DCM FX output will be 200MHz because the CLKFX multiply default value > is 4 ! When the FX multiply is set to default then the multiply > parameter is not present in the MHS file, and without knowing the > default or using the GUI to view the parameters its really hard to > guess. > unless you just know. > > Antti >Article: 113685
up yours.Article: 113686
222 wrote: > up yours. Solid play.Article: 113687
I has the same problem. I wanted to read/write from a DDR memory, so I used the PowerPC which is in the Virtex-II Pro FPGA that I have. You must have the EDK in order to make such a design :(. You can also use the MIG tool provided free by Xilinx, in order to produce a memory controller.Article: 113688
This is a beautiful place to stop this thread, otherwise it might go on ad nauseam. Peter Alfke On Dec 19, 10:16 am, "motty" <mottobla...@yahoo.com> wrote: > 222 wrote: > > up yours.Solid play.Article: 113689
Ndf wrote: > Hello all, > > > > I would like to multiply by 4 a USB chip 12MHz clock. The phase shift is not > important. > > I cannot use LatticeXP PLL because minimum input clock frequency is 25MHz. > > There is a way to work around this problem? I would like to save space and > money avoiding an external oscillator. > > > > Thanks, > > Dan. I see two possibilities: 1) Cheat a little bit (assume that 24 MHz works in most cases) and double the clock input using LUT delays (and hope it's close enough to 50% duty cycle for this to work). 2) Add an external PLL frequency multiplier chip. ICS has some small (8-pin SOIC) cheap (cheaper than a crystal oscillator) parts that work at this frequency. ICS570B comes to mind...Article: 113690
Does anybody know how can I simulate with Modelsim a design that containts a PowerPC in a Virtex-II Pro FPGA? I have done the PowerPC design using the EDK, and I have imported the design in ISE where I have connected it with another design implemented in the FPGA and now I want to simulate the whole design. I tried to create a testbench waveform in ISE, but it didn't work.Article: 113691
PicoBlaze C compiler has been available for some time already,
but until yesterday I never tried it.
But today when I type:
>start build.bat
then the following C file
----- cut -----
// This is first PCCOMP Program tested on MicroFpga!
// Target was S3-200 with KCPSM3_256S MF-Core
#include "..\inc\padmap.h"
#include "..\inc\board.h"
#include "..\lib\pinapi.h"
unsigned int i;
// Delay
void ledelay() { for (i=0;i<65000;i++) {} }
void main()
{
// blink a LED forever !
while (1) {
SetPin(LED1, 0); ledelay();
SetPin(LED1, 1); ledelay();
}
}
----- cut -----
generates a BIT file (without invoking synthesis or fpga implementation
tools)
and there is LED blinking on my desk right this moment :)
KCSPM3_256S core only supports maximum 256 FPGA I/Os but its still fun
the evaluation package is ready for download
http://www.microfpga.com/joomla/index.php?option=com_remository&Itemid=27&func=fileinfo&id=3
it includes the MicroFpga bitstreams and compile scripts
devices included:
xc2v1000_fg256
xc2v250_cs144
xc2v250_fg256
xc2v250_fg456
xc2v40_cs144
xc2v40_fg256
xc2v500_fg256
xc2v80_cs144
xc2v80_fg256
xc2vp2_ff672
xc2vp2_fg256
xc2vp2_fg456
xc2vp4_fg256
xc2vp4_fg456
xc2vp7_fg456
xc3s1000_fg320
xc3s1000_ft256
xc3s200_ft256
xc3s200_pq208
xc3s200_tq144
xc3s200_vq100
xc3s400_fg320
xc3s400_ft256
xc3s400_pq208
xc3s400_tq144
xc3s50_cp132
xc3s50_pq208
xc3s50_tq144
xc3s50_vq100
xc4vfx12_sf363
xc4vlx15_sf363
xc4vlx25_sf363
note: MicroFpga is useable on linux too, but PCCOMP and KCPSM3 are only
available for
windows platform - on linux the java based picoblaze assembler should be
used
(we have no scripts or support for that at the moment)
Antti
PS MicroBlaze based MicroFgpa packages are are also ready but will be
released a little later.
Article: 113692chriskoh wrote: > > I am pretty new to the arena of interrupt handling and would need > some help. I am currently using microblaze v4.00a and with Xilinx > platform studio 7.1 to develop some UART handling routines. what I > am not sure, is > > 1) whether the important registers (eg, stack pointers and other > registers) are saved during an interrupt handling, or do I have to > explicitly save them myself. > > I dun think this is handled by the microblaze and am wondering if > the mb-gcc C compiler would be smart enough to do the same. That depends on the machine you are using. Read its documentation. For example, an X86 saves the return address and the program status (flags, interrupt enables, etc.) automatically. Others may differ. -- Chuck F (cbfalconer at maineline dot net) Available for consulting/temporary embedded and systems. <http://cbfalconer.home.att.net>Article: 113693
Antti Lukats wrote: > PicoBlaze C compiler has been available for some time already, > but until yesterday I never tried it. > But today when I type: > the evaluation package is ready for download <snip> > > http://www.microfpga.com/joomla/index.php?option=com_remository&Itemid=27&func=fileinfo&id=3 Interesting, but light on specifics :) Which PicoBlaze C is this using, and what other tools do the bitstream insertion ? Up to what Code size ? -jgArticle: 113694
Hi, I'm interfacing 2 ADC to spartan 3 3s400. I need to phase shift the
"DATA READY" from ADC with DCM and I'm not succeed. First of all, is it a
good idea to phase shift the DATA READY signal for data capturing
purpose?
I did 90,180 and 270 shift and I did see some change. Now I would like to
use dynamic shift and here is my code. The problem is that status[0]
always high and the phase shift DCM doesn't seem to work. What do I
missed? please help.
always @ (posedge pixel_clk)
begin
if (rst) begin
y_dynamic <= 8'h00;
end
else begin
/***
handshacking for DCM request
***/
if(!req_phase_y)begin req_phase_y_ack <= 0; end
/***
state machine
***/
case(y_dynamic)
8'h00:begin
if(req_phase_y)begin
phase_y_cnt <= 0;
y_dynamic <= 8'h01;
req_phase_y_ack <= 1;
end
else begin
y_dynamic <= 8'h00;
end
PSEN_INy <= 0;
end
8'h01:begin
/***
phase_y_sign[0] is from I2C
phase_y_value is from I2C
phase_y_cnt is counter for phase_y_value
***/
if(phase_y_cnt <= phase_y_value)begin
PSEN_INy <= 1;
PSINCDEC_INy <= phase_y_sign[0];
phase_y_cnt <= phase_y_cnt + 1;
y_dynamic <= 8'h02;
end
else begin
PSEN_INy <= 0;
phase_y_cnt <= 0;
y_dynamic <= 8'h00;
end
end
8'h02:begin
if(PSDONE_OUTy)begin
y_dynamic <= 8'h01;
end
else begin
y_dynamic <= 8'h02;
end
end
default:begin end
endcase
end
end
Article: 113695I am trying to run 2 ChipScope instances connected to two different boards. Unfortunately, Xilinx doesn't support more than one USB cable... I found in the past that you can actually have 2 cables running at the same time if one of them is parallel... My problem now is that my new Dell PC doesn't have a parallel port (neither does it have a serial port )... So I got myself a USB to Parallel adapter, but the ChipScope doesn't want to work through it... It seems that it is only good for a printer. It doesn't even create a proper virtual LPT port... So, I was wondering if someone knows of an adapter that will work? Thanks, /MikhailArticle: 113696
Required a book or web reference or examples suitable for xilinx xc9635 familiy. Thanks.Article: 113697
The big difference, for better or worse, is that, in the olden days, you could, and you had to, understand everything down to the minutest details. Whether it was building vacuum tube radios in the 'fifties, leading a small group to design data processing equipment, and re-invent germanium-transistor circuitry, core-memory drivers and ultra-slow mag-tape radback in the 'sixties. Even as late as 1988, I had the "pleasure" of completely taking apart and re-writing the Xilinx data book. Pain and agony, but also the joy of tangible achievement. Nowadays, the jobs are usually so complex that nobody can understand, let alone create, the whole system. There is no way I could re-write our product documentation. Too many words, too many specialties, and too many fiefdoms. On the other hand, the tools are now so incredibly more powerful that jobs which almost killed us then, have now become trivial. Who remembers looking for once-a-minute transient events on an analog scope? Darken the room, and glue you face, pupils wide open, to the Tektronix screen... It's not a question of pride or envy, it is just dramatically differnt. But, thank God, certain principles just carry over... Peter Alfke On Dec 19, 5:04 am, "Daniel S." <digitalmastrmind_no_s...@hotmail.com> wrote: > I wonder if I should be jealous... on one hand, you got to do one-man IC > designs while on the other hand, the function alone is useless. All I > will ever see on the ASIC side is my functions representing only a > fraction of some 10M+ gates design. > > Well, I suppose you probably envy younger designers for having access to > programmable logic from the very start... but that's probably offset by > the pride of having a hand in making FPGAs a reality for the rest of us :) > > Peter Alfke wrote: > > For what it is worth: > > I designed the very first FIFO integrated circuit, the Fairchild 3341 > > in 1969/70. It was very popular for a while. But Fairchild did not > > patent it. > > Peter Alfke > > > On Dec 18, 5:13 am, "Daniel S." <digitalmastrmind_no_s...@hotmail.com> > > wrote: > >> Peter Alfke wrote: > >>> Let's leave it at that. We won't agree, but then: we do not have to...To agree, there would need to be an argument to agree on in the first > >> place. Since I was only proposing an alternative way of going about > >> pointer data domain crossing, the only thing possibly worth arguing over > >> is whether or not the approach is valid... and since I have used this > >> approach in an ASIC project, I have reasonable proof that it is. > > >> Is it the best implementation? That answer is application-specific.Article: 113698
Hi, I'm interfacing 2 ADC to spartan 3 3s400. I need to phase shift the
"DATA READY" from ADC with DCM and I'm not succeed. First of all, is it a
good idea to phase shift the DATA READY signal for data capturing
purpose?
I did 90,180 and 270 shift and I did see some change. Now I would like to
use dynamic shift and here is my code. The problem is that status[0]
always high and the phase shift DCM doesn't seem to work. What do I
missed? please help.
always @ (posedge pixel_clk)
begin
if (rst) begin
y_dynamic <= 8'h00;
end
else begin
/***
handshacking for DCM request
***/
if(!req_phase_y)begin req_phase_y_ack <= 0; end
/***
state machine
***/
case(y_dynamic)
8'h00:begin
if(req_phase_y)begin
phase_y_cnt <= 0;
y_dynamic <= 8'h01;
req_phase_y_ack <= 1;
end
else begin
y_dynamic <= 8'h00;
end
PSEN_INy <= 0;
end
8'h01:begin
/***
phase_y_sign[0] is from I2C
phase_y_value is from I2C
phase_y_cnt is counter for phase_y_value
***/
if(phase_y_cnt <= phase_y_value)begin
PSEN_INy <= 1;
PSINCDEC_INy <= phase_y_sign[0];
phase_y_cnt <= phase_y_cnt + 1;
y_dynamic <= 8'h02;
end
else begin
PSEN_INy <= 0;
phase_y_cnt <= 0;
y_dynamic <= 8'h00;
end
end
8'h02:begin
if(PSDONE_OUTy)begin
y_dynamic <= 8'h01;
end
else begin
y_dynamic <= 8'h02;
end
end
default:begin end
endcase
end
end
Article: 113699
On 2006-12-19, CBFalconer <cbfalconer@yahoo.com> wrote:
> chriskoh wrote:
>>
>> I am pretty new to the arena of interrupt handling and would need
>> some help. I am currently using microblaze v4.00a and with Xilinx
>> platform studio 7.1 to develop some UART handling routines. what I
>> am not sure, is
>>
>> 1) whether the important registers (eg, stack pointers and other
>> registers) are saved during an interrupt handling, or do I have to
>> explicitly save them myself.
>>
>> I dun think this is handled by the microblaze and am wondering if
>> the mb-gcc C compiler would be smart enough to do the same.
>
> That depends on the machine you are using. Read its
> documentation. For example, an X86 saves the return address and
> the program status (flags, interrupt enables, etc.) automatically.
> Others may differ.
The 68HC11 for example saves all registers on the stack.
Others (e.g. NIOS2) save nothing on the stack and just swap a
couple registers.
--
Grant Edwards grante Yow! My forehead feels
at like a PACKAGE of moist
visi.com CRANBERRIES in a remote
FRENCH OUTPOST!!
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