Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Hi I am currently working on a RGMII interface using the SPARTAN 3E FPGA. I have 1 clock pin (phy_rx_clk) feeding into a DCM and 2 DCM output clk0 and clk180 being used in my design. There is also an external module which I have no control over that will be sending DDR data and clock with the data have a minimum setup time of 1.4 ns and minimum hold time of 1.2 ns. I need to measure the setup time of the data when it reaches the first flip flop of the DDR which is found in the IOB itself. So I setup the constraint to have 2 ns setup time wrt the input clock called phy_rx_clk Now the timing analyzer tells me that it actually needs a setup time of 3.9 ns and I am wondering why it needs such a long setup time. Wouldn't the DCM introduce some delay in the clock line wrt to the data line thus reducing the setup time. Is there anyway to decrease this setup time to what I need. ------------------------------------------------------------------------------------------------------ * COMP "rgmii_rx_ctrl" OFFSET = IN 2 ns BEFORE COMP "phy_rx_clk" HIGH | Requested | Actual | Logic | Absolute |Number of Levels | 2.000ns | 3.928ns | 0 | -1.928ns | 2 ------------------------------------------------------------------------------------------------------ Thanks for any answer. AmishArticle: 114101
Hi Pablo, "Pablo" <pbantunez@gmail.com> writes: > Hi, has anybody worked with a fgpa/dsp board solution from "sundance"? > I need some information about the configuration and "bitstream > download" in those boards. In the web, they say that you need Code > Composer Studio for the DSP and 3L Diamond for FPGA but I want to know > if some other tools like ISE, XPS and IMPACT can be used for that. > > The reference is > http://www.sundance.com/web/files/productpage.asp?STRFilter=SMT761Q. > Yes, you can use Impact to configure the FPGA via a header on the board (well, you can on the SMT374 - I assume the ithers can as well). If you want a standalone boot, you need to program the DSP to configure the FPGA by bitbanging. You don't *need8 the 3L diamond stuff. You do need CCS if you want to write code for the DSP. We did this - we use the SMT374 for an embedded automotive image processing platform - we use none of Sundance's stuff at all! Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 114102
I was wondering if anyone had experience with using combinations of FPGA based CPUs and surrounding logic to perform iterative algorithms. For instance, if we want to implement different types of more complex computer vision algorithms in an embedded system, we may wish to use the parallelism of an fpga to do multiple parts of a 2d convolution or matrix operation in parallel. While the FPGA may be able to handle the number crunching requirements of a given algorithm, it seems to me to be ill suited to handle the iterative (often non-systolic) nature of many advanced image processing algorithms. Often more complex computer vision algorithms seem to be too complex to be handled solely by FPGA based logic. I was thinking of the case were we have an FPGA connected directly to a video source, and data is flowing into the system at some fixed rate. We may wish to process this data at several scales, and iteratively search the low scales up to the higher ones until we have found features of interest in the video stream. Perhaps we wish to mark those features by altering pixels in their local neighborhood. We may need to iteratively process multiple scales of image data and buffer the original video frame in off-FPGA DRAM, since there will not be enough on-FPGA BRAM to store full images. Once we find the region of interest, we may then wish to retrieve the original to be marked and then sent off as output video. A good example of this process might be, say, face detection. It seems to me that the iterative nature of these kinds of algorithms needs to be handled by a combination of CPU and FPGA logic. The FPGA handling the number crunching and parallel data paths, and the CPU handling the notion of when to iterate, or when to stop, or in general, what decision to take next based on the results of the FPGA's number crunching. The CPU could be built from programmable logic, or placed off-FPGA. Does anyone have experience with this kind of thing, or know of somewhere I might be able to find more information about optimal ways of coupling heterogenous processors? I am aware of Altera's C2H compiler, but have not used it, and don't know how optimally it combines FPGA/CPU resources. I might be in the market to hire a consultant, if one were knowledgeable in this area.Article: 114103
hi, thank you for all the information. Ok, now im directed towards simulation. i've downloaded the simulation model for RAM, but there is no model from the manufacturer for CMOS sensor. So my first task is to write a model for sensor, but im not sure which way to take in writing this. My options are pure verilog and verlog mixed with PLI (or something similar). The whole sensore is controlled by I2c interface, so i will need to implement i2c protocol as well. im wondering if there are any free models that implement i2c so that i can use directly. thank you CMOSArticle: 114104
> Are you coming from a software background? Yes, easy to guess ! Electronics hobbyist? Yes after leaving electronics for 20 years ... > > First, buttons need to be understood. The mechanical reality of switches is > that they bounce. The contacts don't physically go from 100% open to 100% > closed and back reliably. To accommodate the bounce, analog or digital > "debounce" circuits are used to give you one event for one action. > I have bouncing contacts problem on my trs80 late in 1978 ... ;) > Second, modern digital electronics work well with a single system clock that > takes inputs from the outside world through synchronizing blocks such that > each input event is seen in the system clock domain as a single event, much > like the debounce; this is most important when many changes occur at the > same time such as when 8 commuters (one byte of information) are trying to > enter a train at the same time the doors (system clock) are closing (hitting > the posedge). Not every commuter can get on the train if they all show up > right when the door closes. > > A system clock will allow the design to see a switch transition and lock out > a change in that switch until a specified time goes by. The counter - which > wants a single clock - will then have the ability to go up or down depending > on the debounced switch settings once per switch press. > Ok > It almost sounds like when I wanted to do a simple Microsoft Windows program > (having done much command-line stuff before) and had to deal with all the > infrastructure to produce the windows and their somewhat involved behavior. > But at least the nuances in electronics are fewer. Switch debounce for > digital circuits is usually one of the first lessons. Yes, doing Windows, java, Qt or Gtk programs need an "important" infrastructure. They also use the event driven approach which can be a big paradigm shift from command-line programming. By the way, the event-driven approach is perhaps nearer the way of thinking in electronics. I am currently trying to create a kind of makefile that produce and download binary file to the fpga board from a set of vhdl files and for a newcomer it is not so easy ... There are so much parameters ... If you go to Xilinx to Altera or XXX, I think you have to learn new softwares. Debugging electronics can also be difficult as debugging concurrent programs (race conditions) can be difficult. So I am not sure that the nuances in electronics are fewer. There are different. > > - John_H > OlivierArticle: 114105
Thanks for the explanations Jonathan. I will try this. Olivier Jonathan Bromley wrote: > John_H gave you the strongest hint: In current digital technologies, > and particularly in FPGAs, it is a VERY bad idea to try to describe > asynchronous state machines. Essentially you had something like > this... > > process(button) > begin > if button = '1' then > if button_seen = '0' then > button_seen <= '1'; > count <= count + 1; > end if; > else --- button = '0' > button_seen <= '0'; > end if; > end process; > > Logically this is fine, but think what it is asking the > hardware to do... On the transition of button from > 0 to 1 you need to set the "button_seen" flag and, > AT THE SAME INSTANT, increment the counter. > That requires all 8 bits (or however many) of the > counter to take up their new values simultaneously, > WITHIN the rather narrow time window between > button going true and button_seen following it. > Getting this to work right is exceptionally tricky, > since all the various pieces may take up their > new values at different speeds - so some may > reliably get their new values, some may fail to > get them, and others may do it unreliably. > > The solution is to use *synchronous design*, > exactly as you have done in your recent > clocked example, which follows the standard > synthesisable process template. Why, you may > well ask, is that different from what you did before? > Because the synthesis tool understands that it > implies flip-flops, and flip-flops have been very > carefully designed by your device vendor to ensure > that they reliably take up their new values on > each new clock cycle. To make this work you need > two things from your device vendor: > (1) reliable flip-flops as I've just described; > (2) a very cleverly designed clock distribution > network, so that all your flip-flops see the clock > at effectively the same instant - to find out more > about this, check out "hold time" in any good > digital design text book. > > Not surprisingly, the FPGA vendors provide > exactly this for you. So your new design > works, and you now have only the switch > bounce issues to worry about. > > Switches typically bounce for between 0.1ms > and 5ms, depending on how they're made. > At 50MHz that means you need quite a long > time delay to remove the bounce. Here's > a little piece of code that will do the trick: > > entity debounce is > generic (delay_count: natural := 10000); > port ( > clock, reset: in std_logic; > switch: in std_logic; > debounced: out std_logic > ); > end; > architecture A of debounce is > begin > process(clock, reset) > variable count: natural range 0 to delay_count; > variable new_switch, old_switch: std_logic; > begin > if reset = '1' then > count := delay_count; > old_switch := '0'; > new_switch := '0'; > elsif rising_edge(clock) then > if old_switch = new_switch then ---- switch stable, count down > if count=0 then --- timeout has expired, update output > debounced <= old_switch; > else --- still counting > count := count - 1; > end if; > else ---- switch has changed, start timing again > count := delay_count; > end if; > old_switch := new_switch; > new_switch := switch; > end if; > end process; > end; > > Note that the ONLY thing I do with the original switch input > is to copy it into the "new_switch" flip-flop, thereby avoiding > input hazards (another good search term to study!). Really > paranoid engineers might consider adding a metastability- > hardening flip-flop too, but I reckon that's too much for > a manual switch input. > > The reset isn't really essential in hardware because the > design will always sort itself out within a reasonable > time, but it makes life much easier for simulation.Article: 114106
The read and write signals have to be set one clock cycle before the action right? If I do the following, will it read the first FIFO byte? ... RD_EN <= '1'; TEST <= FIFO_OUT; ...Article: 114107
Thanks Guru, I too was able to resolve the problem that I was facing ... I did as follows: 1)I copied the file custom_bram.edn into the pcores/<core>/netlist directory. 2)In the import peripheral wizard, I ticked the option to use netlist files also as source files for the peripheral , and entered the path of the netlist file specified above. Now I am not getting any errors on bitstream generation.... :) My solutions seems to be similar to yours except for one difference ..... in the directory created by Xilinx Core Lib , I DO NOT see any file custom_bram.bbd ... The *.bbd has been discussed in another posts also , but I am yet to come across it in any of my designs... I am using EDK8.02.02i and ISE8.02.03i. "bbd" stands for black box description ... when does this concept come into the design flow? Thanks Again VenuArticle: 114108
By the way I'm using the latest coregen FIFO generator. My question is, using the code above, will TEST be set to the fifo out byte and the end of the clock cycle?Article: 114109
I keep getting the following warning from ISE:
FF/Latch <full_wf_out<319:317>> (without init value) have a constant
value of 0 in block <dhsm_in>.
FF/Latch <full_wf_out_316> is unconnected in block <d1>.
FF/Latch <full_wf_out_315> is unconnected in block <d1>.
FF/Latch <full_wf_out_314> is unconnected in block <d1>.
FF/Latch <full_wf_out_313> is unconnected in block <d1>.
FF/Latch <full_wf_out_312> is unconnected in block <d1>.
FF/Latch <full_wf_out_311> is unconnected in block <d1>.
FF/Latch <full_wf_out_310> is unconnected in block <d1>.
...and so on down to :
FF/Latch <full_wf_out_0> is unconnected in block <d1>.
The code for this was quite simple:
reg[319:0] full_wf_out;
always @(posedge clk)
begin
if(ch_cross_ctr[chnum]==36)//we're done
full_wf_out[319:0] <= {modnum, chnum, cross_time, samp8,
wf_ram_do[279:0]};
end
assign data_to_pci_q = full_wf_out //data_to_pciq is an output of
dhsm_in and an input to pci_pnp
What causes this pesky error?
Thanks,
Ian
Article: 114110Guru wrote: > I use MPMC2 memory controller with my peripheral connected to NPI port > (DMA write capable). When I enable caches the PPC does not read the > addr 0x00000000 properly, but when caching is disabled it works OK. I > am not clearing the caches before using it. I think not clearing the caches is your problem. If memory serves, you need to invalidate every single tag in the cache, post reset. You will also need to invalidate the cache tags for any data that MAY have been shanged outside the context of the processor. > I have two Avnet Virtex-4 Mini Modules with ES FPGAs. > > Is it possible to put a memory address at the end (or the beginnig) of > cached area; e.g. caching first 128MB and DDR memory start at > 0x07800000? Can this work? There are at least two ways to do this. The first is to use the TLB to do a "virtual" double map of the memory into a cacheable and non-cacheable region. This is overkill if you are not using the TLB for any other reason. The second, easier way, is to do a "physical" double map of the memory bank so it is visible from two 128MB regions. You would set the PLB address space for the memory controller to 256MB even though the SDRAM might be > Why is there no specs for bits 1-8 of CCR0? What do the bit 1 and 3 do? There is no need for you to know this. This is an "oh shit" port for the IP owner (IBM) to fix problems with his IP. Cache coherency is the responsibility of the user with the PPC405. The cache takes a tiny amount of silicon area, and drastically improves performance. But it does have some limitations as a result. There is also a great deal of flexibility in the modes that it can be employed. It is the responsibility of the user to understand this. > Frustration is what you get when you use PPC. If you want to have > little more performance than MB then this route is inevitable. Respectfully, I suggest you read all of the documentation regarding the cache, specifically the initial conditions (i.e. power up, and post reset state), and the setup and initialization procedures. The PPC is remarkable easy to use. We have come across a few gotchas along the way, but no more than usual. The documentation from IBM for this piece of IP is extremely complete. And the performance of the PPPC405 is not a little more perfomormance than the MB, it is many multiples for compute intensive (as opposed to IO intensive) applications, so long as the caches are turned on. The last thing I wonder about is this: Why the fascination with the GSRD design as a starting point? The power of this design comes from the fact that it allows a system with a memory bank that is capable of providing multiples of the easy to get to 800MB/sec performance of a PLB bus, to multiple such sources. With a x16 DDR configuration, and 400Mb/pin, you would only be capable of filling a single PLB bus. PLB bus masters can be extremely compact and easy to implement. And 70%+ utilization of the PLB bus is quite easy to achieve with quad-doubleword transfers. Double the burst length and your idle time on the bus will drop 2x. The topic of the IBM Coreconnect buses seems to constantly come up in this news group. The way in which Xilinx chose to implement the interfaces with the IPIF packages is not necessarily the simplest or most efficient. The Coreconnect buses just aren't that complicated. If we were to release an application note (or XCell Journal article) that described how to architect an efficient coreconnect based system with very high throughput, that also included basic VHDL behavioral code that implemented the following most basic cores: OPB Slave that can be 32bit read/written OPB Slave (for setup) / PLB Master that does quad-doubleword reads Would that help with all of this silliness of new users being drawn to these overly complicated reference designs? Our time is a little short these days, so I make no promises, it just seems that the same sort of issues come up repeatedly. Regards, Erik. --- Erik Widding President Birger Engineering, Inc. (mail) 100 Boylston St #1070; Boston, MA 02116 (voice) 617.695.9233 (fax) 617.695.9234 (web) http://www.birger.comArticle: 114111
Hi Pablo, I did something very similar last week, but i am working on the Xilinx Virtex2Pro Board and using the EthenetMacLite on the OPB Bus. I can outline the steps that you will have to look into: 1. You have instantiated the OPB Ethernet Core ... In EDK8.02 you will have to first specify that it is a slave on the OPB Bus , then assign it a address. The first step is trivail. 2. The User Manual of the Spartan Board that you are using will specify the pin configuration, that is which pins on the FPGA are connected to the Ethenet PHY chip on board ... You will have to copy these specifications from the document and paste in the constraints (system.ucf) file 3. In the Ports tab you have to export all the signals of the Ethernet core that are interfaced to the PHY chip ... You have to be careful to name the exported ports as they are named in the user manual and the ucf file. 4. Use the online Xilinx help to write a small C-code to be downloaded onto the processor so that it can send packets out through the Ethenet connection 5. Be sure to connect the Spartan Board and your system through a cross cable and not the normal ethernet cable. VenuArticle: 114112
wallge wrote: > I was wondering if anyone had experience with using combinations of > FPGA based CPUs and surrounding logic to perform iterative algorithms. > For instance, if we want to implement different types of more complex > computer vision algorithms in an embedded system, we may wish to use > the parallelism of an fpga to do multiple parts of a 2d convolution or > matrix operation in parallel. > While the FPGA may be able to handle the number crunching requirements > of a given algorithm, it seems to me to be ill suited to handle the > iterative (often non-systolic) nature of many advanced image processing > algorithms. Often more complex computer vision algorithms seem to be > too complex to be handled solely by FPGA based logic. > > I was thinking of the case were we have an FPGA connected directly to a > video source, and data is flowing into the system at some fixed rate. > We may wish to process this data at several scales, and iteratively > search the low scales up to the higher ones until we have found > features of interest in the video stream. Perhaps we wish to mark those > features by altering pixels in their local neighborhood. > > We may need to iteratively process multiple scales of image data and > buffer the original video frame in off-FPGA DRAM, since there will not > be enough on-FPGA BRAM to store full images. Once we find the region of > interest, we may then wish to retrieve the original to be marked and > then sent off as output video. A good example of this process might be, > say, face detection. > > It seems to me that the iterative nature of these kinds of algorithms > needs to be handled by a combination of CPU and FPGA logic. The FPGA > handling the number crunching and parallel data > paths, and the CPU handling the notion of when to iterate, or when to > stop, or in general, what decision to take next based on the results of > the FPGA's number crunching. The CPU could be built from programmable > logic, or placed off-FPGA. > > Does anyone have experience with this kind of thing, or know of > somewhere I might be able to find more information about optimal ways > of coupling heterogenous processors? > > I am aware of Altera's C2H compiler, but have not used it, and don't > know how optimally it combines FPGA/CPU resources. > I might be in the market to hire a consultant, if one were > knowledgeable in this area. Some ideas If you have the dosh, you might consider using the Opteron server boards with the 2nd socket used for an FPGA plugin module, there is one product for virtex and another for stratix, you will need to google for those. They were discussed in this group a year ago when they first came out but I forget the vendor names. One issue here is that the Opterons are comunicating with the FPGAs through the HT bus and the Opterons are running at compute speeds in the 2GHz & up while the FPGA may be grunting at 300MHz or less but massively parallel. The Opteron had better be smart about partioning the problem and not get to into the FPGA at too fine a grain otherwise the HT bus will be the bottleneck and either the cpu or FPGA may be idle. The other idea is to consider the soft core processor as a unit you can either customize at the instruction level by adding your own bit twiddly opcodes or add a coprocessor for more complex processing. Adding opcodes usually slows down the cpu since it has already been architected without your new opcodes in mind. The copro route should work better since this support is usually included in the architecture definition. If soft cores can perform most of their workload from a Bram with little need to go to external DRAM for code or data, then quite a few of these cores might be placed in the bigger FPGAs and you might then be able to mix and match with a mix of hardware engines under software control of local soft cpu and much closer in clock speed. You could think of a FFT butterfly box as a specialized cpu engine that has it instructions set in wired logic, generalize this into a DSP engine and there are many options. Also consider using real TI/ADI DSP chips with FPGA as possible accelerator and also look at nVidia GPUs as a PC accelerator, haven't been there but some folks claim some impressive speed ups and you probably already got the hardware. John Jakson transputer guyArticle: 114113
>The read and write signals have to be set one clock cycle before the action right? If I do the >following, will it read the first FIFO byte?
>
>... RD_EN <= '1'; TEST <= FIFO_OUT; ...
>
> By the way I'm using the latest coregen FIFO generator. My question is, using the code above, >will TEST be set to the fifo out byte and the end of the clock cycle?
>
>John,
Are you writing in Verilog or VHDL?
You need to show some more code. Are both of these things happening on
the same posedge clk? If so you will most certainly miss the first
piece of fifo out. Remember to think of these things in terms of
hardware. There is a rising time for every signal. For instance when
you say
RD_EN <= '1' (perhaps you assert this at every posedge clk), it takes
some time for the RD_EN signal to reach its value of one (this is the
rising time). I think you might be better off using combinational
logic for the RD_EN like so :
wire RD_EN = (CONDITION1 & CONDITION2 & ~CONDITION3);
Then you can do something like:
always @(posedge clk)
begin
if(RD_EN)
TEST <= FIFO_OUT;
end
Article: 114114Also, I assume you are using Xilinx ISE for synthesis, etc. If all else fails, do some simulation for a better idea of what is going on. I can not stress how helpful this is. Hope this helps. Best, IanArticle: 114115
colin wrote: > PeteS wrote: >> colin wrote: >>> Hi all >>> >>> I'm having trouble finding pcb layout recomendations on the altera and >>> xilinx web sites for lead free bga's. I'm wanting to use an altera F256 >>> package and I can find all I need for the leaded version but nothing >>> for the rohs packages. Does anyone know where I should be looking or >>> what changes to the leaded footprints I should make? >>> >>> all the best in 07 >>> >>> Colin >> I'm facing that issue right now for a FT256 package, and I'll do what >> I've done with all the other RoHS BGA parts I've had done leadfree (and >> that's quite a few) - use non-SMD pads with the recommended sizes from >> the leaded versions. >> >> If my manufacturer thinks it needs to be tweaked - after all, they do a >> *lot* of BGAs - they'll let me know. >> >> So far I haven't had any problems provided I use a gold finish; of >> course, I haven't had sufficient time to get decent long term >> reliability data. >> >> Cheers >> >> PeteS > > Thanks Pete, I will do the same. > > Colin > You're welcome. As it happens, after re-evaluating the design, I am going to plonk down a 456 ball RoHS compliant BGA (and 2 256 parts plus some - 6 - at about 100 balls apiece), so I'll let you know how it all turns out. Cheers PeteSArticle: 114116
Dave Pollum wrote: > Bob Perlman wrote: > > On Tue, 2 Jan 2007 10:14:21 -0000, "Symon" <symon_brewer@hotmail.com> > > wrote: > > > > >p.s. On the subject of US vs. UK toasting techniques, IMO the problem in the > > >US is not the toaster machines, it's the post-toasting technology. The toast > > >just gets piled up on a plate. The US seems to be a veritable toast rack > > >desert, so the toast always ends up soggy. I guess that's why it's IHOP and > > >not IHOT! :-) > > > Bob Perlman said: > We are an odd country: as you've suggested, we have very poor > post-toasting technology, but we do have a cereal called Post > Toasties. No one can explain this. > > And we drive on parkways and park on driveways. And we "pre-drill" and > "pre-heat". ;) > -Dave Pollum And special people get to "pre-board" an airplane! -aArticle: 114117
On Thu, 4 Jan 2007 12:06:55 -0000, "Symon" <symon_brewer@hotmail.com> wrote: >p.p.s. Bob, I found this http://en.wikipedia.org/wiki/Post_Toasties . The >article is on Wikipedia, so it must be true. It even mentions 'angry >clergyman', lending that needed air of authenticity. I don't know which is more intriguing: a cereal named Elijah's Manna (Now With 18% More Piety!), or the fact that Post Toasties has its own entry in Wikipedia. Truly, we are a species with too much time on its hands. Bob Perlman Cambrian Design Works http://www.cambriandesign.comArticle: 114118
A false path is not a real path ... the tool does not know what are real paths and what are not .. it just reports the longest path. A multi-cycle path is a path than can take more than one clock. The design may be such that a signal is not going to be used for a few clocks after it comes out of a FF. You can then tell the tool that this signal has more time to propagate using a multi-cycle constraint. Mike "Davy" <zhushenli@gmail.com> wrote in message news:1167909771.705282.273860@11g2000cwr.googlegroups.com... Hi Jerome, Thanks a lot! Can you tell me what's false path and multicycle path mean? Best regards, Shenli Jerome wrote: > Hi, > > i will just describe what i do: > > First, try to understand the violation: > is this a real one? > if not, add either a false path or a multicycle path or redefine > the timing definition in order to remove this false violation > if yes, change the RTL > regards. > > > Davy a écrit : > > Hi all, > > > > I am new to Synopsys DC. And I have a basic problem. When I find timing > > violation in DC report, what shall I do first? > > > > 1. Shall I change the script of DC? To let the tools do something like > > retiming? > > 2. Shall I change the RTL code? To pipeline the comb logic manually? > > 3. Other choice, please recommend. > > > > What circumstance to do "1" or "2" or "1 and 2 at the same time"? > > > > Best regards, > > Shenli > >Article: 114119
All, I am trying to run through the LatticeMico32 Tutorial from Lattice. Using 6.1.1 version LatticeMico32 System. I followed everything to a T in the tut, and I run the DRC as it says to and I get the following error: Info:DRC:Thu Jan 04 14:11:39 PST 2007 Start DRC Error:IRQ:No component with interrupt input connections Info:DRC:End DRC. Total errors 1 Now the LatticeMico32 ought to have the interrupt input, and they don't mention in the tutorial about needing to configure the Mico32 core to support interrupts. Based on my read it should just work. Anyone have any ideas, suggestions, or experiences? I pretty much can't implement the tutorial design because the tool will not generate the Mico32 Verilog with the DRC error in place. Thanks, -JoelArticle: 114120
"Davy" <zhushenli@gmail.com> wrote: >Hi all, > >I am new to Synopsys DC. And I have a basic problem. When I find timing >violation in DC report, what shall I do first? > >1. Shall I change the script of DC? To let the tools do something like >retiming? >2. Shall I change the RTL code? To pipeline the comb logic manually? >3. Other choice, please recommend. > >What circumstance to do "1" or "2" or "1 and 2 at the same time"? The first thing you should do is find out which part of the design doesn't meet the timing specifications. The Xilinix tools for instance show the elements causing the delay. From this you can decide whether you'll need to split the path (extra pipeline stage), alter the optimizer settings or change the timing constraints. -- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nlArticle: 114121
> > I am trying to run through the LatticeMico32 Tutorial from Lattice. > Using 6.1.1 version LatticeMico32 System. > > I followed everything to a T in the tut, and I run the DRC as it says > to and I get the following error: > > Info:DRC:Thu Jan 04 14:11:39 PST 2007 Start DRC > Error:IRQ:No component with interrupt input connections > Info:DRC:End DRC. Total errors 1 > > Now the LatticeMico32 ought to have the interrupt input, and they don't > mention in the tutorial about needing to configure the Mico32 core to > support interrupts. Based on my read it should just work. > > Anyone have any ideas, suggestions, or experiences? I pretty much > can't implement the tutorial design because the tool will not generate > the Mico32 Verilog with the DRC error in place. Hi, It might be worth posting on the Lattice web site Mico32 forum, as some of their developers read it: http://www.latticesemi.com/forums/forum/index.cfm?forumid=101 Cheers, JonArticle: 114122
ZHI wrote: > I would like to add some information here. I transmit these data by > separating them as 2 parts like this: > > for i= 1: N^2 > if R1(i) < 0 > R1(i) = R1(i) + 2^8; > end > for j=1:2 > if j==1 > R3(k)= rem(R1(i),256); > k=k+1; > elseif j==2 > R3(k)= floor(R1(i)/256); > k=k+1; > end > end > end > > Then I use a double-ports ram in FPGA to store these data, I use > 8bits wideth data port to receive these data. Data is out from a port > with 16bits width. So these data resume to the original ones. I guess > if these data actually needs 16bits, so I plus 2^8 will get the wrong > result. I cannot convince myself. Does anybody know something about it? > Thank you. It looks like you're using Matlab. Their integer functions are very clumsy. This would be easy in almost any other language. If you're looking to end up with 8-bit 2's complement integers, then you should add 2^7 not 2^8. This might clear up your problem. I don't understand what your loop on "j" is doing. So I can't comment further. Good luck. TomArticle: 114123
Post your question to the appropriate category on the Forums on www.latticesemi.com, and you should get some Applications Engineering support for the problem.Article: 114124
Hi Mike, Thanks a lot! I am also confused with your explaination. What cause the tool think there is a false path or multi-cycle path? IMHO, tools are the first important thing to believe? Best regards, Shenli Mike Lewis wrote: > A false path is not a real path ... the tool does not know what are real > paths and what are not .. it just reports the longest path. > > A multi-cycle path is a path than can take more than one clock. The design > may be such that a signal is not going to be used for a few clocks after = it > comes out of a FF. You can then tell the tool that this signal has more t= ime > to propagate using a multi-cycle constraint. > > Mike > > > > "Davy" <zhushenli@gmail.com> wrote in message > news:1167909771.705282.273860@11g2000cwr.googlegroups.com... > Hi Jerome, > > Thanks a lot! > Can you tell me what's false path and multicycle path mean? > > Best regards, > Shenli > > Jerome wrote: > > Hi, > > > > i will just describe what i do: > > > > First, try to understand the violation: > > is this a real one? > > if not, add either a false path or a multicycle path or redefine > > the timing definition in order to remove this false violation > > if yes, change the RTL > > regards. > > > > > > Davy a =E9crit : > > > Hi all, > > > > > > I am new to Synopsys DC. And I have a basic problem. When I find timi= ng > > > violation in DC report, what shall I do first? > > > > > > 1. Shall I change the script of DC? To let the tools do something like > > > retiming? > > > 2. Shall I change the RTL code? To pipeline the comb logic manually? > > > 3. Other choice, please recommend. > > > > > > What circumstance to do "1" or "2" or "1 and 2 at the same time"? > > > > > > Best regards, > > > Shenli > > >
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z