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"John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk> schrieb im Newsbeitrag news:1165867148.44940.0@iris.uk.clara.net... > First picture of Tarfessock1, minus cardbus covers, now on our website for > those that are interested in our little cardbus dual-FPGA development > board. > > John Adair > Enterpoint Ltd. > www.enterpoint.co.uk > WAU! you are hoping to ship in SEPTEMBER !!! its only 10 months from now :) and the board is using memory of type TBD !! AnttiArticle: 113351
John Adair wrote: > First picture of Tarfessock1, minus cardbus covers, now on our website for > those that are interested in our little cardbus dual-FPGA development board. Congrats. I'll take one in a 3S1600E guise, but there's no urgency. The picture is blurry! What's under the white square? :-) Cheers, TommyArticle: 113352
On 2006-12-11, Chao <ssc3k@yahoo.com> wrote: > Hi, everyone > I am designing a FPGA PCB board with one DDR2 dimm memory slot. As > current project will only need single dimm slot, is that mean I don't > need any termination resistor on the board? You shouldn't need termination on the board. Make sure the core you are using to talk to the DDR2 supports ODT! It's not just an on/off thing. (well, maybe it *could* be for a 1-module config, but even then your core has to set the mode registers right) -- Ben Jackson AD7GD <ben@ben.com> http://www.ben.com/Article: 113353
burn.sir@gmail.com wrote: > In an interview from 97, Bob Yannes the designer of MOS 6581 (aka > "SID") said the following aboud the chips ASDR enveloper: That interview is from Aug 1996, about two months before Ensoniq went kerblooey. -aArticle: 113354
John Adair wrote: > First picture of Tarfessock1, minus cardbus covers, now on our website for > those that are interested in our little cardbus dual-FPGA development board. Sorry, gotta ask: how do you come up with these names? -aArticle: 113355
"Andy Peters" <Bassman59a@yahoo.com> schrieb im Newsbeitrag news:1165873229.990241.88560@73g2000cwn.googlegroups.com... > John Adair wrote: >> First picture of Tarfessock1, minus cardbus covers, now on our website >> for >> those that are interested in our little cardbus dual-FPGA development >> board. > > Sorry, gotta ask: how do you come up with these names? > > -a > stones. holy stones. names of holy stones.Article: 113356
Folks, The FSL_V20 design is implemented in VHDL, how can I develop my code in Verilog and still be able to interface to the existing FSL device? Thanks BEA G=F6ran Bilski wrote: > If you planning to do some SW acceleration I would advice to use the FSL > interface on MicroBlaze instead. > There are drivers for handling FSL communication with EDK and you will mo= st > likely have a more performance by using FSL instead of OPB. > > G=F6ran > > <beagle197@hotmail.com> wrote in message > news:1165641995.350599.236560@79g2000cws.googlegroups.com... > > Folks, > > > > I have an EDK(*1) based project that utilizes the Microblaze, along > > with several peripherals connected via OPB (on-chip peripheral bus) for > > use with a Spartan3(*2). The project is set to use VHDL. I would like > > to develop a custom data encoder(*3) Verilog module that can be > > accessed via C, and I am trying to determine if developing the module > > as device that attaches to the OPB would be a good choice of > > implementation. Probably I am missing some important technical > > considerations about the verilog module's interfaces, etc. However, it > > appears that if I try to develop the lzw_opb in this fashion, it will > > require that I write a device driver similar to the other OPB > > components. Also since the project is set for VHDL, I am not certain > > how to develop the Verilog project along side. Wondering if anyone else > > has had a similar issue and can perhaps shed some light on how to > > approach this kind of problem? > > > > The basic design I have in mind is as follows: > > > > Data Input =3D> UART =3D> C code running on uBlaze =3D> updates state of > > lzw_opb =3D> UART =3D> Data out > > > > Thanks, > > BEA > > > > *1 Using Xilinx EDK 6.3 Build EDK_Gmm.12.3+1 > > *2 Spartan3 xc3s400 > > *3 LZW compression algo > >Article: 113357
Hi all I have a remote module which I can only easily get 2.5V to. Powering a xilinx or altera FPGA from this is easy but does anyone have any advice for powering the config prom. Both X and A solutions need at least 3.3. I can easily get a higher voltage/power to it to program the prom, I just need to get enough volts to it to program the fpga. ColinArticle: 113358
topweaver@hotmail.com wrote: > Hi, > Based on the suggestion of Gabor, I have revised Anydivider to generate > the following sample code. > Some other new features have also been added. The comparison between > DLL/PLL and TAD will also be added in the document. Topweaver > Anydivider 1.1 will be released soon after the final test. > > TAD > > /*********************************************************************************** > > Module Name : tad > Fout/Fin : 4/11 > Duty Cycle : 50.00000% > Jitter : 0.82645% > Website : http://www.topweaver.com > ... > ***********************************************************************************/ > > module tad ( > input rst , > input clk , > output reg error , > output clko > ); > reg [3:0] cnt ; > reg h ; > reg l ; > always @(posedge clk)begin > if(rst==1'b1)begin > cnt<=10; > end else begin > cnt<=(cnt>=10)?0:cnt+1'b1; > end > end > always @(posedge clk)begin > if(rst==1'b1)begin > h<=1'b0; > end else begin > h<= > ( > cnt==4 || > cnt==7 || > cnt==10 || > cnt>=0 && cnt<=1 > )?~h:h; > end > end > always @(negedge clk)begin > if(rst==1'b1)begin > l<=1'b0; > end else begin > l<= > ( > cnt==3 || > cnt==6 || > cnt==9 > )?~l:l; > end > end > /* > h and l cannot recover from a error state automatically, > so I think an optional error indicator is needed. > */ > always @(posedge clk)begin > if(rst==1'b1)begin > error<=1'b0; > end else begin > error<=(cnt==10)?(clko):error; > end > end > assign clko = h ^ l ; > endmodule Very nice! I did an experiment by pasting the above code into my test project. I used this code as a top level module with XST (6.1i) and ran post P&R simulation. Results looked pretty much the same as behavioural simulation, except for the output latency. Then I used FPGA editor to take all the slice logic and locate it in the very center of the XC2V3000. With the previously generated code this would cause big glitches due to clock routing delays. With the above code the simulation looked clean, again only affecting the output latency, not the waveshape. Regards, GaborArticle: 113359
While playing around with the Avnet utility that came with the Evaluation Kit, I discovered that doing a bulk erase of the SPI Flash, makes it possible to write to it. It would have been nice if Avnet had mentioned this in their documentation, for guys like me who are don't always think of the obvious. Xilinx also needs to fix ISE/iMPACT 8.2, so that it can generate HEX file for this PROM. For now you need to use ISE/iMPACT 7.1 to generate these files. With a few bug fixes in ISE/iMPACT 8.2 and the xspi_usb program, you could use one of them for programming the SPI Flash. Xilinx support tried their best to help me. When opening a Web Case at Xilinx I choose to interact by email. This resulted in trying one thing per day. Interaction by phone would have had a faster turn around time, but I don't know if that would have helped since I found the problem myself eventually. Avnet support ignored me. I might use the Avnet Spartan 3E Evaluation Kit again, because it is cheap and I now know how to make it work. Adding a QuickUSB PROM from Bitwise Systems, does increase the cost a little. QuickUSB is needed because the Cypress firmware and Windows device driver is useless. I also have an Opal Kelly board on order. If that works well I might use those for future projects instead. BillArticle: 113360
jonas@mit.edu wrote: > Keep in mind too that, for the really "interesting" stuff, you don't > generally need to physically touch hardware. We did all of our studies > with wavelet compression in FPGAs without ever touching hardware. The > synthesis and sim tools are all available cheap and run under windows, > and generally let you learn far more about what your code is doing than > the physical hardware would. This sounds like what I should be doing. Once I know what I am doing, I can start thinking about what hardware to use. I also have an Avnet Spartan 3E Evaluation Kit and an Opal Kelly Spartan 3 board, which I use for instrumentation applications. These boards will also work for testing FPGA programs. When I get to the point where I need to move stuff back and forth faster than the USB can handle I will think of getting something like the Raggedstone1. If I spend my money on a computer, I can convert the old one to a Linux box, eliminating the need for Windows device drivers. BillArticle: 113361
cippalippa wrote:
> I'm happy; finally the original DDR opencore code working; the only
> thing is that the frequency is only 50 MHz because the DCM that
> increase the frequency from 50MHz to 100MHz don't work (I use the
> Xilinx system generator in the webpack 8.2) but I hope to solve the
> problem quickly.
50 MHz is not good, because it violates timing of the DDR RAM. Use this
code for generating 266 MHz:
-- Spartan 3E stepping 0, speed grade -4 devices:
-- CLKFX frequency in "high" mode: min: 220 MHz, max: 307 MHz
clock266: dcm_sp
generic map(
clkfx_multiply => 16,
clkfx_divide => 3,
clkin_period => 4.0,
dfs_frequency_mode => "HIGH")
port map(
clkfx => clk_266mhz,
clkin => clk_50mhz);
As far as I understand, you can't divide to 133 MHz, because the datasheet
specifies different ranges for high and low mode for the speed grade -4
devices, so I've used this additional code for dividing 266 MHz by two:
-- divide 266 MHz to system clock
clock_divide: process(clk_266mhz)
begin
if rising_edge(clk_266mhz) then
clk_133mhz <= not clk_133mhz;
end if;
end process;
The signals:
signal clk_266mhz: std_logic := '0';
signal clk_133mhz: std_logic := '0';
Imports:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;
At least it works for my TCP/IP receiver/sender core, let me know, if it
works with your DDR implementation and maybe upload the project somewhere
or submit your modifications to the Open Cores project.
--
Frank Buss, fb@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de
Article: 113362Hi; I went back to look at this topic again (had other fires to fight first). For the life of me, I can't find the divide-by-6 or divide-by-12 value in the .MIF file that Quartus generates (hopefully I recompiled the project correctly -- no instructions in the downloaded example files for example #1). I've put a ticket into Altera's "mySupport" helpdesk, asking for more detailed info on how to do this. (My local supplier's FAE hasn't run into using ALTPLL and ALTPLL_RECONFIG cases yet). -Bob Subroto Datta wrote: > Hi Bob, also check out http://www.altera.com/literature/an/an367.pdf > > which will have more Stratix II specific information on this topic. > Hope this helps, > Subroto Datta > Altera Corp. > > On Nov 20, 3:11 pm, "Subroto Datta" <sda...@altera.com> wrote: > > Hi Bob, > > Please see if the user guide available athttp://www.altera.com/literature/ug/ug_altpll_reconfig.pdf > > answers your questions. If it does not do sen me email. > > > > Hope this helps, > > Subroto Datta > > Altera Corp. > > > > On Nov 20, 5:46 am, Bob <rjmy...@raytheon.com> wrote: > > > > > > > > > For some reason, I'm not getting how to create the various > > > .mif files to initialize enhanced PLLs with Quartus II. > > > I'm trying to target a Stratix II device. The situation that > > > I'm in will require me to reconfigure the PLL's divisors > > > dependent upon the state of an input pin on the FPGA. > > > > > Anyone got a step-by-step set of instructions that cleary > > > describe how to do this?- Hide quoted text -- Show quoted text -Article: 113363
Anyone have tips on having the Virtex 4 generate cleaner signals? I have 8 data lines coming out from the header IOs. They are supposed to be 3.3V but the noise amplitude swing is rather big, sometimes the high signal dips all the way to 2.1V. I have slew rates set to fast, drive is 12. What can I do in the FPGA to improve signal quality?Article: 113364
Tenteric, if you want any meaningful response, I suggest you give yourself a name, and you mention your educational level, and your geographic location. Without this, you will hardly get any answers. Peter Alfke On Dec 11, 9:58 am, "tenteric" <tente...@gmail.com> wrote: > Hello. > I've implemented few crypto algorithms in FPGA and I found this > exciting - it require very different way to think rather than in case > of conventional programming, etc. > So I wish to continue - to implement different crypto or math or > another calculation tasks in FPGA. > The question is - where and how should I start. Can I apply for > temporary/freelance job, if so, where should I try to do this? > Thanks in advance.Article: 113365
Chao wrote: > Hi, everyone > I am designing a FPGA PCB board with one DDR2 dimm memory slot. As > current project will only need single dimm slot, is that mean I don't > need any termination resistor on the board? Since the DDR2 will have > ODT(On Die Termination) technology. Even without ODT, it should not > cause signal reflection problem since this is only one dimm slot. Remember, ODT is for the bidirectional signals only (data, strobe, mask), not clock, address or command. >There > is no standby hi-Z on the end of transmission line. So there is no > necessary to put termination resistors on the end? Normal ref design > have two DDR2 Dimm Slots, I believe single slot is different. Can anyone > tell this idea is correct or more things need to be concern? Micron has lots of application notes here: http://www.micron.com/support/designsupport/documents/technotes including the very interesting TN4720 which has recommendations on termination and trace length matching. --- Joe Samson Pixel VelocityArticle: 113366
Antonio, Actually, the Spartan3 and Virtex4 do have bus macros available for use with ISE 8.x. The only place I know of on the web that has the latest bus macros is Xilinx's Partial Reconfiguration Early Access Software Tools website. There are early access tools, so you need to apply and be granted access. I believe Xilinx requires a certain level of local support to be in place before granting access. You can apply for access at http://www.xilinx.com/xlnx/xil_entry2.jsp?sMode=login&group=prealounge I hope this helps, David A.D. wrote: > Hi all, > does anybody know how partial reconfiguration is carried > out in new Xilinx FPGAs (Spartan3 and Virtex4)? > These devices have no internal three-state buffers or > bus macros, so is there a way to avoid contentions during > reconfiguration?!? > > Thanks, > AntonioArticle: 113367
John, The closest to a 50 ohm nominal trace IO driver is LVTTL/LVCMOS 8 mA SLOW, or 6 mA FAST. I suggest you simulate your signal integrity before doing anything. It is the shortest, and easiest path (as well as being the safest). AustinArticle: 113368
Perhaps having the config device in is providing enough of load to clean up the signals? Have you looked at the clock and data lines w/o the config device in to see if they're clean. I believe the standard clock rate is 10MHz, pretty respectable, and needs to treated appropriately during board layout. "Mark McDougall" <markm@vl.com.au> wrote in message news:457cfcd0$0$2704$5a62ac22@per-qv1-newsreader-01.iinet.net.au... > Nevo wrote: > >> I have a board designed around the EP1C6 Cyclone device. The Quartus >> programmer is able to detect the EP1C6 on a JTAG boundary scan. I'm able >> to >> initiate programming the device over the JTAG port, but Quartus gives me >> an >> error CONF_DONE failed to go high on device 1. > > Interesting that you have these problems... > > I have very recently inherited a board which I am using for a very > different purpose to that for which it was originally intended. The > board is based on an EP2C35 and has options for both passive and active > serial configuration, as well as JTAG. The former options require > configuration devices to be plugged into DIP sockets on the board. > > Not needing auto-configuration, I dispatched with the config devices (I > actually don't *own* any) but was met with "CONF_DONE not going high" > when attempting to configure via JTAG. > > After scratching my head for some time, I eventually tried it with the > config device plugged in - and it worked! > > Now I can't for the life of me understand why this device must be > present for JTAG programming? There's a pullup on CONF_DONE (10k)and > nSTATUS (10k). > > What's more, at one stage I configured the FPGA then removed the config > device whilst still powered - and I'm pretty sure a subsequent attempt > to configure the FPGA via JTAG actually succeeded!?! > > Ultimately I need a solution because eventually I probably won't have > access to the config device (it's on a small daughterboard) and I just > don't like not knowing *why* it doesn't work!?! > > So any suggestions/insight/wild guesses would be most welcome here too! > > I guess I should add that CONF_DONE is being routed to an empty header > (for ASM programming) and also an empty socket. > > Regards, > > -- > Mark McDougall, Engineer > Virtual Logic Pty Ltd, <http://www.vl.com.au> > 21-25 King St, Rockdale, 2216 > Ph: +612-9599-3255 Fax: +612-9599-3266Article: 113369
Hi, Does anyone have a design example to share of Power PC booting from ISOCM? :) Any information is welcome as well... Thanks, eArticle: 113370
Rob wrote: > Perhaps having the config device in is providing enough of load to clean up > the signals? Have you looked at the clock and data lines w/o the config > device in to see if they're clean. I believe the standard clock rate is > 10MHz, pretty respectable, and needs to treated appropriately during board > layout. But the JTAG lines don't even go to the config devices! Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 113371
The bus is implemented in VHDL but you don't need to write a new bus. Just create a new IP under pcores who will interface to the FSL bus. Connect the new IP to a FSL bus in the .mhs file. Göran <beagle197@hotmail.com> wrote in message news:1165874328.159836.106670@80g2000cwy.googlegroups.com... Folks, The FSL_V20 design is implemented in VHDL, how can I develop my code in Verilog and still be able to interface to the existing FSL device? Thanks BEA Göran Bilski wrote: > If you planning to do some SW acceleration I would advice to use the FSL > interface on MicroBlaze instead. > There are drivers for handling FSL communication with EDK and you will > most > likely have a more performance by using FSL instead of OPB. > > Göran > > <beagle197@hotmail.com> wrote in message > news:1165641995.350599.236560@79g2000cws.googlegroups.com... > > Folks, > > > > I have an EDK(*1) based project that utilizes the Microblaze, along > > with several peripherals connected via OPB (on-chip peripheral bus) for > > use with a Spartan3(*2). The project is set to use VHDL. I would like > > to develop a custom data encoder(*3) Verilog module that can be > > accessed via C, and I am trying to determine if developing the module > > as device that attaches to the OPB would be a good choice of > > implementation. Probably I am missing some important technical > > considerations about the verilog module's interfaces, etc. However, it > > appears that if I try to develop the lzw_opb in this fashion, it will > > require that I write a device driver similar to the other OPB > > components. Also since the project is set for VHDL, I am not certain > > how to develop the Verilog project along side. Wondering if anyone else > > has had a similar issue and can perhaps shed some light on how to > > approach this kind of problem? > > > > The basic design I have in mind is as follows: > > > > Data Input => UART => C code running on uBlaze => updates state of > > lzw_opb => UART => Data out > > > > Thanks, > > BEA > > > > *1 Using Xilinx EDK 6.3 Build EDK_Gmm.12.3+1 > > *2 Spartan3 xc3s400 > > *3 LZW compression algo > >Article: 113372
calling moose ... :) can someone give me an example of how to work with the opb_emc and write sequnce in c leng. ????? thanks PeteS wrote: > Guy_FPGA wrote: > > ok, > > say i have managed to program it.Do I read it using the emc as if it > > is a regular sram ? > > can i use the xio_in? > > > > thanks > > > > > > PeteS wrote: > > > Guy_FPGA wrote: > > > > Hello all, > > > > This is the first time i am working with Flash. > > > > Has anyone experienced with reading data from intel strata flash p30. I > > > > read the flash data-sheet and it says that in order to read array i > > > > need to write 0xFF to device base address. I didn't find the place > > > > where I insert the desire address to read from. can anyone explain me > > > > in simeple words what is the read or write sequence of the Flash. > > > > > > > > My next step is to write a C code that impliments the procedures of > > > > reading and writing. I have an OPB_EMC. I have talked with xilinx > > > > support and the guy there told me not to use xio_in16 or xio_out16 with > > > > the opb_emc base address + offset. Does anyone know what instead?? > > > > > > > > > > > > so, thanks alot in advance. > > > > > > > > Guy > > > > > > Once the device is in read array mode (which it defaults to on power up > > > or reset) simply assert the address you want to read on the address bus > > > and read the data on the data bus (i.e. it's a normal memory device). > > > > > > Cheers > > > > > > PeteS > > Assuming you have successfully programmed the device, it's readable as > a standard memory device. Check the timings; flash and sram are not > quite the same although in most cases the same timings are adequate. > > As to using your core, I can give you no advice without looking at the > details. If this is a standard core, then no doubt others here who may > have used it might be able to help. > > Cheers > > PeteSArticle: 113373
Hi Gabor, If I am not connecting A10 to SDRAM there is no problem, but if I connect A10 board hangs and is not even detected by the system. If anybody could help me get rid of this problem, please help. Thanks Mohni. Amirtham wrote: > "Have you tried using A9 and A11, but not A10?" > > I have only tried all A9, A10 and A11 together and not A9,A11 > seperately. > > Thanks > Mohni. > > > > > The one thing that comes to mind is that A10 has more than one > > function. > > So if you are not generating the "AutoPrecharge" function properly > > during > > Read and Write cycles, or "SelectAllBanks" function during refresh, you > > can run into problems. Have you tried using A9 and A11, but not A10? > > > > HTH, > > GaborArticle: 113374
Hi Clark. Thanks for your answer. At the moment in the application where ISRs are present no cache using has been enabled. So I don't think problem should related to it. I don't understand very well about interrupt table... I'm using, for the moment, to register the ISR in dynamic mode with the low level function XIntc_RegisterHandler(). I tested also the static mode setting handler function via EDK using software menu and so on... But problem are the same... Please could you explain better what you mean with "...Vector Table on 64 KB boundary.." ? Thank you very much. Al.
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