Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
"Antti Lukats" <antti@openchip.org> schrieb im Newsbeitrag news:el4ioe$log$1@online.de... > "Steve Knapp (Xilinx Spartan-3 Generation FPGAs)" <steve.knapp@xilinx.com> > schrieb im Newsbeitrag > news:1165348083.641699.51670@80g2000cwy.googlegroups.com... >> [... snip ...] >>> >>> Steven - you arent working for Altera? >>> >>> I clicked on the link to plddesignline and got a big flashing Altera >>> Stratix-III AD flyer !! >>> ok, well its beyound your control, but was amusing. >>> similarly as it was amysing to come to Xilinx booth at Electronica2006, >>> all >>> it was to >>> see was a big Actel Logo as their booth was just befor Xilinx and way >>> more >>> visible. >>> >>> Antti >> >> I saw that too, but unfortunately I don't get to decide who advertizes >> on the EE Times web sites. >> >> Hey, if you can afford a Stratix-III FPGA, I'd really like to introduce >> you to the following superior FPGA product line. :-) >> http://www.xilinx.com/virtex5 >> >> --------------------------------- >> Steven K. Knapp >> Applications Manager, Xilinx Inc. >> General Products Division >> Spartan-3/-3E/-3A FPGAs >> http://www.xilinx.com/spartan3e >> http://www.xilinx.com/spartan3a >> E-mail: steve.knapp@xilinx.com >> --------------------------------- >> The Spartan(tm)-3 Generation: The World's Lowest-Cost FPGAs. >> > HAHA - ROTFL > > I have been playing with Virtex-5 on my desk for some time now. > > V-5 is pretty cool, as finger-excercise I designed a > UART and baud rate divider for Virtex-5 that uses as much as > > LUTs --- 0 (zero) > FF's --- 0 (zero) > :) > Really - not cheating, it utilizes > > DSP48E --- 1 (one) > > but not FFs or LUTs from FPGA fabric > > -------- > > S-III will come before christmas (2007), ok some months before ;) > > Antti uups correction in single DSP48E was implement UART transmit channel and baud rate divider the receiver would not fit the same DSP slice (not in V5 at least) AnttiArticle: 113051
Hi all,
Has anyone ever had success routing an NPI port of the MPMC2
controller to an External Port of a PPC based system component in EDK
(i.e. I would like to route an NPI port to some custom logic...I use
the flow where I use EDK simply to generate a component & I
subsequently instantiate this in the top level of my VHDL design)? I
am having a lot of problems doing this. Xilinx doesn't have a
reference design available for this partuicular case; however, the
documentation for MPMC2 implies that one can do this. Please keep in
mind that I am an EDK newbie....I have been using Xilinx
Alliance/ISE/etc. for many years though :)!
What I seem to be seeing is that MPMC2 declares the NPI interface to
be a "transparent bus". Now, does this imply that I have to make some
kind of "bus to pins" converter and subsequently declare this component
in an MPD file, or is this completely useless? What I tried doing was
modify the MPMC2 MPD generated by the GUI...I simply removed the
"transparent bus" declaration from the MPD as well as all the labels on
the ports that were part of this bus, but that did not seem to help.
It almost seems like EDK is automatically recognizing the NPI bus as
some sort of "bus" and is getting confused no matter what I comment out
of the MPD.
I understand that my above description sounds rather stupid.
However, I am just throwing this out there for discussion to see if
anyone was successful doing this. Basically, my MPMC has 5 ports :
ISPLB
DSPLB
PLB (seems I need this so that I can add PLB slaves....if not added in
the MPMC2, I recall seeing errors...all reference designs seem to have
this as well).
OPB (again, seems like I need this in the MPMC2 or else I get errors
when adding OPB slaves to my EDK design...all reference designs seem to
have this as well)
NPI
All I really thought I would need would be the ISPLB and DSPLB so that
the PowerPC would have fast access to the DDR DRAM. The NPI is
basically intended as port for storing data that is streaming into the
FPGA. I hope to use custom hardware to pop data from DRAM after the
PowerPC does some processing on it.
If anyone has any tips, tricks, pointers, etc., it would be appreciated
greatly! I filed a webcase on this, but I would have to imagine that
someone out there has run into this situation before!
Thanks!
Ed
PS After re-reading this before posting, I realized that some of the
errors or warnings I get are related to the block diagram generator
getting confused about multiple busses and probably not able to place
and route the block diagram...this might simply be a red herring & an
actual physical implementation might be OK....I will post again if that
is the case, but I am having problems with the PLB masters and slaves
now not having matching bit widths...ugh...
Article: 113052"ed_h" <ehenciak@gmail.com> schrieb im Newsbeitrag news:1165351478.866080.261170@80g2000cwy.googlegroups.com... > Hi all, > > Has anyone ever had success routing an NPI port of the MPMC2 > controller to an External Port of a PPC based system component in EDK 1) dont change the MPD 2) in EDK set port visible filter "all" you should see all ports of all cores, and you can make any of then exertnal AnttiArticle: 113053
Is there any advantage of using a BUFIO/BUFR's for driving IOB FF's versus a BUFG? After looking through that section in the V4 user guide I'm not sure I really see an advantage other than resource usage of the global clock buffers. Normally I just use the typical IBUFG -> DCM -> BUFG setup and use the output of the BUFG to drive everything... Thanks, -BrandonArticle: 113054
I just downloaded from Altera's website QuartusII 6.1 and tried it out. I was disappointed that they didn't include any StratixIII device files with the web edition. I wanted to compare how QuartusII would have fitted what I'm working on, to the new devices. I also found the installer locked you into a predefined destination install directory. At one point I changed my install directory from 'quartus' to 'QuartusII'. The new installer will let you select the path to the directory but not the end directory. When I launched QuartusII it still was able to find my license file in the other directory. NiosII EDS, MegaCore Lib and ModelSim did the same. Maybe it is a bug in the installer because when I installed it didn't display the whole path but I doubt it since all the installers behaved that way. But comparing version 6.1 to 5.1 sp 2 I found it made better use of my dual core system then previous releases and it reported some of my signal paths slightly faster. Good job. DerekArticle: 113055
Antti, regarding Electronica (the biggest electronic component show in the world): the Actel booth was indeed surprisingly large and flat, and fairly empty. The Xilinx booth was more vertical and more crowded, also more crowded with customers and with serious conferences with customers. So we are quite happy (I was there). I am however amazed that Actel finds the money for such a large number of square meters... Altera, by the way, was hiding in a tiny cubicle next to some automotive guys, in a different hall. Everybody has different ideas about spending effort and money at shows... Peter Alfke, Xilinx On Dec 5, 11:31 am, "Antti Lukats" <a...@openchip.org> wrote: > "Steve Knapp (Xilinx Spartan-3 Generation FPGAs)" <steve.kn...@xilinx.com> > schrieb im Newsbeitragnews:1165346298.454531.194840@16g2000cwy.googlegroups.com... > > > Antti wrote: > >> Antti schrieb: > > >> > as Xilinx PR ES samples are available, and tools support for S3A also, > > >> as usual - the documentation is not complete :( > > > [... snip ...] > > >> Antti > > > Hi Antti, > > > There was about a 2-3 hour span last night when the Spartan-3A > > technical documentation wasn't yet available on the Xilinx web site. > > The nearly 1,000 pages of documentation all went live about 11 PM > > Pacific time on 4-DEC-2006.[..] > no problems, I actually found all i was looking for, but I had already > posted before > > > You may also be interested in the associated article discussing how to > > use the Device DNA. > > > How to implement high-security in low-cost FPGAs > >http://www.pldesignline.com/howto/showArticle.jhtml?articleID=196601422 > > > --------------------------------- > > Steven K. Knapp > > Applications Manager, Xilinx Inc. > > General Products Division > > Spartan-3/-3E FPGAs > >http://www.xilinx.com/spartan3e > > E-mail: steve.kn...@xilinx.com > > --------------------------------- > > The Spartan(tm)-3 Generation: The World's Lowest-Cost FPGAs.Steven - you arent working for Altera? > > I clicked on the link to plddesignline and got a big flashing Altera > Stratix-III AD flyer !! > ok, well its beyound your control, but was amusing. > similarly as it was amysing to come to Xilinx booth at Electronica2006, all > it was to > see was a big Actel Logo as their booth was just befor Xilinx and way more > visible. > > AnttiArticle: 113056
>I just downloaded from Altera's website QuartusII 6.1 and tried it > out. I was disappointed that they didn't include any StratixIII > device files with the web edition. I wanted to compare how QuartusII > would have fitted what I'm working on, to the new devices. Strange, in my download the smallest Stratix III were included... (I used custom installation, maybe that made a difference ?) > But comparing version 6.1 to 5.1 sp 2 I found it made better use of my > dual core system then previous releases and it reported some of my > signal paths slightly faster. Have you seen the "Maximum processors" in "Compilation process settings"? Changing this two 2 gives you another 10% improvement (better than nothing...). Thomas www.entner-electronics.comArticle: 113057
HI Antti,
First and foremost, thank you for the reply!
I tried your suggestion at first, but when I go to build the netlist
in EDK after connecting the ports using your suggested method, I get
this error:
ERROR:MDT - mpmc2_ddr_idpon_100mhz_x16_mt46v16m16_6t
(mpmc2_ddr_idpon_100mhz_x16_mt46v16m16_6t_0) -
C:\projects\test_single_npi\system.mhs line 235 - transparent bus
interface
connector 'npi_4' is only referenced once!
That is why I started editing the MPD and started removing the
transparent bus parameters and the like. I should have been a little
clearer in my initial post, but just let me blame that on my
inexperience with EDK :) .
When I remove the transparent bus types from the MPD, I get this
warning when I generate the block diagram :
WARNING:MDT - Bridge mpmc2_ddr_idponn_100mhz_x16_mt46v16m16_6t_0 is
connected to
more than two busses
WARNING:MDT - This condition is not handled by layout algorithm
Now I am starting to wonder if "layout" means layout of the block
diagram.....for whatever stupid reason, I associated "layout" with
"place and route" since I used to "layout" ASICs for a living a long,
long time ago :)! If all this means is that my block diagram is
incorrect (which it is after I remove the transparent bus), I can most
definitely live with that...
Again, many thanks! I'll be sure to post the solution to my
problem should I figure it out :)!
Ed
Antti Lukats wrote:
> "ed_h" <ehenciak@gmail.com> schrieb im Newsbeitrag
> news:1165351478.866080.261170@80g2000cwy.googlegroups.com...
> > Hi all,
> >
> > Has anyone ever had success routing an NPI port of the MPMC2
> > controller to an External Port of a PPC based system component in EDK
>
> 1) dont change the MPD
> 2) in EDK set port visible filter "all"
> you should see all ports of all cores, and you can make any of then exertnal
>
> Antti
Article: 113058Brandon Jasionowski wrote: > Is there any advantage of using a BUFIO/BUFR's for driving IOB FF's > versus a BUFG? After looking through that section in the V4 user guide > I'm not sure I really see an advantage other than resource usage of the > global clock buffers. > > Normally I just use the typical IBUFG -> DCM -> BUFG setup and use the > output of the BUFG to drive everything... > > Thanks, > -Brandon The BUFRs have less delay than the BUFGs, and the BUFIOs have less delay than the BUFRs. If you are going through a DCM, this may not matter to you, but if you are not using a DCM, it can matter quite a bit. The difference in speed depends on the size of the device. The BUFRs and BUFIOs only go to three clock regions, while the BUFGs can drive a clock to the entire chip. For example, I use the BUFRs and BUFIOs for interfacing to PCI because with them I can make the timing without using a DCM, and if I use BUFGs, I can not. I do not use DCMs on the PCI clock for several reasons, including that it may be spread spectrum and may change frequency, and I want to save them for other uses. Regards, John McCaskillArticle: 113059
Brandon Jasionowski wrote: > Is there any advantage of using a BUFIO/BUFR's for driving IOB FF's > versus a BUFG? After looking through that section in the V4 user guide > I'm not sure I really see an advantage other than resource usage of the > global clock buffers. > > Normally I just use the typical IBUFG -> DCM -> BUFG setup and use the > output of the BUFG to drive everything... The BUFIO and BUFR are really meant for use with source-synchronous data inputs. The BUFIO can only be driven from clock-capable input pins. The BUFR can be driven from the BUFIO or the fabric, but there not much advantage if you're driving it from the fabric. The typical use is to have the BUFIO clock the input SERDES at the fast clock rate, and use the BUFR with its divider to clock the SERDES outputs to the fabric. --- Joe Samson Pixel VelocityArticle: 113060
Derek Simmons wrote: > I just downloaded from Altera's website QuartusII 6.1 and tried it > out. I was disappointed that they didn't include any StratixIII > device files with the web edition. I wanted to compare how QuartusII > would have fitted what I'm working on, to the new devices. > > I also found the installer locked you into a predefined destination > install directory. At one point I changed my install directory from > 'quartus' to 'QuartusII'. The new installer will let you select > the path to the directory but not the end directory. When I launched > QuartusII it still was able to find my license file in the other > directory. NiosII EDS, MegaCore Lib and ModelSim did the same. Maybe it > is a bug in the installer because when I installed it didn't display > the whole path but I doubt it since all the installers behaved that > way. Hmmm. If the software developers can't figure out a variable path, I'm not sure I would be willing to trust my FPGA development to them. [I will note that this is a personal nit; put the tools where *I* want them, not some predetermined place *you* want them] Cheers PeteS > > But comparing version 6.1 to 5.1 sp 2 I found it made better use of my > dual core system then previous releases and it reported some of my > signal paths slightly faster. > > Good job. > > DerekArticle: 113061
"Peter Alfke" <peter@xilinx.com> schrieb im Newsbeitrag news:1165356300.186322.284830@l12g2000cwl.googlegroups.com... > Antti, regarding Electronica (the biggest electronic component show in > the world): > > the Actel booth was indeed surprisingly large and flat, and fairly > empty. > The Xilinx booth was more vertical and more crowded, also more crowded > with customers and with serious conferences with customers. So we are > quite happy (I was there). > I am however amazed that Actel finds the money for such a large number > of square meters... > Altera, by the way, was hiding in a tiny cubicle next to some > automotive guys, in a different hall. > Everybody has different ideas about spending effort and money at > shows... > Peter Alfke, Xilinx > Hi Peter, right you are, Xilinx booth was way more crowded both by customers and Xilinx own personel. I looked shortly at the ice cold igloo at actel, but well I already did know all that so there wasnt much todo there. was much more interesting at Xilinx booth as of Altera, its not the first time they are at automotive section, I never really understood it, but... there are things to learn from: last year at Altera I got a small soft-ball, its was really nice, exactly the size that my children (3 and 4yr) can handle it with their smallish hands. this year I got a coffe mug from Altera, commentary from my wife: * right size * right form * right color * right finishing (eg the surface texture) ==> almost perfect ? ok, its not required to have 'perfect' take-aways at the shows, but sometimes its nice, and sometimes its small things that you remember, and sometimes its small things that make the difference. AnttiArticle: 113062
"ed_h" <ehenciak@gmail.com> schrieb im Newsbeitrag news:1165356904.533431.323000@l12g2000cwl.googlegroups.com... > HI Antti, > > First and foremost, thank you for the reply! > > I tried your suggestion at first, but when I go to build the netlist > in EDK after connecting the ports using your suggested method, I get > this error: > > ERROR:MDT - mpmc2_ddr_idpon_100mhz_x16_mt46v16m16_6t > (mpmc2_ddr_idpon_100mhz_x16_mt46v16m16_6t_0) - > C:\projects\test_single_npi\system.mhs line 235 - transparent bus > interface > connector 'npi_4' is only referenced once! > hm.. if the direct port export realy isnt working you need to create a dummy wrap-export ip core that doesnt do anything except connects to NPI and export wires that can be used as external ports. this should work, and I would say its better than post modifying the MPMC2 generated MPD file AnttiArticle: 113063
Is there a mindelay constraint keyword or something similar? My fpga is producing 1 byte with a clock signal going to the pads and I need the data to be on the pads for 5ns, then clock. So I just need a way to delay the clock until data is definitely ready.Article: 113064
by the way I'm using virtex 4 and I'm having sampling issues. The signal it produces is not that clean for some reason.Article: 113065
Thomas Entner wrote: > >I just downloaded from Altera's website QuartusII 6.1 and tried it > > out. I was disappointed that they didn't include any StratixIII > > device files with the web edition. I wanted to compare how QuartusII > > would have fitted what I'm working on, to the new devices. > > Strange, in my download the smallest Stratix III were included... (I used > custom installation, maybe that made a difference ?) > > > But comparing version 6.1 to 5.1 sp 2 I found it made better use of my > > dual core system then previous releases and it reported some of my > > signal paths slightly faster. > > Have you seen the "Maximum processors" in "Compilation process settings"? > Changing > this two 2 gives you another 10% improvement (better than nothing...). > > Thomas > > www.entner-electronics.com When I restarted QuartusII the next time the StratixIII devices were available. The first time I ran it I clicked on the 'Web License Update' and I don't know why it didn't occure to me then that I should restart the application. Maybe I was talking to somebody. Anyways they are available now. I didn't see much of difference in build time or processor activity when I changed the number of processors. But my code really isn't too complex. At the statement level it isn't too complex and I stay away from complex compound statements (less work for the front end). Other designers code I have looked at can run on page after page, and I think to myself that they could have broken it up, created a simpler presentation, and made it easier to maintain. DerekArticle: 113066
This sounded interesting until I saw the output. It is not a frequency of pulses, but rather the incoming pulse-stream with the appropriate number of pulses deleted. That means a big jitter (except for the trivial cases of integer division) and a broad spectrum. If that is acceptable, your solution is still not optimal, as shown in your example of 4/11, which could have a better spectrum than the one you provide. A good solution should only delete n and n-1 consecutive pulses. Peter Alfke On Dec 5, 6:34 am, topwea...@hotmail.com wrote: > Hi, > I have just finished this free commercial grade tool. I wish it is > useful. > Topweaver Anydivider (TAD) is a GUI based EDA tool to generate a > divided output clock (frequency = Fout) based on an input clock > (frequency = Fin), without a DLL/PLL. The waveform of the output clock > can be either from automatical calculation or from visual adjustment. > Fout=Fin * M / N > TAD can analyze the relation of duty cycle and jitter. > The generated code are written by verilog. Thanks to the mixed-language > feature of most EDA tools, VHDL user can use it directly. > For more features, please visithttp://www.topweaver.com/doc/tad/tad.htm > Downloadhttp://www.topweaver.com/download.htmArticle: 113067
Ed, > Has anyone ever had success routing an NPI port of the MPMC2 > controller to an External Port of a PPC based system component in EDK > (i.e. I would like to route an NPI port to some custom logic... I haven't tried exporting MPMC2 ports, but I succeded in designing a NPI peripheral. If you really want to export the pins you probably have to do what Antti says, i.e. create a dummy peripheral. But then why not to do your whole custom thing as a peripheral? /MikhailArticle: 113068
Do not even think about generating a 5 ns delay by analog means, like concatenated buffers or LUTs. :-( Virtex-4 has a Digital Clock Manager (DCM) that allows you to delay a clock in very small increments. Just pick the apprpriate increment or clock polarity. And keep working on your "cleanliness" issue. Peter Alfke On Dec 5, 3:26 pm, John <seabass...@yahoo.com> wrote: > by the way I'm using virtex 4 and I'm having sampling issues. The signal it produces is not that clean for some reason.Article: 113069
I would use one of the pins in question and attach a 1 kilohm resistor. Then you first ground the other end of that resistor, and later connect it to Vcc. If the pin follows these two levels, it is obviously not being driven. If it does not move Low and High, you have a driven pin. Under static conditions, you can use a $10 multimeter, or the ubiquitous 'scope. Dynamically you can also use your slightly more expensive logic analyzer. Peter Alfke On Dec 5, 8:21 am, zhongqiang.ch...@gmail.com wrote: > hi, > > We have a FPGA Board, on which there is a RAM. RAM connected with FPGA, > nat=FCrlich, :) > > How can i make sure, the output of the RAM is HIGH Z, when i set > de-select the RAM. I 've a logic analyzer anhand, is this useful? >=20 > Thanks >=20 > ChengArticle: 113070
As stated BUFIO/BUFR is intended for Source Synchronous Applications. There are significant advantages of using BUFIO/BUFR with ISERDES for source sync data capture: The sampling window is smaller, and the setup time is negative. One simply can instantiate BUFIO/BUFR/ISERDES to capture data without doing any type of clock/data alignment; provided that the data eye > (setup+hold). Also, if you'd like to forward a clock for SDR application, you can only use BUFIO to drive clock frequency > 500MHz. -M Joseph Samson wrote: > Brandon Jasionowski wrote: > > Is there any advantage of using a BUFIO/BUFR's for driving IOB FF's > > versus a BUFG? After looking through that section in the V4 user guide > > I'm not sure I really see an advantage other than resource usage of the > > global clock buffers. > > > > Normally I just use the typical IBUFG -> DCM -> BUFG setup and use the > > output of the BUFG to drive everything... > > The BUFIO and BUFR are really meant for use with source-synchronous data > inputs. The BUFIO can only be driven from clock-capable input pins. The > BUFR can be driven from the BUFIO or the fabric, but there not much > advantage if you're driving it from the fabric. The typical use is to > have the BUFIO clock the input SERDES at the fast clock rate, and use > the BUFR with its divider to clock the SERDES outputs to the fabric. > > --- > Joe Samson > Pixel VelocityArticle: 113071
I have two problems in verilog gate level simulation 1) I want to preserve hierarchy between entity.Where will be this setting in quartus s/w 2) The gate level netlist has time scale has 1ps/1ps.test bench and host models have 1ns/10ps.I want to change the time scale of netlist.is it feasible for changing the delays after # symbol.How to do it kumarArticle: 113072
I'm looking into buying the fpga and/or cpld starter kits. I was wondering if the logic chips can be taken out of the development board after they are programmed. ThanksArticle: 113073
1) Use the Assignments->Settings->EDA Tools Settings dialog. Enter your simulation tool name and then click the More Settings button. Then change the valueof Maintain Hierarchy to On. 2) Use the Assignments->Settings->EDA Tools Settings dialog. Set Format for output etlist to Verilog. Then change the time scale settings right next to it. Then regenerate the netlist. Hope this helps, Subroto Datta Altera Corp. "ram" <vsrpkumar@rediffmail.com> wrote in message news:1165370100.584453.313030@80g2000cwy.googlegroups.com... >I have two problems in verilog gate level simulation > 1) I want to preserve hierarchy between entity.Where will be this > setting in quartus s/w > 2) The gate level netlist has time scale has 1ps/1ps.test bench and > host models have 1ns/10ps.I want to change the time scale of netlist.is > it feasible for changing the delays after # symbol.How to do it > kumar >Article: 113074
wanwan wrote: > I'm looking into buying the fpga and/or cpld starter kits. I was > wondering if the logic chips can be taken out of the development board > after they are programmed. Sure, but they are unlikely to be usable afterwards :-) Besides, only CPLDs are non-volatile. It would be rather pointless for an FPGA. Your question suggest that you don't really understand CPLDs and FPGAs. Both are really meant to be programmed in-system. The FPGA is usually programmed on each power on, typically from a serial programming flash or a microcontroller. If you do need them in a different application, you're better of laying out a board and populate it with fresh chips. Be warned though, it's a lot more complicated than with a microcontroller. Get a Spartan 3E starter kit or the Cyclone II Starter Development Kit, read the documentation and play with it. Cheers, Tommy
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z