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stephen.horsford@gmail.com wrote: > I am looking for an 8bit * 8 bit pipelined multiplier. http://justfuckinggoogleit.com/ Try "pipelined multiplier" and then e.g. the 3rd link: 8 bit x 8 bit Pipelined Multiplier in Verilog: http://www.doulos.com/knowhow/verilog_designers_guide/models/8bit_x_8bit_pipelined_multiplier/ > I hope what i've stated above makes sense. Does it makes sense to you? I assume this is a homework (the problem and the description of the solution looks too strange to be a real world problem), so please ask your instructor, if it doesn't makes sense. -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 111826
hikmetkoca schrieb: > thank for your answer, did you write a code for configuring the cam and > taking image data from the it?. > > Antti yazdi: > > hikmetkoca schrieb: > > > > > Hello, > > > > > > Is there anyone who interface the C3188A - 1/3" Digital Output Colour > > > Camera Module with an fpga. > > > I am waiting for your answers. > > > > > > Thanks > > > > there is one tool you need, it is called "soldering iron". > > > > Antti Mr hikmetkoca, if you want answer, then you must first ask something in such form that an answer can be given. I answered how to connect a the C3188A to an FPGA, the tool really is "soldering iron" if you have some specific questions or issues or problems then you should explain what problems you have. as a starter you could do 2 minutes google search and find http://suzaku-en.atmark-techno.com/dev/demos/esec2005-ccdcamera there is full FPGA project for the C3188A camera module, try that project first, if it doesnt work for you then you might be able to ask a more specific question about the problems you have with your camera. of course this means you have already managed the "solder iron" task of course. AnttiArticle: 111827
Thomas Entner wrote: > Personally, I am waiting for Cyclone III.... what about MAX III ? -jgArticle: 111828
"Jim Granville" <no.spam@designtools.maps.co.nz> schrieb im Newsbeitrag news:4554e533$1@clear.net.nz... > Thomas Entner wrote: >> Personally, I am waiting for Cyclone III.... > > what about MAX III ? > MAX III -> too small, S-III -> too expensive for our typical applications (however, the smallest S-III for a Cyclone-price would be a deal :-) But what I really wanted to say is that I am pretty euphoric about multi-processor support, if it really works well and gets compile-time down drastically. Hmm, will I have still time to post here? ThomasArticle: 111829
I was reading about the multi processor support in upcoming Quartus software and I wonder if another idea to increase synthesizing speed would be to use the FPGA itself to calculate routing etc. Maybe some tasks could take advantage of the high parallel capabilities of FPGAs. -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 111830
To do much useful in 500 lines of code and have that resource utilization as the output, my guess is that you are using a few IP cores which take up those resources. ---Matthew Hicks <ian.peikon@gmail.com> wrote in message news:1163181720.400625.238980@h48g2000cwc.googlegroups.com... > Hi, > > I've been working on an FPGA project for a month or so now and I have > finally finished the code. Before I began I calculated the amount of > BRAM and Distributed Ram that I had available and designed the code > accordingly. However after compilation I get the following results: > Number of Slices: 43734 out of 1200 3644% (*) > Number of Slice Flip Flops: 19047 out of 2400 793% (*) > Number of 4 input LUTs: 27654 out of 2400 1152% (*) > Number of IOs: 58 > Number of bonded IOBs: 53 out of 96 55% > Number of BRAMs: 528 out of 10 5280% (*) > Number of GCLKs: 2 out of 4 50% > > I don't really see how any of this is possible. I instantiated 5 > BRAM's. Where does it come up with 528? Additionally where do the > flipflops, slices, and LUT's come from? My code is only ~500 lines, I > don't even know how I coded for this much logic?!!! > > PLEASE HELP!! >Article: 111831
Stef wrote: > Anyone who had the same issue, or knows how to find/create the missing > components ? I have the exact same problem using the Webpack 8.2i. Another problem I had with the newer Webpack is that it can't fit a design into the Spartan 3 200 that Webpack 7.1i could (good thing I didn't throw away the old bit file). -- JecelArticle: 111832
Jecel wrote: > Stef wrote: > > Anyone who had the same issue, or knows how to find/create the missing > > components ? > > I have the exact same problem using the Webpack 8.2i. Oops - I should have searched further before posting this. Here is what Martin Schoeberl posted on the Open Cores list on August 17, 2006: "Some VHDL files are generated by the microcode assembler. See http://www.jopdesign.com/doc/build.pdf for further details on the design flow." -- JecelArticle: 111833
Most synthesis tools, when converting tri-states to muxes assume that the tri-state enables were mutually exclusive (otherwise it would not have worked with tri-states), which allows optimizing the select logic out of the mux, and using simpler and/or trees (implemented with LUTs in an FPGA, of course). I occasionally use this trick to optimize multiplexor circuits when I know the select lines are mutex, but the synthesis tool does not. I just code it as a 3-state bus, and let it do the conversion. Andy Al wrote: > Mike Treseler wrote: > > > > Sorry, I didn't read the whole question. > > Synthesis will convert tri-buff inferences to muxes. > > > > How these muxes look like? Is there any scheme they are arranged? I can > imagine it, but I need to understand how many resources that will > require. Do you suggest to try to implement it and then look at the rtl > view? Can I foresee some structure? > Thanks a lot > > Al > > -- > Alessandro Basili > CERN, PH/UGC > Hardware DesignerArticle: 111834
Matthias Alles wrote:
> I'm trying to implement an add-compare-select (ACS) unit in a Spartan3
> but I am not satisfied with the speed. The code looks like this:
What's the current speed ?
What would you like to achieve ?
> ...
> type sum_array is array(0 to 7) of signed(13 downto 0);
> signal state_reg : sum_array;
> ...
>
> process(clk, rst) is
>
> variable sum1, sum2, sum3, sum4 : sum_array;
>
> begin
> if rst = '1' then
> ....
> elsif clk'event and clk = '1' then
>
> ...
>
> sum1(0) := state_reg(a1) + gamma(a2);
> sum2(0) := state_reg(b1) + gamma(b2);
> sum3(0) := state_reg(c1) + gamma(c2);
> sum4(0) := state_reg(d1) + gamma(d2);
>
> state_reg(0) <= MIN4(sum1(0), sum2(0), sum3(0), sum4(0));
>
> ...
> end if; -- rst,clk
> end process;
>
> where a1, a2, ..., d2 are some constants. The problem with this code is
> that we access the newly calculated state_reg in the very next clock
> cycle (the constants can be for instance zero!). Hence pipelining is not
> possible. The Minimum search (MIN4) is done by doing 6 subtractions in
> parallel to avoid a two stage minimum search tree.
> I would like to boost the clock frequency of this architecture. Is there
> a way to further improve the description in VHDL? Or is it possible to
> do some hand optimisations?
Are the gamma constants ?
The only thing I see from a quick look is that you could "post-pone" part of
the minimum mux.
For now, you have a MUX4 between the 4 sums. You could just assign
state_reg_a to min2(sum1,sum2) and state_reg_b to min2(sum3,sum4). Then
register the output of your other comparaison (to know whick of _a or _b is the
good one), then do the mux the cycle after. And that mux can fit within the same
LUT as the one that does the addition.
I have no idea if it will be really that much faster (or faster at all) because
all you gain is a F5 mux and that gain could be couteracted by other factors ...
You can also take a faster speedgrade ;)
Sylvain
Article: 111835I am a newbie with this FPGA stuff, but I'm having to use a Stratix II design to develop some software until they can get me a chip that works. So please forgive me if I misuse terms or appear ignorant. I am! ;) In this design, we have memory images in .hex files that are picked up by the Quartus compiler and placed onto the Stratix board during the .sof file download. I can also download these images individually within the In-System Memory Content Editor. The problem that I'm seeing is that a location in one of the images is not what is in that .hex file. Is there a way to tear down the .sof file so that I can see if the problem is happening during the compiler process or if it is happening during or after the download? We are using Quartus II (5.0 SP2 or 6.0 SP1) on Windows XP Home Edition (2002 SP2) within a Parallels (Build 1970) VM on an iMac 2GHz Intel Core Duo (OSX 10.4.8). The memory images and FPGA project files are stored in OSX and accessed over Parallels sharing with a mapped network drive. However, I have the same behavior if I move the entire folder over to the WinXP drive. Has anyone else seen this type of problem? DaRArticle: 111836
Hi all,
I have two problem of SystemVerilog Assertion. About property
implication and sequence.
1. Is
//--------
property rule (a,b,c);
@(posedge clk) a |-> b ##1 c;
endproperty
//--------
equal to
//--------
sequence rule;
@(posedge clk) (a&&b) ##1 c;
endsequence
//--------
2. I was told implication can be same or next cycle. Is same cycle
equal to "|->"? And is next cycle equal to "|=>"?
Thanks a lot!
Best regards,
Davy
Article: 111837Thanks Ray. I tried that, generating 2 seperate edf files for the top and lower-level module. And I put // synthesis syn_black_box on the stub module in the modified top-level design. But when I put both edf files into ise, it complains cannot have 2 source files. I must have missed out something, probable due to my limited Verilog. Just to confirm. Is it true that, no matter it's hdl or edf top-level, we can have hierarchical structure in the lower levels described in either hdl or edf, right? I mean in ISE. Ray Andraka wrote: > kanglc@gmail.com wrote: > > > Hi, > > > > Is there a way to use partition for top-level edif flow? (Synthesis: > > Synplify_premier) > > > > Since there is only one edif design file, how do we set partition for > > lower level module? > > > > Thanks! > > > > You can synthesize in parts leaving your lower module(s) as black boxes > in the top level. Just leave the source for the lower module that you > want a separate edif for out of the file list in the top level project, > and then create another project with that module as the top level. Make > sure you disable i/o insertion and clock buffer insertion for your lower > level module, otherwise xilinx will throw an error when it tries to > stitch the edifs together.Article: 111838
Hi Frank, There's not much in the CAD tool that could be easily sped up on an FPGA. CAD tools have huge working sets (active memory) and spend a lot of their time jumping around through that memory. Many key algorithms are manipulating graphs and this sort of stuff isn't easy to parallelize. Spliting it into multiple threads for a CPU is tough enough -- going massively parallel in an FPGA (or heck, a GPU -- anyone read up on the G8800?) is much tougher. Plus think of the maintenance nightmare... each new alogrithm or tweak becomes a hardware change! - PaulArticle: 111839
Try specifying only the top level edif file and include a macro search path for the translate stage to allow the tool to find the other edifs. This is how the .ngo files are included for some Xilinx cores; perhaps it's identical with the edif-only flow. kanglc@gmail.com wrote: > Thanks Ray. > > I tried that, generating 2 seperate edf files for the top and > lower-level module. And I put // synthesis syn_black_box on the stub > module in the modified top-level design. But when I put both edf files > into ise, it complains cannot have 2 source files. I must have missed > out something, probable due to my limited Verilog. > > Just to confirm. Is it true that, no matter it's hdl or edf top-level, > we can have hierarchical structure in the lower levels described in > either hdl or edf, right? I mean in ISE. > > Ray Andraka wrote: >> kanglc@gmail.com wrote: >> >>> Hi, >>> >>> Is there a way to use partition for top-level edif flow? (Synthesis: >>> Synplify_premier) >>> >>> Since there is only one edif design file, how do we set partition for >>> lower level module? >>> >>> Thanks! >>> >> You can synthesize in parts leaving your lower module(s) as black boxes >> in the top level. Just leave the source for the lower module that you >> want a separate edif for out of the file list in the top level project, >> and then create another project with that module as the top level. Make >> sure you disable i/o insertion and clock buffer insertion for your lower >> level module, otherwise xilinx will throw an error when it tries to >> stitch the edifs together.Article: 111840
I just used Xilinx Chipscope with EDK for the first time and it is
great!
Just drap and drop chipscope_icon and chipscope_plb_iba in XPS and
connect them together.
Then recompile and you have a non-intrusive plb bus analyzer.
One problem I had was Chipscope didn't want to work with the evaluation
version of ISE.
In the file chipscope_plb_iba_v1_01_a/data/chipscope_plb_iba_v2_1_0.tcl
I had to change:
exec xst -ifn $xst_scr_filename
to:
exec xst -ifn $xst_scr_filename 2> null
so the warning about the evaluation version expiring doesn't cause the
compile to fail.
I also had a problem with my Zone Alarm firewall because Chipscope sets
up a client/server connection so it can be used remotely.
EDK 8.1.02, ISE 8.1.03, Chipscope 8.1.03
Alan Nishioka
Article: 111841Hello and thanks for your cooperation. Sorry, since I copied this script from another place, during the copy, the last question was not pasted correctly. Anyhow, my two questions were as follows: 1- As I have seen in different vendors pages, most of the SERDES devices are placed after a protocol device. For transmitting SDH telecombus data is it necessary to implement a protocol on it or not. (Why protocol specification is required?). 2- Has anyone seen any SERDES chip which supports the mentioned rates (19.44 MHz and 77.76MHz) on its parallel side or not? John_H wrote: > Since STM4 is only 622 Mb/s and you're posting on the FPGA board, you can > apply a SerDes from just about any FPGA to get to your rate Many families > will also support 622 Mb/s in the standard I/Os. The STM-4 rate is a target > for most FPGA vendors so they'll shoot at this as an achievable maximum on > standard I/O and a minimum on the SerDes as well. > First of all, SERDES is not available in any FPGA, and for example in Xilinx FPGA's, it is available in VIRTEX-II pro and the VIRTEX-4 and VIRTEX-5 familes. do you know any low price small FPGA which supports the SERDES feature as we want. (In our current design the telecombuses from the tributary cards are directly connected from the tributary cards to the FPGA on the OIU card). Meanwhile, if we don't want to have SERDES, and just use the ordinary I/O's for communication, we would need a (233.28MHz=19.44Mhz*12) 233.28 MHz clock in each of the E1 tributary cards and a 933.12 MHz clock on the data card to transmit the 12-bit telecombuses serially. Meanwhile we should also transmit the 233.28 MHz and 933.12MHz clock on the backplane. Am I right? have you any other idea about this? > The SerDes are often used after the protocol layer but isn't needed in an > application with protocol. The FPGAs have this functionality as a more > generic function than you might perceive. > > Two cautions for your application: > > First, the clocks must be supplies separately for your links; the FPGA logic > doesn't deal well with plesiochronous signals alone though some SerDes > blocks might support some form of clock recovery. If you have the local > clock available and can communicate that clock with the 622 Mb/s data, you > should be in good shape. > > Second, these signals can *not* be used for timing. The jitter requirements > for the SDH signals are sincerely more strict that what you should expect > from the FPGAs. As with most SDH designs, you should only introduce signals > onto the line that are within the ITU-T jitter limits. > They won't surely be used for timing. > As long as all your data shuffling is internal to your system and you're > retimed for all your transmitters with the appropriate low-jitter circuitry, > today's FPGAs can really carry you well. > But we should be sure that neither of theses 12 bits are shuffled. Because the SDH chip needs these 12 signals in its correct timing position. > Oh - and did you have two questions? > > - John_H > > > "Arash" <arash.majd@gmail.com> wrote in message > news:1163175421.380944.121850@h48g2000cwc.googlegroups.com... > > Hello > > I have got a problem in SERDES chip selection that I would be grateful > > if someone helps me in this regard. First, I explain the system that we > > have. We want to design an STM-4 SDH system which has 5 tributary > > cards and 1 optical STM-4 line card.The tributary cards are of two > > types : E1 card and data card. The E1 tributary card which contains an > > SDH E1 mapper, has a 12-pin telecombus in 19.44 MHz rate in each of > > its transmit and receive directions (each card has 24 pins in > > backplane). but the Data tributary card which contains an EoS device on > > itself, has a 12-pin telecombus in 77.76MHz rate in each of the > > transmit and receive directions.The pslot of the optical line card is > > fixed but each of the tributary cards can sit in any position of the 5 > > tributary slots. to reduce the number of the pins on the backplane we > > want to serialize the telecombuses between the optical line card and > > the tributary cards. Since we do not know which of the tributary cards > > is inserted in in each slot we should select a SERDES which can > > serialize the data from both of the rates of 19.44 and 77.76 MHz (But > > during my searches in different vendors I haven't been able to find > > such a chip). I have got 2 questions. > > 1- As I have seen in different vendors pages, most of the SERDES > > devices are placed after a protocol device. for transmitting SDH > >Article: 111842
Thomas Entner wrote: > > But what I really wanted to say is that I am pretty euphoric about > multi-processor support, if it really works well and gets compile-time > down drastically. Hmm, will I have still time to post here? In 6.1, only a few parts of the fitter have been paralellized - think of about 15% performance increase on a quad-core. However, once the timing engines have been paralellized in 7.0 or 7.1, expect a more noticeable speedup. On the other hand, better to start saving a bit of time now and getting better over the next months than to make you wait for the whole thing to be fully paralellized for another year. Best regards, BenArticle: 111843
Yes, I am using IP cores to generate the blockrams, but I only instantiate 5 of them at 8x16 (hardly the 520 that ISE claims). Matthew Hicks wrote: > To do much useful in 500 lines of code and have that resource utilization as > the output, my guess is that you are using a few IP cores which take up > those resources. > > > ---Matthew Hicks > > > <ian.peikon@gmail.com> wrote in message > news:1163181720.400625.238980@h48g2000cwc.googlegroups.com... > > Hi, > > > > I've been working on an FPGA project for a month or so now and I have > > finally finished the code. Before I began I calculated the amount of > > BRAM and Distributed Ram that I had available and designed the code > > accordingly. However after compilation I get the following results: > > Number of Slices: 43734 out of 1200 3644% (*) > > Number of Slice Flip Flops: 19047 out of 2400 793% (*) > > Number of 4 input LUTs: 27654 out of 2400 1152% (*) > > Number of IOs: 58 > > Number of bonded IOBs: 53 out of 96 55% > > Number of BRAMs: 528 out of 10 5280% (*) > > Number of GCLKs: 2 out of 4 50% > > > > I don't really see how any of this is possible. I instantiated 5 > > BRAM's. Where does it come up with 528? Additionally where do the > > flipflops, slices, and LUT's come from? My code is only ~500 lines, I > > don't even know how I coded for this much logic?!!! > > > > PLEASE HELP!! > >Article: 111844
"Ben Twijnstra" <btwijnstra@gmail.com> schrieb im Newsbeitrag news:cc60$4555781c$d52e23a9$13983@news.chello.nl... > Thomas Entner wrote: >> >> But what I really wanted to say is that I am pretty euphoric about >> multi-processor support, if it really works well and gets compile-time >> down drastically. Hmm, will I have still time to post here? > > In 6.1, only a few parts of the fitter have been paralellized - think of > about 15% performance increase on a quad-core. Would have been too good to be true... > However, once the timing > engines have been paralellized in 7.0 or 7.1, expect a more noticeable > speedup. > > On the other hand, better to start saving a bit of time now and getting > better over the next months than to make you wait for the whole thing to > be > fully paralellized for another year. > Agreed. ThomasArticle: 111845
On 10 Nov 2006 18:36:25 -0800, "Davy" <zhushenli@gmail.com> wrote: >Hi all, > >I have two problem of SystemVerilog Assertion. About property >implication and sequence. > >1. Is >//-------- >property rule (a,b,c); > @(posedge clk) a |-> b ##1 c; >endproperty >//-------- > >equal to >//-------- >sequence rule; > @(posedge clk) (a&&b) ##1 c; >endsequence >//-------- No. See the recent thread "implication operators in sva" on comp.lang.verilog. Also, you have parameterised the property but not the sequence. >2. I was told implication can be same or next cycle. Is same cycle >equal to "|->"? And is next cycle equal to "|=>"? Yes. See my post in the thread I just mentioned. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 111846
Thanks @ All!Article: 111847
Personnaly, I'm also waiting for Cyclone III. Looks promising. By the way, I've been told that MAX III is also on the way ... and that NIOS II will be supported :o) ---------------------------------------------- Posted with NewsLeecher v3.5 Beta 5 * http://www.newsleecher.com/?usenetArticle: 111848
> However, once the timing > engines have been paralellized in 7.0 or 7.1, expect a more noticeable > speedup. A small correction to Ben's post: Portions of the timing engine are parallized in this release. I should also point out that in addition to parallel compile, there have been other improvements made for compile time. We're always pushing on the fitter to reduce compile by general coding & algorithm improvements, and by being more intelligent about just how much effort we spend on your design based on how tight your timing & fitting requirements are. Regards, Paul Leventis Altera Corp.Article: 111849
Hi I wonder if the MPMC2 system can work on Virtex-5, the last release of MPMC2 does generate a UCF file that matches Xilinx ML-501 board but I have so far failed with all attempt to get MPMC2 generated system to work on ML501 Antti
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