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Hi Molecule, You need to ask a more specific question and show you have done some reading around the particular area to increase the likelihood of useful info/advice/pointers from the experts in this group. What are the functions provided by the MAC layer for 802.11? What does DCF stand for? Regards Andrew molecularelectronics@googlegroups.com wrote: > hi, > > i am doing the following project. can any one help me for VHDL coding > for simulation on altium designer? or at least guid me with ideas to > implement software without any errors. > > > > VHDL simulation and Implementation of CSMA and DCF of Wireless LAN > > Learn about the wireless LAN technique and system design, simulation > and verification techniques for digital communication systems. Parts of > the Medium Access Control (MAC) layer of the IEEE 802.11 Wireless LAN > standard will be simulated and implemented in VHDL. > > > hoping a positive reply..from you all experts in this area. > > > thanks and regards > vasuArticle: 111726
Hi, Hope everyone is doing fine. I'm trying to estimate static power consumption of my system in higher temperature. I'm using XPower and there is a field in XPower to set Ambient Temperature. However when I set Ambient Temperature to a higher temperature, it doesn't change Quiescent power and just changes the Junction temperature and Case temperature. Do you know how I can get static power consumption in different temperatures using XPower? In datasheet there are two fields for Quiescent current. One of them is typical current which basically is the same as XPower report. I've assumed that typical current is the current in 25 degrees. However there is also a max current which I'm not sure if it is quiescent current in 85 degrees or not. I'd be very happy to know your opinion on this one, Thanks, AmirArticle: 111727
Virtex5 datasheet specifies typical static current draw at 85 deg C now, but I guess if you were using V5 you wouldn't be asking the question. Xesium wrote: > Hi, > Hope everyone is doing fine. > I'm trying to estimate static power consumption of my system in higher > temperature. I'm using XPower and there is a field in XPower to set > Ambient Temperature. However when I set Ambient Temperature to a higher > temperature, it doesn't change Quiescent power and just changes the > Junction temperature and Case temperature. Do you know how I can get > static power consumption in different temperatures using XPower? > In datasheet there are two fields for Quiescent current. One of them is > typical current which basically is the same as XPower report. I've > assumed that typical current is the current in 25 degrees. However > there is also a max current which I'm not sure if it is quiescent > current in 85 degrees or not. > > I'd be very happy to know your opinion on this one, > > Thanks, > > AmirArticle: 111728
Hi, dears:
I am using a GE MAC with atlantic interface. I need a asyn fifo with
atlantic to short my time. Anyone have it? thank you!
Jude Wu
Article: 111729I have a JED file for an old PAL device and I have to put this design in a FPGA. Is there a tool that can read the JED file and translate it to any usable language (VHDL prefered)...Article: 111730
backhus wrote: > Hi Davy, > I`m more familiar with FPGA design than ASIC design, but I think for > both targets latches should be avoided. They are not sensitive to clock > edges, and data changes while they are enabled pass the latch causing > trouble in the circuit that follows. > > I'm not sure if there are still designs which have to use latches > instead of FFs for some reason. But to my knowledge Clock gating for > latches is a design technique from way back when, when there were no > real FFs available and the clock frequencies were about 1 MHz. > > From the groups you are posting to, I guess that you are using NC-Sim, > dont'you? [snip] Hi backhus, Thanks for the help! Yes, I use NC-Sim. My knowledge of gated clock is from a SNUG paper "How to successfully use gated clocking in an ASIC design". > If you say that you wonder about the seqence of changes (Clock > before/after Data or vice versa) what time scale are you talking about? Do you think timescale is a relative matter (corresponding to delay)? > Do you change Data within the setup/hold time of your FFs? This may lead > to strange results in your simulator. I forbidden all the delay and timing check (i.e. setup/hold timeing check of FFs). Will it lead to strange results? > Besides simulation, have you made a static timing analysis for your design? I want to do functional simulation of gate level and don't care delay(and they are not accurate). > > Have a nice simulation > Eilert > > > Davy schrieb: > > Hi backhus > > > > Thanks a lot! > > > > I heard latch is only used in gated clock in ASIC design. Is it right? > > > > I think it must be gated clock cause the problem. I see the waveform. > > And I found though data and clock change at the same time i.e at the > > same delta time (I forbidden timing delay at global scope), clock > > change is follow the data change. > > > > As we all know data change must follow the clock change. So I guess > > there must be gated clock cause some logic sequence chaos in simulator. > > > > Best regards, > > Davy > > > > backhus wrote: > >> Hi Davy, > >> When you say netlist simulation do you mean a timing simulation? > >> And when you say RTL level simulation Do you mean a behavioral simulation? > >> If my assumtions are correct think about the following: > >> > >> If you are using gated clocks, the gate has no delay in behavioral > >> simulation, so your circuit works as expected. But in Timing simulation > >> the gate and the associated routing creates a delay to the clock signal > >> of the connected registers. The effects depend on the desired clock > >> speed, and may be significant as you already observed. > >> > >> To overcome this you should consider using Clock Enable inputs rather > >> than gating the critical clock net. > >> > >> And, yes you guessed right. A gated clock doesn't behave like the > >> original clock because it's a totally different signal. > >> You can compare it to trains. One on rails (clock net), the other not > >> (normal routing ressources). Guess wich one misses it's schedule at the > >> next station. :-) > >> > >> Have a nice simulation > >> Eilert > >> > >> Davy schrieb: > >>> Hi all, > >>> > >>> When I simulate netlist with gated clock, I found the output is very > >>> different with what I see in RTL level. > >>> > >>> So I add tfile in NCSim to forbidden the delay and timing check in > >>> global scope (Because the design have no memory like RAM/FIFO). > >>> > >>> The netlist waveform seems to be better, but there are also some > >>> trivial differences between RTL and netlist waveforms (e.g. some signal > >>> have one clock advance and some signal have one clock delay). I guess > >>> gated clock does not behavior like original clock and introduce race. > >>> > >>> But how to understand gated clock simulation behavior? Any > >>> comments/reference will be appreciated! > >>> Thanks! > >>> > >>> Best regards, > >>> Davy > >>> > >Article: 111731
sharp@cadence.com wrote: > Davy wrote: > > > > I guess > > gated clock does not behavior like original clock and introduce race. > > A gated clock will be delayed relative to the original clock, by the > delay of the gate used to gate it. In a timing simulation, this will > be a positive time delay. In a zero-delay simulation, this will be > more like a delta cycle delay. In either case, this can introduce a > race condition. > > If you have flip-flops A and B, where A is clocked by the original > clock, and B is clocked by the gated clock, and the input of B is > driven by A, then you have a potential race condition. The output of A > can change before B is clocked by the delayed gated clock. It only > works if the propagation delay from the clock through A to the input of > B is greater than the propagation delay from the clock to the gated > clock (actually, it has to exceed it by the hold time of B). This is > true even in zero-delay, except that the delays are essentially delta > cycles (and Verilog makes no guarantees about delta cycle ordering, so > you cannot rely on anything here). [snip] Yes, I agree. > > This kind of problem is why some design methodologies forbid gated > clocks, and require the use of clock enabled flip-flops instead. Do you mean both ASIC and FPGA have methodology forbid gated clocks (I know that FPGA forbid gated clock and use clock enabled D-FF). Thanks!Article: 111732
Hello, If you use a Nios2 processor then you can access the EPCS pins. Has anybody been able to do this without using the Nios2 processor? I found a module called tornado_epcs_controller_atom and I think it should be possible to do it using this module. best regards, KarelArticle: 111733
Mark McDougall wrote: > oopere wrote: > > > Of course, there is the possibility that I am missing some point. Any > > hint? > > Did it meet timing? > Were your timing constraints actually correct? > Is it a synchronous design? > Are you using gated clocks? > > Could be a lot of things before you point the finger at Quartus... Sure, there may be problems in my design. However, the main point of my post is that the circuit behaviour is different in the following cases: - State a). Original design - State b). Originial design + output pin added + compiled + output pin removed + compiled And I have observed this kind of behavior happening twice, in different designs. One aprox. one year ago and the other yesterday. If I am the only one who has experienced this then obviously I am doing something wrong, somewhere. But where?Article: 111734
Mark McDougall wrote: > oopere wrote: > > > Of course, there is the possibility that I am missing some point. Any > > hint? > > Did it meet timing? > Were your timing constraints actually correct? > Is it a synchronous design? > Are you using gated clocks? > > Could be a lot of things before you point the finger at Quartus... Sure, there may be problems in my design. However, the main point of my post is that the circuit behaviour is different in the following cases: - State a). Original design - State b). Originial design + output pin added + compiled + output pin removed + compiled And I have observed this kind of behavior happening twice, in different designs. One aprox. one year ago and the other yesterday. If I am the only one who has experienced this then obviously I am doing something wrong, somewhere. But where?Article: 111735
Thank you guys for the help. It did help me a little further. I am able to generate a system.bit and download.bit file now. However, I get no response from any of the µblazes. One is connected to the uart and external memory, the other only has access to its local bram memory. Is it required to write separate linker script files for each microblaze? Regards, Gerd PS: thank you marada for your time, you helped me a lot!Article: 111736
Hi, Slurp, hi Backhus, Thanks for your advise I've found the problem: i feed the input singal through the Agilent Soft Touch Cable(E5404A), which contains a RC-Network inside. And that's why the output by 1MHz worse then by 150MHz, because of the character of this RC. hmmm..... Regards, Cheng backhus schrieb: > hi, > as Slurp already mentioned, the reset seems to be missing, > but besides that.. > > What about your Clock signal? > Are there Overshots or Ground Bouncing at your FPGA Input? > Depending on your measuring setup and the sensitivity of your LA-Pods > these might be invisible to your LA, but valid for the Clock input of > your FPGA. Since only the clock edge is of importance here and not the > frequency it doesn't matter if you use 150 MHz or 1 MHz when you have > this problem. It only depends on the rise time and drive strength of > your Clock generator and the associated wire(transmission line) to your > FPGA Input. > > You need some good oszillscope to analyse this, and it may also happen > that the problem vanishes when the oszilloscope is connected to your > system. In that case the problem is there but can't be seen due to the > influence of your probe (input impedance) which changes the behavior of > your transmission line. > > have a nice measuring > EilertArticle: 111737
"oopere" <oopere@netscape.net> wrote in message news:1163062587.507437.291270@h48g2000cwc.googlegroups.com... > > If I am the only one who has experienced this then obviously I am doing > something wrong, somewhere. But where? If it's a timing problem which is affected by the temperature of the circuit, then getting it working by one method might mean that the whole thing then warms up to the point where it then continues to work in the old configuration. I'm afraid I didn't really understand your description of the design yesterday, but I expect that you make sure you're rock solid on setup times (async inputs into multiple FF's) and timing constraints, then it will all work much more consistently. If you have signals in multiple clock domains, which I suspect you do, then you probably need to treat them a lot more carefully than just XORing them together. You're certainly not the only one to experience bizarrely inconsistent problems which are apparently related to something they later turn-out not to be related to. If it's only working by luck in the first place, I wouldn't waste time by trying to second-guess precisely what causes that luck to run out. WillArticle: 111738
Hi NigelE, Is AVM IEEE 1800 compatible? Thanks! Thanks! Davy NigelE wrote: > Davy wrote: > > Hi NigelE, > > > > Thanks a lot! I mis-understand virtual interface. > > > > Is there any web seminar or online video talk about AVM? That I want to > > understand AVM more clearly. > > > > Best regards, > > Davy > > > > Hi Davy > > Try a look at > > http://www.mentor.com/products/fv/events/ > > You'll find listed in the online events, our recent 'Hitchhikers Guide > to Verification' seminar that covers AVM and other SV verification > topics. > > It's split into 5 sessions so you don't need to watch it all at once ;) > > Best regards > > - NigelArticle: 111739
Hello, I work as Design Engineer at Bull SAS in France (Server Design and Development). I saw a webcase on the web in which someone try to provide some guidance concerning LVDS signals. I am not sure to have understood all your answers, so please let me ask the following question : I am currently working on a design based on the spartan XC3S1000. Can it be used to drive LVDS clocks ? (LVDS clock's frenquency is 100 Mhz). If yes, what output buffers should we use ? (Is there an "OBUFGDS" in the XC3S1000 ?). What will be the maximum jitter between these 100Mhz-LVDS clocks ? Thanks a lot for your answers, JulienArticle: 111740
well yes. Basically I'm looking at virtex 2 or virtex 4. But good to know that. Thanks. I'll check virtex 5 data sheet also. Amir Andrew FPGA wrote: > Virtex5 datasheet specifies typical static current draw at 85 deg C > now, but I guess if you were using V5 you wouldn't be asking the > question. > > Xesium wrote: > > Hi, > > Hope everyone is doing fine. > > I'm trying to estimate static power consumption of my system in higher > > temperature. I'm using XPower and there is a field in XPower to set > > Ambient Temperature. However when I set Ambient Temperature to a higher > > temperature, it doesn't change Quiescent power and just changes the > > Junction temperature and Case temperature. Do you know how I can get > > static power consumption in different temperatures using XPower? > > In datasheet there are two fields for Quiescent current. One of them is > > typical current which basically is the same as XPower report. I've > > assumed that typical current is the current in 25 degrees. However > > there is also a max current which I'm not sure if it is quiescent > > current in 85 degrees or not. > > > > I'd be very happy to know your opinion on this one, > > > > Thanks, > > > > AmirArticle: 111741
Hi experts,
my design is a rather simple demo for a spartan3E starter kit and uses
a picoblaze softcore and a grlib CAN2B core (can_mod).
I can't get it running...
I can read a good CR register value in reset mode (CR & A1 == 21 it is
a beginning...) but the other registers are not correct...
With my app, I get y N N N N...
I am a software guy, new to vhdl and design ... could someone
investigate my code ...
code and design is based on s3esk_startup.vhd (xilinx initial demo
shipped with kit)
regards,
vhdl
-=-=-=
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity cantest is
Port ( led : out std_logic_vector(7 downto 0);
strataflash_oe : out std_logic;
strataflash_ce : out std_logic;
strataflash_we : out std_logic;
switch : in std_logic_vector(3 downto 0);
lcd_d : inout std_logic_vector(7 downto 4);
lcd_rs : out std_logic;
lcd_rw : out std_logic;
lcd_e : out std_logic;
clk : in std_logic;
rx_pin : in std_logic;
tx_pin : out std_logic
);
end cantest;
--
------------------------------------------------------------------------------------
--
-- Start of test architecture
--
architecture Behavioral of cantest is
--
--gaisler grlib CAN2B
---------------------
component can_mod
generic ( memtech : integer );
port(
reset : in std_logic;
clk : in std_logic;
cs : in std_logic;
we : in std_logic;
addr : in std_logic_vector(7 downto 0);
data_in : in std_logic_vector(7 downto 0);
data_out: out std_logic_vector(7 downto 0);
irq : out std_logic;
rxi : in std_logic;
txo : out std_logic
);
end component;
--
-- declaration of KCPSM3
--
component kcpsm3
Port ( address : out std_logic_vector(9 downto 0);
instruction : in std_logic_vector(17 downto 0);
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
out_port : out std_logic_vector(7 downto 0);
read_strobe : out std_logic;
in_port : in std_logic_vector(7 downto 0);
interrupt : in std_logic;
interrupt_ack : out std_logic;
reset : in std_logic;
clk : in std_logic);
end component;
--
-- declaration of program ROM
--
component control
Port ( address : in std_logic_vector(9 downto 0);
instruction : out std_logic_vector(17 downto 0);
proc_reset : out std_logic; --JTAG
Loader version
clk : in std_logic);
end component;
--
------------------------------------------------------------------------------------
--
-- Signals used to connect KCPSM3 to program ROM and I/O logic
--
signal address : std_logic_vector(9 downto 0);
signal instruction : std_logic_vector(17 downto 0);
signal port_id : std_logic_vector(7 downto 0);
signal out_port : std_logic_vector(7 downto 0);
signal in_port : std_logic_vector(7 downto 0);
signal write_strobe : std_logic;
signal read_strobe : std_logic;
signal interrupt : std_logic :='0';
signal interrupt_ack : std_logic;
signal kcpsm3_reset : std_logic;
--
--
-- Signals for LCD operation
--
-- Tri-state output requires internal signals
-- 'lcd_drive' is used to differentiate between LCD and StrataFLASH
communications
-- which share the same data bits.
--
signal lcd_rw_control : std_logic;
signal lcd_output_data : std_logic_vector(7 downto 4);
signal lcd_drive : std_logic;
--
--
--signal for CAN2B
signal addr : std_logic_vector(7 downto 0);
signal data_out : std_logic_vector(7 downto 0);
signal data_in : std_logic_vector(7 downto 0);
signal can_cs : std_logic;
signal can_we : std_logic;
signal irq : std_logic;
------------------------------------------------------------------------------------------------------------------------------------------------------------------------
--
-- Start of circuit description
--
begin
--StrataFLASH must be disabled to prevent it conflicting with the LCD
display
--
strataflash_oe <= '1';
strataflash_ce <= '1';
strataflash_we <= '1';
can: can_mod
generic map (memtech => 0) --generic ram
port map (
reset => kcpsm3_reset,
addr => addr,
data_in => data_in,
data_out => data_out,
cs => can_cs,
we => can_we,
clk => clk ,
rxi => rx_pin,
txo => tx_pin,
irq => irq);
processor: kcpsm3
port map( address => address,
instruction => instruction,
port_id => port_id,
write_strobe => write_strobe,
out_port => out_port,
read_strobe => read_strobe,
in_port => in_port,
interrupt => interrupt,
interrupt_ack => interrupt_ack,
reset => kcpsm3_reset,
clk => clk);
control_rom: control
port map( address => address,
instruction => instruction,
proc_reset => kcpsm3_reset, --JTAG
Loader version
clk => clk);
-- The inputs connect via a pipelined multiplexer
--
input_ports: process(clk)
begin
if clk'event and clk='1' then
if read_strobe='1' then
case port_id(7 downto 6) is
--read switch data
when "00" =>
in_port <= "0000" & switch;
-- read LCD data at address 10xx xxxx
when "10" =>
in_port <= lcd_d & "0000";
-- read can data at address 11xx aaaa
when "11" =>
in_port <= data_out;
-- Don't care used for all other addresses to ensure minimum
logic implementation
when others => in_port <= "XXXXXXXX";
end case;
end if;
end if;
end process input_ports;
-- adding the output registers to the processor
output_ports: process(clk)
begin
if clk'event and clk='1' then
if write_strobe='1' then
case port_id(7 downto 6) is
-- Write to LEDs at address 80 hex.
when "10" =>
led <= out_port;
can_we <='0';
-- LCD data output and controls at address 40 hex.
when "01" =>
lcd_output_data <= out_port(7 downto 4);
lcd_drive <= out_port(3);
lcd_rs <= out_port(2);
lcd_rw_control <= out_port(1);
lcd_e <= out_port(0);
can_we <= '0';
-- CANB data
when "11" =>
can_we <= '1';
data_in <= out_port;
when others =>
can_we <= '0';
end case;
end if;
end if;
end process output_ports;
--can addr interface 32 registers
addr(7 downto 0) <= "00" & port_id(5 downto 0);
can_cs <= '1';
--
----------------------------------------------------------------------------------------------------------------------------------
-- LCD interface
----------------------------------------------------------------------------------------------------------------------------------
--
-- The 4-bit data port is bidirectional.
-- lcd_rw is '1' for read and '0' for write
-- lcd_drive is like a master enable signal which prevents either the
-- FPGA outputs or the LCD display driving the data lines.
--
--Control of read and write signal
lcd_rw <= lcd_rw_control and lcd_drive;
--use read/write control to enable output buffers.
lcd_d <= lcd_output_data when (lcd_rw_control='0' and lcd_drive='1')
else "ZZZZ";
end Behavioral;
control.psm
-=-=-=-=-=-=
;CAN2B registers
CONSTANT CR, C0
...
CONSTANT CDR, DF
;
CONSTANT LED_port, 80 ;8 simple LEDs
;
CONSTANT switch_port, 00 ;Read switches
and press buttons
;
;LCD interface ports
;
;The master enable signal is not used by the LCD
display itself
;but may be required to confirm that LCD
communication is active.
;This is required on the Spartan-3E Starter Kit if
the StrataFLASH
;is used because it shares the same data pins and
conflicts must be avoided.
;
CONSTANT LCD_output_port, 40 ;LCD character
module output data and control
...
CONSTANT ISR_preserve_s0, 01 ;Preserve s0
contents during ISR
CONSTANT count, 04
;
;
...
CONSTANT character_a, 61
...
CONSTANT character_BS, 08 ;Back Space
command character
;
;
;
;
;
;**************************************************************************************
;Initialise the system
;**************************************************************************************
;
cold_start: CALL LCD_reset ;initialise LCD
display
ENABLE INTERRUPT
;
load s0, 41
store s0, count
load s0,00
output s0, LED_port
;**************************************************************************************
;Main program
;**************************************************************************************
main_loop: LOAD s5, 10 ;Line 1 position 0
CALL LCD_cursor
CALL disp_msg
CALL delay_1s
LOAD s5, 20 ;Line 2 position 0
CALL LCD_cursor
call test_can1
jump main_loop
;*****************************
;END MAIN LOOP
;*****************************
test_can1: ;enter reset mode
load sa, 01
output sa, CR
wait: input sa,CR
and sa, 01
compare sa, 01
jump nz, wait
INPUT sa, CR
AND sa, A1
compare sa, 21
call Z, disp_ok
compare sa, 21
call NZ, disp_nok
INPUT sa, CMR
compare sa, FF
call Z, disp_ok
compare sa, FF
call NZ, disp_nok
INPUT sa, SR
compare sa, 0C
call Z, disp_ok
compare sa, 0C
call NZ, disp_nok
INPUT sa, IR
compare sa, E0
call Z, disp_ok
compare sa, E0
call NZ, disp_nok
INPUT sa, CDR
compare sa, 00
call Z, disp_ok
compare sa, 00
call NZ, disp_nok
RETURN
test_can2: ;nok...
load sa, 01
OUTPUT sa, CR
call delay_1ms
LOAD sa, 00
OUTPUT sa, CDR
LOAD sa, 81
OUTPUT sa, BTR0
LOAD sa, 25
OUTPUT s0, BTR1
LOAD sa, 15
OUTPUT s0, ACR
LOAD sa, 01
OUTPUT sa, AMR
load sa, 00
OUTPUT sa, CR
call delay_1ms
load sa,3E
OUTPUT sa, CR
LOAD sa, A3
OUTPUT s0, TXID1
LOAD sa, 83
OUTPUT sa, TXID2
LOAD sa, 11
OUTPUT sa, TX1
LOAD sa, 22
OUTPUT sa, TX2
LOAD sa, 33
OUTPUT s0, TX3
LOAD sa, 44
OUTPUT sa, TX4
send: LOAD sa, 01
OUTPUT sa, CMR
CALL delay_1ms
;jump send
RETURN
;**************************************************************************************
;LCD text messages
;**************************************************************************************
...
;
;
;
;
;**************************************************************************************
;Software delay routines
;**************************************************************************************
;
...
;**************************************************************************************
;LCD Character Module Routines
;**************************************************************************************
...
;**************************************************************************************
;Interrupt Vector
;**************************************************************************************
;
ADDRESS 3FF
JUMP ISR
;
;
Article: 111742Ray Andraka <ray@andraka.com> writes: > Martin Thompson wrote: > > Ray Andraka <ray@andraka.com> writes: > > > I still maintain that Xilinx should provide us with a useful wrapper > > though, rather than us all having to do our own :-) > > > > I agree, however with the caveat that it may still not fit all > users. This is always true :-) > Mine, for example accepts an unconstrained integer array > generic for initialization values. It puts the contents of that N > element array into the first N locations of the RAM and zero fills the > rest. Since the width can be greater than the 32 bits represented by > VHDL integers, I have a second integer array generic for separately > initializing the top half of an upto 63 bit wide composite memory. That's useful! > The wrapper instantiates RAMB16s with the depths determined by the > number of address bits on each port, and then puts in as many RAMB16s > as are required to accommodate the widths of the data ports. The > entity for my V4 wrapper is: > > entity dual_port_ram is > generic( > SIM_COLLISION_CHECK : STRING := "NONE"; > DO_reg: integer:=0; > allow_pbits: integer:=1; > reset_data: integer:= 0; --not usable with do_reg=1 > RAM_data: int_array:=(0,0); --initial data > RAM_data_hi: int_array:=(0,0)); --initial data > > port( > CLKA: in std_logic; > CLKB: in std_logic; > SSRA: in std_logic; > SSRB: in std_logic; > WEA : in std_logic; > WEB : in std_logic; > DIA : in std_logic_vector; > DIB : in std_logic_vector; > DOA : out std_logic_vector; > DOB : out std_logic_vector; > ADDRA : in std_logic_vector; > ADDRB : in std_logic_vector ); > > end dual_port_ram; And presumably that works with more than just V-4, and also on other brands? I like the idea of using unconstraing vectors on the ports - I got in a habit of generic-ising those sorts of things early in my VHDL life and then constraining port widths based on that. I'm slowly revisiting older code to your sort of style! The upshot of all this seems to be we all have our own wrappers for the standard blocks, which probably only differ very slightly (if at all!)... oh well - I guess that's the way the world has worked out, even if it seems inefficient in term sof engineering effort! Thanks for your contributions (as always - they're full of useful nuggets!) Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 111743
On 8 Nov 2006 23:15:29 -0800, lingamaneni.naveen@gmail.com wrote: >I have a JED file for an old PAL device and I have to put this design >in a FPGA. JED != ABEL. You have only the fusemap! >Is there a tool that can read the JED file and translate it to any >usable language (VHDL prefered)... Yup. It's a sloppy bag of fats and proteins suspended in salty water, and it sits between your ears. But being just a little more helpful.... It is not too difficult to construct a VHDL *netlist* from a fusemap and a description of the target PAL device, although I'm not aware of any off-the-shelf tools to do it. That could give you a simulation model, but it does NOT give you a behavioural model that would allow you to understand and modify the functionality. With your knowledge of the device's intended functionality and the simulation model, you could write a testbench to exercise it, check out the fine details of its behaviour and use that information to do the reverse engineering. If the PAL is purely combinatorial (PAL16L8 etc) then you could construct a truth table. If it's a registered device (PAL16R8, 22V10...) then it's a bit harder. In PAL devices register resources were scarce, and designers used all manner of ingerious tricks to cram in the logic; that usually meant obscuring the distinction between control and datapath, so reverse engineering could be fun. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 111744
Hi.
When I try to see the RTL Schematic, Xilinx ISE hangs and it is not
possible to stop it.
Furthermore I get the following warning in the map report:
WARNING:PhysDesignRules:367 - The signal
<XLXI_3/XLXI_1/split128bit_i/in128_k<63>> is incomplete. The signal
does not
drive any load pins in the design.
But in the vhdl-description of split128bit, in128_k is definitly used:
------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity split128bit is
port (
CLK100M : in std_logic;
in128_d : in std_logic_vector(127 downto 0);
in128_k : in std_logic_vector(127 downto 0);
startin : in std_logic;
out64_d : out std_logic_vector(63 downto 0);
out64_k : out std_logic_vector(63 downto 0);
startout : out std_logic;
loadout : out std_logic;
reset : in std_logic);
end split128bit;
architecture split128bit_arch of split128bit is
signal state : std_logic_vector(1 downto 0) := "00";
begin -- split128bit_arch
process (CLK100M, reset)
begin -- process
if reset = '1' then
out64_k <= (others => '0');
out64_d <= (others => '0');
startout <= '0';
loadout <= '0';
state <= "00";
out64_k <= (others => '0');
out64_d <= (others => '0');
elsif CLK100M'event and CLK100M = '1' then -- rising clock edge
if state = "00" then
startout <= '0';
if startin = '1' then
loadout <= '1';
state <= "01";
out64_k <= in128_k(127 downto 64);
out64_d <= in128_d(127 downto 64);
end if;
elsif state = "01" then
startout <= '0';
loadout <= '0';
state <= "10";
out64_k <= in128_k(63 downto 0);
out64_d <= in128_d(63 downto 0);
elsif state = "10" then
startout <= '1';
loadout <= '0';
state <= "00";
end if;
end if;
end process;
end split128bit_arch;
------------------------------------------------------
Does anyone has an idea how to solve this problem?
Regards
Jonas
Article: 111745On 2006-11-09, jonas <jpistor@uni-bremen.de> wrote: > Hi. > > When I try to see the RTL Schematic, Xilinx ISE hangs and it is not > possible to stop it. > Furthermore I get the following warning in the map report: > > WARNING:PhysDesignRules:367 - The signal > <XLXI_3/XLXI_1/split128bit_i/in128_k<63>> is incomplete. The signal > does not > drive any load pins in the design. > > But in the vhdl-description of split128bit, in128_k is definitly used: Is it used in XLXI_1? Is it ultimately used in XLXI_3? Since you can see this error in the map report the entire design has been optimized so if logic is removed in another module it may also mean that logic is removed in the split128bit module. Try to synthesize only the XLXI_1 module and see if you still see a similar error. If so you have narrowed the problem down somewhat. /AndreasArticle: 111746
Hi I have an 18-bit bus to a ZBT memory but when I P&R it in Xilinx it sets half the bus to TRISTATE and the other to BIDIR. Is this to do with the IO placement or something else? In Synplify they all come up as IOBUF Cheers JArticle: 111747
>>Do you change Data within the setup/hold time of your FFs? This may lead >>to strange results in your simulator. > > > I forbidden all the delay and timing check (i.e. setup/hold timeing > check of FFs). Will it lead to strange results? If the checks are enabled you will see at least the violations, and that might give clues what goes wrong. >>Besides simulation, have you made a static timing analysis for your design? > > > I want to do functional simulation of gate level and don't care > delay(and they are not accurate). With gated clocks the SDF usually has to be almost timing clean, otherwise strange things can happen. Gated clocks are harder to simulate, and make X chasing much harder, it can come trough the clock pin also ;) --KimArticle: 111748
Hi all, I've been struggling for two days now to get xapp730 from Xilinx to work. I've built the hw (wo FSL as it seems to be confusing the debugger) and can communicated with the CPU via xmd. However, the dow command seems to be failing. See transcript of xmd session below. Any help or input is very much apprechiated. Best regards, Johan Thelin --- 8< --- Address Map for Processor microblaze_0 (0x00000000-0x00001fff) dlmb_cntlr dlmb (0x00000000-0x00001fff) ilmb_cntlr ilmb (0x24000000-0x27ffffff) DDR_SDRAM_64Mx32 mb_opb (0x24000000-0x27ffffff) DDR_SDRAM_64Mx32 ixcl (0x24000000-0x27ffffff) DDR_SDRAM_64Mx32 dxcl (0x40000000-0x4000ffff) LEDs_4Bit mb_opb (0x40020000-0x4002ffff) Push_Buttons_Position mb_opb (0x40600000-0x4060ffff) RS232_Uart mb_opb (0x40800000-0x4080ffff) IIC_EEPROM mb_opb (0x40c00000-0x40c0ffff) Ethernet_MAC mb_opb (0x41200000-0x4120ffff) opb_intc_0 mb_opb (0x41400000-0x4140ffff) debug_module mb_opb (0x41800000-0x4180ffff) SysACE_CompactFlash mb_opb (0x41c00000-0x41c0ffff) opb_timer_1 mb_opb Connecting to cable (Parallel Port - LPT1). Checking cable driver. Driver windrvr6.sys version = 7.0.0.0.No resources. LPT base address = 0378h. ECP base address = 0778h. Cable connection failed. Connecting to cable (Parallel Port - LPT1). Checking cable driver. Driver windrvr6.sys version = 7.0.0.0. LPT base address = 0378h. ECP base address = 0778h. Cable connection failed. Connecting to cable (Parallel Port - LPT2). Checking cable driver. Driver windrvr6.sys version = 7.0.0.0.Cable connection failed. Connecting to cable (Parallel Port - LPT2). Checking cable driver. Driver windrvr6.sys version = 7.0.0.0.Cable connection failed. Connecting to cable (Usb Port - USB22). Checking cable driver. Driver xusbdfwu.sys version: 1021 (1021). Driver windrvr6.sys version = 7.0.0.0.Calling setinterface num=0, alternate=0. DeviceAttach: received and accepted attach for: vendor id 0x3fd, product id 0x8, device handle 0x16726b4 Cable PID = 0008. Max current requested during enumeration is 280 mA. Cable Type = 3, Revision = 0. Setting cable speed to 6 MHz. Cable connection established. Firmware version = 1021. CPLD file version = 0012h. CPLD version = 0012h. JTAG chain configuration -------------------------------------------------- Device ID Code IR Length Part Name 1 0a001093 8 System_ACE 2 05059093 16 XCF32P 3 01e58093 10 XC4VFX12 4 09608093 8 xc95144xl Assuming, Device No: 3 contains the MicroBlaze system Connected to the JTAG MicroProcessor Debug Module (MDM) No of processors = 1 MicroBlaze Processor 1 Configuration : ------------------------------------- Version............................5.00.a No of PC Breakpoints...............2 No of Read Addr/Data Watchpoints...0 No of Write Addr/Data Watchpoints..0 Instruction Cache Support..........on Instruction Cache Base Address.....0x24000000 Instruction Cache High Address.....0x27ffffff Data Cache Support.................on Data Cache Base Address............0x24000000 Data Cache High Address............0x27ffffff Exceptions Support................off FPU Support.......................off FSL DCache Support.................on FSL ICache Support.................on Hard Divider Support...............on Hard Multiplier Support............on Barrel Shifter Support.............on MSR clr/set Instruction Support....on Compare Instruction Support........on PVR Supported......................off JTAG MDM Connected to MicroBlaze 1 Connected to "mb" target. id = 0 Starting GDB server for "mb" target (id = 0) at TCP port no 1234 XMD% state Connected targets state Target ID State Target Type ---------------------------------------------------------- 0 Stopped MicroBlaze MDM-based (hw) Target XMD% mrd 0x24000000 100 24000000: FFFFFDFF 24000004: FFFFFFFF 24000008: FFFFFFFF 2400000C: FFFFFEFF 24000010: FFDFFFFF 24000014: FFFFFFFF 24000018: FFFFFFFF 2400001C: FFFFFFFF 24000020: FFFFFFFF 24000024: FFFF7FFF 24000028: BFFFFBFF 2400002C: FFFFFFFF 24000030: FFFFF7FF 24000034: FFFFFFFF 24000038: FFFFFFFE 2400003C: FFFFFFFF 24000040: FFFFFDFF 24000044: FFFFFFF7 24000048: FFFFFFFF 2400004C: FFFFFFFF 24000050: FFFF7FFF 24000054: FFFFFFFF 24000058: FFFFBFFF 2400005C: FFFFFFFF 24000060: FFFFFFFF 24000064: FFFFFFFF 24000068: FFFFFBFF 2400006C: FFFFFFFF 24000070: FFFFDDFF 24000074: FFFFF7FF 24000078: FFFFFFFF 2400007C: FFFFFFFF 24000080: FFFFFFFF 24000084: 7FFFFFFF 24000088: FFFFFFFF 2400008C: FFFFFFFF 24000090: FDFFFFFF 24000094: FFFFFFFF 24000098: FFFFFFFF 2400009C: FFFFFFFF 240000A0: FFFFFFFF 240000A4: FFFFFFFF 240000A8: FFFFFFFF 240000AC: FFFFFFFF 240000B0: FFFF7FFD 240000B4: FFFFFFFF 240000B8: BFFFFFFF 240000BC: BFFFFFFF 240000C0: FFFFFFFF 240000C4: FFFFF77F 240000C8: FFFFFBFF 240000CC: FFFFFFFF 240000D0: FFDFFFFF 240000D4: FFFFFFFF 240000D8: FFFEFFFF 240000DC: FFFFFFBF 240000E0: FFFFFFFF 240000E4: FFFFFFDF 240000E8: FFFFFBFF 240000EC: FBFFFFFF 240000F0: FFFFFFFF 240000F4: FFFFFFFF 240000F8: FFFFFFFF 240000FC: FFFFFFFF 24000100: FFFFFFFF 24000104: FFDFFFFF 24000108: FFEFFBFF 2400010C: FFFFFFFF 24000110: FFFFFFFF 24000114: F7FFFFFF 24000118: FFFFFFFF 2400011C: FFFFFFFF 24000120: FFFFFFFF 24000124: FFF7FFDF 24000128: FFFFFFFF 2400012C: FFFFFFFF 24000130: FFFFFFFF 24000134: FFFFFFFF 24000138: FFFFFBFF 2400013C: FFFFFFFF 24000140: FFFFDFFF 24000144: FFFFFFFF 24000148: BFFFFFFF 2400014C: FEFFFFFF 24000150: FFFFFFFF 24000154: FFFFFFFF 24000158: FFFFFFFF 2400015C: EFFFFFFF 24000160: FFFFFFFF 24000164: FFFFFFFF 24000168: FFFFBEFF 2400016C: FFFFFFFF 24000170: FFFFFDFF 24000174: FFFFFFFF 24000178: FFFFFFFF 2400017C: FFFFFFFF 24000180: FFFFFFFF 24000184: FFFFFDFF 24000188: FFFFFEFF 2400018C: FFFFFFFF XMD% mwr 0x24000000 1 XMD% mrd 0x24000000 1 24000000: 00000001 XMD% dow -data image.bin 0x24000000 XMD% mrd 0x24000000 100 24000000: 00000001 24000004: FFFFFFFF 24000008: FFFFFFFF 2400000C: FFFFFEFF 24000010: FFDFFFFF 24000014: FFFFFFFF 24000018: FFFFFFFF 2400001C: FFFFFFFF 24000020: FFFFFFFF 24000024: FFFF7FFF 24000028: BFFFFBFF 2400002C: FFFFFFFF 24000030: FFFFF7FF 24000034: FFFFFFFF 24000038: FFFFFFFE 2400003C: FFFFFFFF 24000040: FFFFFDFF 24000044: FFFFFFF7 24000048: FFFFFFFF 2400004C: FFFFFFFF 24000050: FFFF7FFF 24000054: FFFFFFFF 24000058: FFFFBFFF 2400005C: FFFFFFFF 24000060: FFFFFFFF 24000064: FFFFFFFF 24000068: FFFFFBFF 2400006C: FFFFFFFF 24000070: FFFFDDFF 24000074: FFFFF7FF 24000078: FFFFFFFF 2400007C: FFFFFFFF 24000080: FFFFFFFF 24000084: 7FFFFFFF 24000088: FFFFFFFF 2400008C: FFFFFFFF 24000090: FDFFFFFF 24000094: FFFFFFFF 24000098: FFFFFFFF 2400009C: FFFFFFFF 240000A0: FFFFFFFF 240000A4: FFFFFFFF 240000A8: FFFFFFFF 240000AC: FFFFFFFF 240000B0: FFFF7FFD 240000B4: FFFFFFFF 240000B8: BFFFFFFF 240000BC: BFFFFFFF 240000C0: FFFFFFFF 240000C4: FFFFF77F 240000C8: FFFFFBFF 240000CC: FFFFFFFF 240000D0: FFDFFFFF 240000D4: FFFFFFFF 240000D8: FFFEFFFF 240000DC: FFFFFFBF 240000E0: FFFFFFFF 240000E4: FFFFFFDF 240000E8: FFFFFBFF 240000EC: FBFFFFFF 240000F0: FFFFFFFF 240000F4: FFFFFFFF 240000F8: FFFFFFFF 240000FC: FFFFFFFF 24000100: FFFFFFFF 24000104: FFDFFFFF 24000108: FFEFFBFF 2400010C: FFFFFFFF 24000110: FFFFFFFF 24000114: F7FFFFFF 24000118: FFFFFFFF 2400011C: FFFFFFFF 24000120: FFFFFFFF 24000124: FFF7FFDF 24000128: FFFFFFFF 2400012C: FFFFFFFF 24000130: FFFFFFFF 24000134: FFFFFFFF 24000138: FFFFFBFF 2400013C: FFFFFFFF 24000140: FFFFDFFF 24000144: FFFFFFFF 24000148: BFFFFFFF 2400014C: FEFFFFFF 24000150: FFFFFFFF 24000154: FFFFFFFF 24000158: FFFFFFFF 2400015C: EFFFFFFF 24000160: FFFFFFFF 24000164: FFFFFFFF 24000168: FFFFBEFF 2400016C: FFFFFFFF 24000170: FFFFFDFF 24000174: FFFFFFFF 24000178: FFFFFFFF 2400017C: FFFFFFFF 24000180: FFFFFFFF 24000184: FFFFFDFF 24000188: FFFFFEFF 2400018C: FFFFFFFF XMD% --- >8 ---Article: 111749
Are you referring to the on-chip block RAM or the attached SDRAM on the sp3e board? John_H wrote: > Please look at the Spartan3E Starter Kit webpage > > http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=HW-SPAR3E-SK-US > > where, under the _Documentation_ heading you'll find the User Guide and the > Reference Designs. The reference design includes a PicoBlaze with a memory > loader that has both Verilog (or perhaps VHDL) source and an external > utility to load the memory dynamically. The Picoblaze assembler will also > generate a file that can be used as INITs in your BlockRAM instantiation. > The JTAG related updates should be the same for Spartan3 as it is for the > 3E. > > There are other memory-only update tools from Xilinx that might be easier. > Search the Xilinx site (or Answers Database) for "coe" which is the memory > file formate used for post-compiled memory updates. > > > "Jialin" <jiaojialin@gmail.com> wrote in message > news:1163025444.476315.65650@m73g2000cwd.googlegroups.com... > > Thank you very much for your help. > > > > But I want to load data/program into the SRAM of that board, > > do you know how can I do that? > > > > Thanks again. > > > > On Nov 7, 7:22 pm, "John_H" <newsgroup@johnhandwork.com> wrote: > >> If, on the other hand, you have a picoBlaze or MicroBlaze for which you > >> want > >> to update the memory, the Spartan3E Starter Kit has that ready to go. > >> Source code is available. > >> > >> "Matthew Hicks" <mdhicks2@uiuc.edu> wrote in > >> messagenews:eiqq83$819$1@news.ks.uiuc.edu... > >> > >> > >> > >> > If you are talking about the EEPROM or any other non-volatile on-board > >> > memory, it should be detected by Impact. Just create an PROM file > >> > (.mcs) > >> > from the .bit file and load it into the memory. All of this can be > >> > done > >> > inside impact and should be detailed in the user manual for your board. > >> > >> > ---Matthew Hicks > >> > >> > "Jialin" <jiaojialin@gmail.com> wrote in message > >> >news:1162913626.614634.231140@m73g2000cwd.googlegroups.com... > >> >> Hi my friends, > >> > >> >> We know little about Spartan and Xilinx. We are connecting our > >> >> Spartan 3 starter kit board to a PC and using Xilinx ISE 8.1 to > >> >> control > >> >> it. > >> > >> >> We want to find a way to load our program ( instructions) into the > >> >> memory of > >> >> the Spartan board. Could you tell me how? We will appreciate it if you > >> >> could kindly show some light on this.- Hide quoted text -- Show quoted > >> >> text - > >
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