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Have you considered using a DCM to remove the clock skew? You have 5.7ns of clock delay, using a DCM would cut this way back. John Providenza On Mar 16, 10:35 am, jean-baptiste.nou...@jdsu.com wrote: > Hello Cheng, > > I have just tried your design here. > 6ns from inside clock to outside of the chip is not huge. > > If you want to go high up in frequency, you have two choices: > - the fpga (when writing to the outside) needs to provide the clock > alonside the data. This is done for instance by running the fpga at > twice the frequency then dividing this clock in the IOB by two and > this > forms the clock you provide to the outside world. But in your case > twice as > much might be a pain. > This way your system is said 'source synchronous'. > > - if your system is 'system synchronous' i.e. an external clock is fed > to your > fpga and the other chips it interfaces with, then what you can do is > use a dcm > inside the fpga and use clk270 to 'advance the clock (1/4Tcycle). This > will help the > fpga-writes case but make sure it doesn't break the fpga-read (you can > do the math: > 1/4Tcycle in your case is 2ns). > > I hope this helps, > jbArticle: 116751
Folks, I need to do a trial synthesis to see if one of our ASIC design module will run at speed (~312.5Mhz) in Xilinx Virtex 5 LXT fpga. Is SYnplify Premiere the front end synthesis tool to use for this exercise ? --Chirag Shroff Tech Lead GGSG Engineering Cisco SystemsArticle: 116752
My thought: if you need a BUFG for internal logic, instantiate it. You can find the BUFG primitive in the libraries guide. "Joel" <jceven@gmail.com> wrote in message news:1174058846.481307.7550@e1g2000hsg.googlegroups.com... > Xilinx gurus out there, > > I have a very very simple design with a 24 bit counter, and I am using > bit 24 in an always block like this > > always @(posedge cnt[23]) > > > Xilinx is telling me that it didnt automatically insert a clock > buffer, and that it thinks this is a clock. I then added > // synthesis attribute BUFFER_TYPE of cnt[23] is bufgp > > to my verilog and to a .xcf file (that I specified as synthesis > constraints file in synthesis properties). > > However synthesis is still reporting that cnt[23] is a clock and the > buffer type is NONE and that I need to specify buffer_type for if I > want it to insert a buffer. > > What am I doing wrong? Based on what I read about synthesis > attributes, they can just go inline with the verilog, but it doenst > seem to be getting picked up. > > Any ideas? > > Thanks, > -JArticle: 116753
glen herrmannsfeldt wrote: > Peter Alfke wrote: > >> John is of course right. Memories have no global or parallel clear. >> Such a clear would require an extra input to every data storage cell, >> plus a wire interconnecting these inputs. Too expensive and too slow >> in the highly competitive high-density RAM market. > > > I remember wondering some years ago (in the 8080 days) if SRAM > tended to power up to the same state. It seemed that the screen > image on power up, before the software cleared the screen, tended > to be similar. While a clear would be expensive, designing memory > cells, either SRAM or DRAM, to power up in a certain state might not > be as expensive. I don't know that anyone has tried, though. > > I also remember discussions about EPROMs that erase to > either 0 or 1, and which processors have opcode X'00' as NOOP. > > -- glen > Xilinx BRAMs do initialize in a known state on FPGA configuration. The memory can be set to specific contents, or will default to all zero.Article: 116754
Yeah that would be pretty easy to do, and I considered that. In fact this synthesis attribute is not that important, but I'd like to know how to implement it, so that the tools pick up the directive. -J > My thought: if you need a BUFG for internal logic, instantiate it. You can > find the BUFG primitive in the libraries guide. > > "Joel" <jce...@gmail.com> wrote in message > > news:1174058846.481307.7550@e1g2000hsg.googlegroups.com... > > > Xilinx gurus out there, > > > I have a very very simple design with a 24 bit counter, and I am using > > bit 24 in an always block like this > > > always @(posedge cnt[23]) > > > Xilinx is telling me that it didnt automatically insert a clock > > buffer, and that it thinks this is a clock. I then added > > // synthesis attribute BUFFER_TYPE of cnt[23] is bufgp > > > to my verilog and to a .xcf file (that I specified as synthesis > > constraints file in synthesis properties). > > > However synthesis is still reporting that cnt[23] is a clock and the > > buffer type is NONE and that I need to specify buffer_type for if I > > want it to insert a buffer. > > > What am I doing wrong? Based on what I read about synthesis > > attributes, they can just go inline with the verilog, but it doenst > > seem to be getting picked up. > > > Any ideas? > > > Thanks, > > -JArticle: 116755
It is unclear on what device you are targeting, but it is very easy to use CoreGen to generate an example design for 1000-BaseX (assuming you are using the embedded EMAC block). It is a simple loopback for non-jumbo sized frames. Before we released Virtex-5, I tested the example design on our ML525 RocketIO Characterization board and can confirm it does work for SGMII 1000Base-X modes. As a matter fo fact, the CoreGen example was used in part of the design that we took to UNH for compliance testing (and passed with it). The only modification required is the addition of a .UCF file. If using Virtex-5, you will need the to have the (9.1i) CoreGen IP update installed to see the 'Virtex-5 Embedded Tri-mode Ethernet MAC Wrapper' core visible. What core are you using and what device are you targeting? -David <mynewlifever@yahoo.com.cn> wrote in message news:1174040570.042282.58070@d57g2000hsg.googlegroups.com... >I want to generate sgmii interface with coregen. I choose this > IP-"Ethernet 1000BASE-X PCS/PMA or SGMII" , when i generate, I never > find sgmii interface except sgmii_clk signal. So i want to ask where > is the serial data bus? > > Thank you! >Article: 116756
The question your're asking is a bit like "how long is this bit of string". All of the Physical synthesis tools claim better performance and from what I have seen there is some truth in those claims. However how far it goes is ultimately limited by the design entered by the human and usually it's is the human being's best efforts that determine if that speed is attained. The speed that you are looking to attain is possible in V5 but only if the design does not have too many logic levels between flip-flops etc. etc.. Best way forward is simply to try it and see how bad a timing result you get before entering the game of making timing closure. John Adair Enterpoint Ltd. On 16 Mar, 17:52, cshr...@gmail.com wrote: > Folks, > I need to do a trial synthesis to see if one of our ASIC design module > will run at speed (~312.5Mhz) in Xilinx Virtex 5 LXT fpga. Is SYnplify > Premiere the front end synthesis tool to use for this exercise ? > > --Chirag Shroff > Tech Lead > GGSG Engineering > Cisco SystemsArticle: 116757
"Joel" <jceven@gmail.com> wrote: >Xilinx gurus out there, > >I have a very very simple design with a 24 bit counter, and I am using >bit 24 in an always block like this > >always @(posedge cnt[23]) > > >Xilinx is telling me that it didnt automatically insert a clock >buffer, and that it thinks this is a clock. I then added >// synthesis attribute BUFFER_TYPE of cnt[23] is bufgp > >to my verilog and to a .xcf file (that I specified as synthesis >constraints file in synthesis properties). > >However synthesis is still reporting that cnt[23] is a clock and the >buffer type is NONE and that I need to specify buffer_type for if I >want it to insert a buffer. > >What am I doing wrong? Based on what I read about synthesis >attributes, they can just go inline with the verilog, but it doenst >seem to be getting picked up. > >Any ideas? Did you look at other verilog examples? I'm far from a verilog expert, but to me the above statement looks like you are using the counter outputs as a clock. Maybe this page will help you a bit further: http://www.asic-world.com/verilog/first1.html -- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nlArticle: 116758
Yes I am using the counter outputs as a clock, and cnt[23] will be fed into the clk input of the flop thats going to be synthesized. Based on the example of xilinx synthesis constraints I either put the synthesis attribute as a verilog comment, or in a xilinx constraints file. I don't think using a bit from a counter is a bad thing to do for a clock and that is what I want to do (provided if I make sure the tools know its going to be a clock) in digital logic, but again its not so much the point that I am using the counter msb as a clock, then how do I get the xilinx tools to pick up my synthesis constraints. I could instantiate a BUFG primitive aswas mentioned but, I'd like to learn why my synthesis attribute is being ignored, or not picked up by the synthesis tool. -J On Mar 16, 12:50 pm, n...@puntnl.niks (Nico Coesel) wrote: > "Joel" <jce...@gmail.com> wrote: > >Xilinx gurus out there, > > >I have a very very simple design with a 24 bit counter, and I am using > >bit 24 in an always block like this > > >always @(posedge cnt[23]) > > >Xilinx is telling me that it didnt automatically insert a clock > >buffer, and that it thinks this is a clock. I then added > >// synthesis attribute BUFFER_TYPE of cnt[23] is bufgp > > >to my verilog and to a .xcf file (that I specified as synthesis > >constraints file in synthesis properties). > > >However synthesis is still reporting that cnt[23] is a clock and the > >buffer type is NONE and that I need to specify buffer_type for if I > >want it to insert a buffer. > > >What am I doing wrong? Based on what I read about synthesis > >attributes, they can just go inline with the verilog, but it doenst > >seem to be getting picked up. > > >Any ideas? > > Did you look at other verilog examples? I'm far from a verilog expert, > but to me the above statement looks like you are using the counter > outputs as a clock. > > Maybe this page will help you a bit further:http://www.asic-world.com/verilog/first1.html > > -- > Reply to nico@nctdevpuntnl (punt=.) > Bedrijven en winkels vindt U opwww.adresboekje.nlArticle: 116759
John, I agree. It's a little bit of an open ended question. I guess, I was looking for someone to jump in and say, try this particular tool because it did the trick for us. BTW, I did try Synplify Premiere and I am close to 270Mhz with just the tool "switches". --Chirag Shroff On Mar 16, 3:26 pm, "John Adair" <g...@enterpoint.co.uk> wrote: > The question your're asking is a bit like "how long is this bit of > string". All of the Physical synthesis tools claim better performance > and from what I have seen there is some truth in those claims. However > how far it goes is ultimately limited by the design entered by the > human and usually it's is the human being's best efforts that > determine if that speed is attained. The speed that you are looking to > attain is possible in V5 but only if the design does not have too many > logic levels between flip-flops etc. etc.. Best way forward is simply > to try it and see how bad a timing result you get before entering the > game of making timing closure. > > John Adair > Enterpoint Ltd. > > On 16 Mar, 17:52, cshr...@gmail.com wrote: > > > Folks, > > I need to do a trial synthesis to see if one of our ASIC design module > > will run at speed (~312.5Mhz) in Xilinx Virtex 5 LXT fpga. Is SYnplify > > Premiere the front end synthesis tool to use for this exercise ? > > > --Chirag Shroff > > Tech Lead > > GGSG Engineering > > Cisco SystemsArticle: 116760
Hi, I'm about to buy a new workstation for FPGA development and I'm hesitating between a Core 2 Extreme @ 2.93 GHz (X6800) and the new quad-core @ 2.66 GHz (QX6700). The price difference is 100$. Does Xilinx have any roadmap for multi-core CPU support in the future? I'd hate to buy a dual-core CPU just to learn that ISE v10.1 features quad-core support... If there is no multi-core support planned for the foreseeable future, I'll probably buy the dual-core CPU because it's slightly faster than the quad-core one. I'm going to work on a Virtex 4 FX100 soon so I'll need all the horsepower I can get for the P&R runs... PatrickArticle: 116761
Ray Andraka wrote: > glen herrmannsfeldt wrote: >> Peter Alfke wrote: >> >> I remember wondering some years ago (in the 8080 days) if SRAM >> tended to power up to the same state. It seemed that the screen >> image on power up, before the software cleared the screen, tended >> to be similar. While a clear would be expensive, designing memory >> cells, either SRAM or DRAM, to power up in a certain state might not >> be as expensive. I don't know that anyone has tried, though. >> >> I also remember discussions about EPROMs that erase to >> either 0 or 1, and which processors have opcode X'00' as NOOP. >> >> -- glen >> > > Xilinx BRAMs do initialize in a known state on FPGA configuration. The > memory can be set to specific contents, or will default to all zero. True, but device reprogramming happens only once at power-up unless triggered by other means afterwards. Since the OP was about clearing memory "on-demand", none of those power-up-specific details are relevant though.Article: 116762
Did you run it through the ISE backend tools as well? Synplify can be very optimistic in its estimate of net delays. ah On Mar 16, 4:04 pm, cshr...@gmail.com wrote: > John, > > I agree. It's a little bit of an open ended question. I guess, I was > looking for someone to jump in and say, try this particular tool > because it did the trick for us. > > BTW, I did try Synplify Premiere and I am close to 270Mhz with just > the tool "switches". > > --Chirag Shroff > On Mar 16, 3:26 pm, "John Adair" <g...@enterpoint.co.uk> wrote: > > > The question your're asking is a bit like "how long is this bit of > > string". All of the Physical synthesis tools claim better performance > > and from what I have seen there is some truth in those claims. However > > how far it goes is ultimately limited by the design entered by the > > human and usually it's is the human being's best efforts that > > determine if that speed is attained. The speed that you are looking to > > attain is possible in V5 but only if the design does not have too many > > logic levels between flip-flops etc. etc.. Best way forward is simply > > to try it and see how bad a timing result you get before entering the > > game of making timing closure. > > > John Adair > > Enterpoint Ltd. > > > On 16 Mar, 17:52, cshr...@gmail.com wrote: > > > > Folks, > > > I need to do a trial synthesis to see if one of our ASIC design module > > > will run at speed (~312.5Mhz) in Xilinx Virtex 5 LXT fpga. Is SYnplify > > > Premiere the front end synthesis tool to use for this exercise ? > > > > --Chirag Shroff > > > Tech Lead > > > GGSG Engineering > > > Cisco SystemsArticle: 116763
Hi, What official functions should I call to genertate a sum of products in VHDL? S(...) <= A0*B0(...) + A1*B1(...) + A2*B2(...) + ... + An*Bn(...); Ax is a type of std_logic or bool; Bx() is a type of std_logic_vector or unsigned. I use the following two libraries: USE ieee.std_logic_1164.all; use ieee.numeric_std.all; Thank you. WengArticle: 116764
ANSI-C preprocessor supports a 'wildcard' ...
#include<stdio.h>
#define _NOISY_PRINTF( ... ) printf( ... )
#define _QUIET_PRINTF( ... )
int
main( void )
{
_NOISY_PRINTF( "hello world, %d, %d, %d!\n", 1, 2,3 );
// hello world, 1, 2, 3!
//
_QUIET_PRINTF( "hello world, %d, %d, %d!\n", 1, 2,3 );
// <<no output to stdout>>
//
}
I don't suppose Systemverilog's preprocessor supports this?
(And I assume SystemC has no trouble with it...)
Article: 116765
I noticed XST 9.1 still doesn't support multi-dim arrays in an always @*
block.
Here's a (perhaps poor) example:
reg signed [15:0] table [0:255];
reg signed [23:0] sum;
integer i;
always @*
begin
sum = 0;
for ( i =0; i < 256; i = i + 1 )
sum = sum + table[i]; // yes, I know this will synthesize a suboptimal
imbalanced adder-tree!
end
Article: 116766
Weng Tianxiang schrieb:
> What official functions should I call to genertate a sum of products
> in VHDL?
>
> S(...) <= A0*B0(...) + A1*B1(...) + A2*B2(...) + ... + An*Bn(...);
>
> Ax is a type of std_logic or bool; Bx() is a type of std_logic_vector
> or unsigned.
Looks similar to standard multiplication. What about:
process(A,B)
variable result : unsigned(result_bits-1 downto 0);
begin
result:=to_unsigned(0,result'length);
for N in A'range loop
if (A(N)='1') then
result:=result+resize(unsigned(B(N)),result'length);
end if;
end loop;
s<=result;
end process;
(code not checked for any errors - just typed)
This may result in synthesis in a slow carry-ribble array. As an
alternative you could use this for-loop to first generate a 2D-vector
table containing eigther zero vectors or B-vectors (depending on A).
This 2D-Array could be added as multipliers do: Carry-Save-Array,
Wallace-Tree...
Another option would be to make each A-Bits a vector:
A_vec(N)<=('0' & A(N));
Such a vector can be easily converted to unsigned and you can just type
you sum of products, as you have done it in your question.
Ralf
Article: 116767<cshroff@gmail.com> wrote in message news:1174075466.100899.53760@l77g2000hsb.googlegroups.com... > John, > > I agree. It's a little bit of an open ended question. I guess, I was > looking for someone to jump in and say, try this particular tool > because it did the trick for us. With a name like Cisco I would set up an NDA with Synplicity and Mentor (Precision Physical) give them the design and say hey I need 312.5MHz and if you can achieve it I will buy it :-) Hans www.ht-lab.com > > BTW, I did try Synplify Premiere and I am close to 270Mhz with just > the tool "switches". > > --Chirag Shroff > On Mar 16, 3:26 pm, "John Adair" <g...@enterpoint.co.uk> wrote: >> The question your're asking is a bit like "how long is this bit of >> string". All of the Physical synthesis tools claim better performance >> and from what I have seen there is some truth in those claims. However >> how far it goes is ultimately limited by the design entered by the >> human and usually it's is the human being's best efforts that >> determine if that speed is attained. The speed that you are looking to >> attain is possible in V5 but only if the design does not have too many >> logic levels between flip-flops etc. etc.. Best way forward is simply >> to try it and see how bad a timing result you get before entering the >> game of making timing closure. >> >> John Adair >> Enterpoint Ltd. >> >> On 16 Mar, 17:52, cshr...@gmail.com wrote: >> >> > Folks, >> > I need to do a trial synthesis to see if one of our ASIC design module >> > will run at speed (~312.5Mhz) in Xilinx Virtex 5 LXT fpga. Is SYnplify >> > Premiere the front end synthesis tool to use for this exercise ? >> >> > --Chirag Shroff >> > Tech Lead >> > GGSG Engineering >> > Cisco Systems > >Article: 116768
On 3=D4=C217=C8=D5, =CF=C2=CE=E72=CA=B128=B7=D6, "Ulsk" <a...@ljs.com> wrot= e: > I noticed XST 9.1 still doesn't support multi-dim arrays in an always @* > block. > Here's a (perhaps poor) example: > > reg signed [15:0] table [0:255]; > reg signed [23:0] sum; > > integer i; > always @* > begin > sum =3D 0; > for ( i =3D0; i < 256; i =3D i + 1 ) > sum =3D sum + table[i]; // yes, I know this will synthesize a subopt= imal > imbalanced adder-tree! > end I think the code can not be synthesize correctly by any tool not only ISE!Article: 116769
"Joel" <jceven@gmail.com> wrote: >Yes I am using the counter outputs as a clock, and cnt[23] will be fed >into the clk input of the flop thats going to be synthesized. Based >on the example of xilinx synthesis constraints I either put the >synthesis attribute as a verilog comment, or in a xilinx constraints >file. > >I don't think using a bit from a counter is a bad thing to do for a >clock and that is what I want to do (provided if I make sure the tools >know its going to be a clock) in digital logic, but again its not so >much the point that I am using the counter msb as a clock, then how do >I get the xilinx tools to pick up my synthesis constraints. > >I could instantiate a BUFG primitive aswas mentioned but, I'd like to >learn why my synthesis attribute is being ignored, or not picked up by >the synthesis tool. The answer should be somewhere in the log files. However, the number of BUFG elements is limited (because they drive low skew global clock nets). You can use the counter outputs as a local clock without the BUFG. It is a good idea to also specify the period of the local clocks as well so the routing tools can do a proper placement. > >-J > > >On Mar 16, 12:50 pm, n...@puntnl.niks (Nico Coesel) wrote: >> "Joel" <jce...@gmail.com> wrote: >> >Xilinx gurus out there, >> >> >I have a very very simple design with a 24 bit counter, and I am using >> >bit 24 in an always block like this >> >> >always @(posedge cnt[23]) >> >> >Xilinx is telling me that it didnt automatically insert a clock >> >buffer, and that it thinks this is a clock. I then added >> >// synthesis attribute BUFFER_TYPE of cnt[23] is bufgp >> >> >to my verilog and to a .xcf file (that I specified as synthesis >> >constraints file in synthesis properties). >> >> >However synthesis is still reporting that cnt[23] is a clock and the >> >buffer type is NONE and that I need to specify buffer_type for if I >> >want it to insert a buffer. >> >> >What am I doing wrong? Based on what I read about synthesis >> >attributes, they can just go inline with the verilog, but it doenst >> >seem to be getting picked up. >> >> >Any ideas? >> >> Did you look at other verilog examples? I'm far from a verilog expert, >> but to me the above statement looks like you are using the counter >> outputs as a clock. >> >> Maybe this page will help you a bit further:http://www.asic-world.com/verilog/first1.html >> >> -- >> Reply to nico@nctdevpuntnl (punt=.) >> Bedrijven en winkels vindt U opwww.adresboekje.nl > > -- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nlArticle: 116770
On 25 f=E9v, 02:22, Michael Gernoth <m...@gernoth.net> wrote: > Hello, > after being bitten by windrvr once again (it did not compile after a > kernel upgrade), I decided to see if I could get the Xilinx USB cable > and impact working without a kernel module. > [...] > Please report back if this library is useful and works for you. > [...] Just to add another positive feedback : * It works like a charm for me ! * I find it very usefull ! My configuration : * OS : Ubuntu Dapper 6.06 * cable : Xilinx parallel IV * Xilinx Tool : ISE Webpack 9.1 SP02 * programmed chip : Virtex4 LX25 (of an ML401 board) For me, it works in "compatibility mode" only, as with "windrvr" driver. Many thanks for your work ! Luzerne GANHIRArticle: 116771
Hi,
In my many projects, some signals have both positive reference and
negative reference, does it cause an additional LUT delay?
For example, in the following statement Rx and not Rx are both used
and they cannot be put together by a LUT.
A1 : process(CLK)
begin
if(CLK'event and CLK = '1') then
A <= Sx;
end if;
end process;
A2 : process(CLK)
begin
if(CLK'event and CLK = '1') then
B <= not Sx;
end if;
end process;
Sx may be a combinational signal or a flip-flop output.
I am wondering whether Xilinx interconnect resources is capable of
inversing a passing signal based on the need.
Thank you.
Weng
Article: 116772"Rebecca" <pang.dudu.pang@hotmail.com> wrote in message news:1173995035.186185.243100@b75g2000hsg.googlegroups.com... > > But I noticed when I load the input netlist file which is targeting on > virtex5, the inserter didn't recongnized it and I have to changed it > manually from virtex4 to virtex5. If I don't change this setting, it > can still generated the .ngo file. Is there any problem? > Which version of the tools are you using? There are a few answer records on Xilinx site covering problems in using ChipScope with Virtex 5, e.g. the following for 8.2: http://tinyurl.com/2m6bxf and this for 9.1: http://tinyurl.com/28gdls /MikhailArticle: 116773
Hi, I do a post place and route simulation using modelsim. To estimate the power I generate dump.vcd file during simulation so that I can get the power numbers using XPower. The problem is that XPower at the very end of its execution crashes and it aborts, giving me this message: FATAL_ERROR:Power:vcdParser.y:815: - PowerVcd_Parser: line 669374017: No valid identifier code was specified for scalar value change. Identifier provided was jL:0nL: Process will terminate. To resolve this error, please consult the Answers Database and other online resources at http://support.xilinx.com. The size of the vcd file is about 5GB. So there is no way that I can open it to get a better idea of the problem. Do you have any idea why I get this error message? Can it be a problem of my design size? or can it be a problem with the design itself? Because the simulation works just fine so I don't know why XPower should crash. My design is roughly about 8000-9000 slices. Thanks,Article: 116774
I forgot to mention that I'm using ISE foundation 8.2i. On Mar 17, 11:35 am, "Xesium" <amirhossein.gholamip...@gmail.com> wrote: > Hi, > I do a post place and route simulation using modelsim. To estimate the > power I generate dump.vcd file during simulation so that I can get the > power numbers using XPower. The problem is that XPower at the very end > of its execution crashes and it aborts, giving me this message: > > FATAL_ERROR:Power:vcdParser.y:815: - PowerVcd_Parser: line 669374017: > No valid identifier code was specified for scalar value change. > Identifier provided was jL:0nL: Process will terminate. > To resolve this error, please consult the Answers Database and other > online resources athttp://support.xilinx.com. > > The size of the vcd file is about 5GB. So there is no way that I can > open it to get a better idea of the problem. > Do you have any idea why I get this error message? Can it be a problem > of my design size? or can it be a problem with the design itself? > Because the simulation works just fine so I don't know why XPower > should crash. > My design is roughly about 8000-9000 slices. > > Thanks,
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