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On 13 mar, 16:27, "John_H" <newsgr...@johnhandwork.com> wrote:
> Add them together?
>
> Your problem is not clear. Do you have an array in memory that you need to
> cycle through the elements one-by-one through an accumulator? Do you have
> an array of registers that needs a sum through a simple adder tree? Do you
> need to add two arrays held in memory to get a third array?
>
> Please clarify the help you would like.
>
> "VHDL_HELP" <abai...@gmail.com> wrote in message
>
> news:1173792287.141073.35720@t69g2000cwt.googlegroups.com...
>
> > hi every body ,
>
> > please please how to calculate the sum of an array ( for example an
> > array of std_logic_vector(3 downto 0) )
>
> > thank you
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity somme is
Port ( clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR (3 downto 0);
taille : in STD_LOGIC_VECTOR (2 downto 0);
dout : out STD_LOGIC_VECTOR (3 downto 0)
);
end somme;
architecture Behavioral of somme is
type tab is array(3 downto 0) of STD_LOGIC_VECTOR(3 DOWNTO 0);
signal s : tab;
begin
process(clk)
begin
if clk'event and clk ='1' then
s(conv_integer(taille)) <= din;
end if;
end process;
dout <= s(0) + s(1) + s(2) + s(3);
end Behavioral;
------------------------------------------------------------------------------------------------------------------------------------------------
my problem is : a simple addition for elements of an array !!!
this programm is correct into syntax but not synthetisable and it dont
give me the results that i want
please i m a beginner and i want a clear way to think how to make
this simple addition
thank you
Article: 116601
On 13 mar, 16:27, "John_H" <newsgr...@johnhandwork.com> wrote:
> Add them together?
>
> Your problem is not clear. Do you have an array in memory that you need to
> cycle through the elements one-by-one through an accumulator? Do you have
> an array of registers that needs a sum through a simple adder tree? Do you
> need to add two arrays held in memory to get a third array?
>
> Please clarify the help you would like.
>
> "VHDL_HELP" <abai...@gmail.com> wrote in message
>
> news:1173792287.141073.35720@t69g2000cwt.googlegroups.com...
>
> > hi every body ,
>
> > please please how to calculate the sum of an array ( for example an
> > array of std_logic_vector(3 downto 0) )
>
> > thank you
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity somme is
Port ( clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR (3 downto 0);
taille : in STD_LOGIC_VECTOR (2 downto 0);
-- clk_out : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR (3 downto 0)
);
end somme;
architecture Behavioral of somme is
type tab is array(3 downto 0) of STD_LOGIC_VECTOR(3 DOWNTO 0);
signal s : tab;
begin
process(clk)
begin
if clk'event and clk ='1' then
s(conv_integer(taille)) <= din;
end if;
end process;
dout <= s(0) + s(1) + s(2) + s(3);
end Behavioral;
------------------------------------------------------------------------
it is correct on syntax but not sythetisable : it gives me as a reslt
for dout : 4'hX
Article: 116602
"VHDL_HELP" <abaidik@gmail.com> wrote in message
news:1173802687.701492.283170@64g2000cwx.googlegroups.com...
>
> library IEEE;
> use IEEE.STD_LOGIC_1164.ALL;
> use IEEE.STD_LOGIC_ARITH.ALL;
> use IEEE.STD_LOGIC_UNSIGNED.ALL;
>
> entity somme is
> Port ( clk : in STD_LOGIC;
> din : in STD_LOGIC_VECTOR (3 downto 0);
> taille : in STD_LOGIC_VECTOR (2 downto 0);
>
> dout : out STD_LOGIC_VECTOR (3 downto 0)
> );
> end somme;
>
> architecture Behavioral of somme is
> type tab is array(3 downto 0) of STD_LOGIC_VECTOR(3 DOWNTO 0);
> signal s : tab;
> begin
> process(clk)
> begin
> if clk'event and clk ='1' then
> s(conv_integer(taille)) <= din;
> end if;
> end process;
> dout <= s(0) + s(1) + s(2) + s(3);
> end Behavioral;
>
> ------------------------------------------------------------------------------------------------------------------------------------------------
> my problem is : a simple addition for elements of an array !!!
> this programm is correct into syntax but not synthetisable and it dont
> give me the results that i want
> please i m a beginner and i want a clear way to think how to make
> this simple addition
> thank you
Could it be that you haven't yet written all four elements of the array in
your simulation? At start, all four elements of s are 4'hX. All four
elements have to be written in order to obtain a valid dout. I am curious
about the (2 downto 0) on the taille input yet array(3 downto 0) on s. Are
you trying to abbreviate:
if( NOT taille(2) ) then
s(conv_integer(taille(1 downto 0))) <= din;
end if;
or should taille be (1 downto 0) or should tab be array(7 downto 0) ?
Article: 116603"Duane Clark" <junkmail@junkmail.com> wrote in message news:HpzJh.7823$FG1.3299@newssvr27.news.prodigy.net... > ALuPin@web.de wrote: >> Hi John, >> >> yes, your proposal seems to be a good approach. Setting a timing >> constraint to achieve setup time margin when changing the clock domain >> is the point which should be kept clearly in mind. > > As long as you are using just different edges of the same clock, a period > timing constraint will automatically take into consideration that you have > changed clock edges. That is true, indeed, as long as you're using registers. If you use a latch to provide more generous timing margins to synchronize between two time domains, the timing analyzer needs to by "nudged" to get the proper set of constraints. "ENABLE=lat_d_q;" is insufficient to get the setup to the trailing edge of the latch clear pulse at the correct clock edge if memory serves. - John_HArticle: 116604
On 13 mar, 18:05, "John_H" <newsgr...@johnhandwork.com> wrote: > "VHDL_HELP" <abai...@gmail.com> wrote in message > > news:1173802687.701492.283170@64g2000cwx.googlegroups.com... > > > > > > > library IEEE; > > use IEEE.STD_LOGIC_1164.ALL; > > use IEEE.STD_LOGIC_ARITH.ALL; > > use IEEE.STD_LOGIC_UNSIGNED.ALL; > > > entity somme is > > Port ( clk : in STD_LOGIC; > > din : in STD_LOGIC_VECTOR (3 downto 0); > > taille : in STD_LOGIC_VECTOR (2 downto 0); > > > dout : out STD_LOGIC_VECTOR (3 downto 0) > > ); > > end somme; > > > architecture Behavioral of somme is > > type tab is array(3 downto 0) of STD_LOGIC_VECTOR(3 DOWNTO 0); > > signal s : tab; > > begin > > process(clk) > > begin > > if clk'event and clk =3D'1' then > > s(conv_integer(taille)) <=3D din; > > end if; > > end process; > > dout <=3D s(0) + s(1) + s(2) + s(3); > > end Behavioral; > > > -----------------------------------------------------------------------= ----=AD--------------------------------------------------------------------- > > my problem is : a simple addition for elements of an array !!! > > this programm is correct into syntax but not synthetisable and it dont > > give me the results that i want > > please i m a beginner and i want a clear way to think how to make > > this simple addition > > thank you > > Could it be that you haven't yet written all four elements of the array in > your simulation? At start, all four elements of s are 4'hX. All four > elements have to be written in order to obtain a valid dout. I am curious > about the (2 downto 0) on the taille input yet array(3 downto 0) on s. A= re > you trying to abbreviate: > if( NOT taille(2) ) then > s(conv_integer(taille(1 downto 0))) <=3D din; > end if; > or should taille be (1 downto 0) or should tab be array(7 downto 0) ? for taille : i have to get an array of 4 elements so i need 2 bits to reference these elements ( the elements are represented with 4 bits ) no? that it is why i use taille isnt right? From Tim@spamtrap.com Tue Mar 13 09:30:38 2007 Path: newsdbm02.news.prodigy.net!newsdst02.news.prodigy.net!prodigy.com!newscon02.news.prodigy.net!prodigy.net!news.glorb.com!feed.xsnews.nl!border-1.ams.xsnews.nl!eweka.nl!hq-usenetpeers.eweka.nl!195.245.201.2.MISMATCH!news.clara.net!wagner.news.clara.net!monkeydust.news.clara.net!proxy02.news.clara.net From: "Tim" <Tim@spamtrap.com> Newsgroups: comp.arch.fpga Subject: PCI - Express Date: Tue, 13 Mar 2007 17:30:38 -0000 Lines: 20 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.3028 X-RFC2646: Format=Flowed; Original X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.3028 X-Complaints-To: abuse@clara.net (please include full headers) X-Trace: 734fc645333012ce23e0213e6030059230d2e53312387512c2ac220e45f6dfc7 NNTP-Posting-Date: Tue, 13 Mar 2007 17:30:47 +0000 Message-Id: <1173807047.4904.0@proxy02.news.clara.net> Xref: prodigy.net comp.arch.fpga:128179 X-Received-Date: Tue, 13 Mar 2007 13:35:01 EDT (newsdbm02.news.prodigy.net) My understanding of the initialising sequence for a PCI-E card is as follows: 1 Detect phase to see if there's a receiver connected 2 Send TS1s 3 Send 1024 TS1 after at least one TS1 has been received 4 Send TS2s and continue to send them until 8 TS2s have been received 5 Send a further 16 TS2s 6 Send TS1s and wait for 2 TS1s with Link number rather than PAD symbol 7 Return TS1s with Link number and wait to receive 2 TS1s with Lane number 8 Return TS1s with Link and lane number What's wrong with the above? Regards TimArticle: 116605
On 13 mar, 18:05, "John_H" <newsgr...@johnhandwork.com> wrote: > "VHDL_HELP" <abai...@gmail.com> wrote in message > > news:1173802687.701492.283170@64g2000cwx.googlegroups.com... > > > > > > > library IEEE; > > use IEEE.STD_LOGIC_1164.ALL; > > use IEEE.STD_LOGIC_ARITH.ALL; > > use IEEE.STD_LOGIC_UNSIGNED.ALL; > > > entity somme is > > Port ( clk : in STD_LOGIC; > > din : in STD_LOGIC_VECTOR (3 downto 0); > > taille : in STD_LOGIC_VECTOR (2 downto 0); > > > dout : out STD_LOGIC_VECTOR (3 downto 0) > > ); > > end somme; > > > architecture Behavioral of somme is > > type tab is array(3 downto 0) of STD_LOGIC_VECTOR(3 DOWNTO 0); > > signal s : tab; > > begin > > process(clk) > > begin > > if clk'event and clk =3D'1' then > > s(conv_integer(taille)) <=3D din; > > end if; > > end process; > > dout <=3D s(0) + s(1) + s(2) + s(3); > > end Behavioral; > > > -----------------------------------------------------------------------= ----=AD--------------------------------------------------------------------- > > my problem is : a simple addition for elements of an array !!! > > this programm is correct into syntax but not synthetisable and it dont > > give me the results that i want > > please i m a beginner and i want a clear way to think how to make > > this simple addition > > thank you > > Could it be that you haven't yet written all four elements of the array in > your simulation? At start, all four elements of s are 4'hX. All four > elements have to be written in order to obtain a valid dout. I am curious > about the (2 downto 0) on the taille input yet array(3 downto 0) on s. A= re > you trying to abbreviate: > if( NOT taille(2) ) then > s(conv_integer(taille(1 downto 0))) <=3D din; > end if; > or should taille be (1 downto 0) or should tab be array(7 downto 0) ? for taille : i have to calculate the sum of 4 elements so i need 2 bits to reference the elements ( the elements are for 4 bits) no?Article: 116606
Jeff Cunningham wrote: > I have a V4FX12 application that could potentially benefit from having > Gbytes of ROM data storage easily changeable through a CF card, so the > system ACE CF thing looks sort of interesting. > > We are trying to put together SW on a ML403 board based on xilkernel and > the lwip ethernet stack. I am wondering how hard it would be to give the > app access to a big table of data on the CF card. > > Maybe I'm not looking in the right place, but I've seen no example > designs or drivers for accessing the system ACE short of MontaVista > Linux. I've read the white paper and system ACE FAQ and skimmed the > datasheet. They don't come right out and say it, but give the impression > that the app must have FAT file system awareness to use the CF card. It > would be great if there were some simple way of accessing big table of > read-only data (as the configuration functionality obviously does). > > Has anyone here used the system ACE for generic storage? How was the > experience? > You could use xilfatfs which is another library shipped in EDK along with xilkernel & lwip. The accesses to CF itself will be slow, and the CF has to be formatted with FAT16 as explained here: http://www.xilinx.com/products/boards/ml403/reference_designs.htm Check the section "Restoring ML403 Demo Images". /SivaArticle: 116607
kangwei365@gmail.com wrote:
> Error (10334): VHDL error at tap.vhd(82): entity "tsb" is used but not
> declared
The *entity* tsb is missing.
That is causing the error.
You can not do this tsb instance:
TSB_1 : tsb port map(clk, Read_Data, tsb_out, First_oct);
without a tsb entity.
Next time consider using direct instances
instead of components.
-- Mike Treseler
Article: 116608My response isn't quoting properly so I'll top post to avoid confusion with the latest questions. I asked about taille because the input is dimensioned with three bits (2 downto 0) rather than 2 bits (1 downto 0). It's correct to use taille for an address but you're showing 3 bits to reference 4 elements. "VHDL_HELP" <abaidik@gmail.com> wrote in message news:1173806971.269800.43820@c51g2000cwc.googlegroups.com... On 13 mar, 18:05, "John_H" <newsgr...@johnhandwork.com> wrote: > > Could it be that you haven't yet written all four elements of the array in > your simulation? At start, all four elements of s are 4'hX. All four > elements have to be written in order to obtain a valid dout. I am curious > about the (2 downto 0) on the taille input yet array(3 downto 0) on s. > Are > you trying to abbreviate: > if( NOT taille(2) ) then > s(conv_integer(taille(1 downto 0))) <= din; > end if; > or should taille be (1 downto 0) or should tab be array(7 downto 0) ? for taille : i have to get an array of 4 elements so i need 2 bits to reference these elements ( the elements are represented with 4 bits ) no? that it is why i use taille isnt right?Article: 116609
With everyone else's previously mentioned comments in mind as well, I would recommend downloading Xilinx's webpack tool. Open their "Core Generator" software. Run the FFT core from there. You can enter in things like processing frequency, sample frequency, etc... and it will give you a resource utilization. You can also pull this information from the datasheet for their radix-2 fft core. I wish you the best of luck - but you may want to recommend that your boss consult a hardware engineer. With all do respect to software engineers (I can't write decent C code to save my life) despite what management likes to believe, FPGA design is hardware design, not software design. Without have a good deal of background experience in digital design, you're going to find it's difficult to make this kind of estimate accurately. Again, nothing against software folks, it's just a different set of training and experience that's required. On Mar 12, 3:18 pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: > rbbla...@gmail.com wrote: > > I'm absolutely new to FPGAs, in fact my work is much more related with > > the SW than with the HW, so I need to solve a problem that ideally I > > was not targeted to. > > The issue is this: I have to estimate (roughly) the number of FPGAs > > needed to support a typical signal processing algorithm, steps are as > > follows, always in single-precision: > > 1.16k complex samples FFT > > 2. 16k complex vector multiplication > > 3. 16k complex samples IFFT > > 4. 16k complex vector multiplication > > 5. 16 k complex vector sum > > The idea is to know how many FPGAs will cover this kind of processing > > in a given time, to compare with different types of processors. Por > > the later, it is really easy just counting number of operations in > > GFLOPs, but with hardware devices I am getting a lot of trouble, since > > I don't have a clear understanding on what should I count. > > First, floating point tends to be a lot bigger on FPGAs than fixed > point, especially floating point addition. If you can get away with > fixed point, even if the actual width is somewhat larger, it is probably > worth doing. > > Also, you can't just count 'FPGA', but you have to take into account > the size of the different FPGAs, even from the same product family. > > I like systolic array processors, which usually work well for this > type of problem. The thought process for hardware implementations, > especially good pipelined ones, is somewhat different than for software > implementations. Usually hardware implementations are used when > software isn't fast enough, so you need to know how fast it has to go. > > There is a tradeoff between time and size, but it isn't linear enough > to quote without more details. > > -- glen- Hide quoted text - > > - Show quoted text -Article: 116610
Poof ! The offensive paragraph is now gone for American and Asian registration also. Sanity prevailed! Peter Alfke On Mar 12, 1:22 pm, "Peter Alfke" <p...@xilinx.com> wrote: > Poof ! It's gone, at least for the European registration. > No more reason to delay your sign-up... > Peter Alfke > > On Mar 12, 7:37 am, "comp.arch.fpga" <ksuli...@googlemail.com> wrote: > > > I just stated in the comments box that I do not agree. > > In germany the hand written text should supercede the check box in a > > contract. > > > Kolja Sulimma > > > On 12 Mrz., 15:32, "Peter Alfke" <a...@sbcglobal.net> wrote: > > > > Let's see how fast Avnet can react. > > > The problem has been brought to their attention. > > > The clock is ticking... > > > Peter AlfkeArticle: 116611
John_H wrote: > But a printed manual wouldn't have any of the fancy hyperlinks that let you > cruise around the board with the click of a mouse! But i'm certainly using the ug230.pdf document as well. No question about it. But there is no real reason for the absence of the printed manual. Or maybe cut down $5-$10 of cost? Or is it more reasonable to bounce around the .pdf and the ISE environment all the time? OK, so give away all your books (your hardcopies). Would you like that? > You have to use the computer to work with the board - designing, > programming - why not use it to bounce around the .pdf to your heart's > content? I, for one, sincerely appreciated the ease of getting around the > manual with the help of the hyper-linked image and other internal > cross-references. A decent manual all around. I'm preparing some stuff for some end-users that are complete newbies (first lab for some students that involves any kind of board). I'm used to several different boards (ARM evaluator, ARM integrator, S3SK (this i actually bought), Altera Nios-II Stratix-II DK board) although i considered myself a (relative) newbie as well. This is the FIRST case of a board/kit without a single drop of printed manual/help!!! ONLY some dumpass evaluation versions. So what am i supposed to do with them? Eat them for lunch? I think that the X* guys enjoy their reign BIG TIME. UNTIL THEY FALL. And when they do, they'll do it the HARD way. An angry Xilinx customer PS: I, myself, suggested the S3E-SK here at the office, because i thought (and still believe) and it's a very good deal for the buyer. And we bought a certain amount for a lab. But no printed manual?Article: 116612
Uncle Noah wrote: > Hi > > i'm outraged! Those guys from the X* company STOPPED DELIVERING > printed manuals with their boards!!!! > > This is not right. For $149 plus international shipping rates, I > demand a printed manual as well!!! > > What is your opinion? Does this happen for all (after mid 2006) Xilinx > boards? I thought this had already happened, some years back, on most low-cost eval level systems ? Some vendors now off-load their manuals to a Web printing company, who have a library of PDFs and they print/bind a book, just for you. [for a fee, of course] -jgArticle: 116613
Hi All, I've found a wonderful tool for QEMU+SystemC cosimualtion: http://cephis.uab.es/proj/public/qemu/ However as my students are more familiar with VHDL, than with SystemC, I'm looking for a similar solution based on VHDL simulator (preferrably GHDL). Has anybody tried to use QEMU or UML (user mode Linux) together with GHDL for hardware-software cosimulation? What is the efficiency of such solution? -- TIA & Regards, Wojtek ZabolotnyArticle: 116614
Comments embedded: "Uncle Noah" <nkavv@skiathos.physics.auth.gr> wrote in message news:1173812349.741687.91190@64g2000cwx.googlegroups.com... > > John_H wrote: >> But a printed manual wouldn't have any of the fancy hyperlinks that let >> you >> cruise around the board with the click of a mouse! > > But i'm certainly using the ug230.pdf document as well. No question > about it. But there is no real reason for the absence of the printed > manual. Or maybe cut down $5-$10 of cost? > > Or is it more reasonable to bounce around the .pdf and the ISE > environment all the time? > OK, so give away all your books (your hardcopies). Would you like > that? Actually, I don't work from hardcopies anymore. Only a few ancient reference texts are at home in hardcopy, rarely referenced but there for safekeeping. I gave up my bookcase full of data books when I moved 7 years ago and haven't accumulated any more references (unless you count company training). >> You have to use the computer to work with the board - designing, >> programming - why not use it to bounce around the .pdf to your heart's >> content? I, for one, sincerely appreciated the ease of getting around >> the >> manual with the help of the hyper-linked image and other internal >> cross-references. A decent manual all around. > > I'm preparing some stuff for some end-users that are complete newbies > (first lab for some students that involves any kind of board). I'm > used to several different boards (ARM evaluator, ARM integrator, S3SK > (this i actually bought), Altera Nios-II Stratix-II DK board) although > i considered myself a (relative) newbie as well. This is the FIRST > case of a board/kit without a single drop of printed manual/help!!! > ONLY some dumpass evaluation versions. So what am i supposed to do > with them? Eat them for lunch? The reference design examples found at http://www.xilinx.com/products/boards/s3estarter/reference_designs.htm aren't limited to Xilinx-generated material. I haven't gone through them myself but did use the initial design as a starting point to add my own modifications for the LCD driver, for instance. The Starter kit's primary goal from my perspective (as a Xilinx user) is to get some hands-on with the part, not necessarily to educate the student in the art of FPGAs. The board was designed partly or wholly by the folks at digilentinc.com - a company dedicated to making FPGAs accessible to students in addition to intustry. There was a post on this newsgroup recently that pointed out material on the digilentinc.com website that's useful in the teaching environment. You might find better student-oriented material directly from them as opposed to Xilinx; it is their main focus, after all. My S3E starter kit is at home so I can't verify the kit contents. The PCIe eval board comes with an "Introduction to Programmable Logic" book (192 pages) that isn't board specific. The S3-1600E board (similar to the starter kit) I got directly from Digilent. While the same board from Xilinx (packaged with specific software) comes with additional documentation, the board from Digilent came with just the raw board and power supply. > I think that the X* guys enjoy their reign BIG TIME. UNTIL THEY FALL. > > And when they do, they'll do it the HARD way. > > An angry Xilinx customer > > PS: I, myself, suggested the S3E-SK here at the office, because i > thought (and still believe) and it's a very good deal for the buyer. > And we bought a certain amount for a lab. > > But no printed manual? I'm sorry that the item you consider crucial to the proper use of the board in your environment wasn't included. Any manual would end up tossed aside by a user like me. The cost of the manual would be shouldered by all purchasers for what ends up as a few people who need it. Is it too much to have the .pdf printed? Is there a concern that the rights aren't there to reproduce the manual for the students' use? I'm certain Xilinx would work with you to give you the allowances you need to get things done; the University Access program I've heard about might be a good contact point. And find out what Digilent has or can do. - John_HArticle: 116615
Michael Jørgensen wrote: > "KJ" <kkjennings@sbcglobal.net> wrote in message > news:QPcHh.3095$iw4.17@newssvr23.news.prodigy.net... > >> If FPGA/CPLDs cobbled together LUTs to create flip flops the same argument >> could be made for not using flip flops. But since FPGA/CPLD/ASICs all >> have flip flops implemented as hard logic you don't have this issue. >> Also, if the target device does have a hard latch as a resource that can >> be used then the use of latches is just fine also. >> > > So, just making sure I understand this. The synthesis tool may or may not > choose to generate a "latch inference" warning, depending on whether a latch > is natively supported by the target device. > > And the reason for this warning is that it is not possible to reliably > implement a latch, unless the target device has built-in support for it. > > Is the above correct? > > -Michael. That is pretty much it. If you look at Xilinx's FPGA datasheet, most families' slice FFs have an FF/latch configuration bit, which I presume (I do not remember trying to infer latches on FPGAs) means slice FFs can be configured as latches. The problem then becomes one of generating a suitable latch enable pulse. To prevent disorderly feedback (as you would in a latch-based counter) while the latches are enabled, this enable pulse needs to be very short and will be problematic on FPGAs since FPGAs are not particularly good at generating, distributing (on anything other than clock nets) and handling sub-nanosecond signals. You are better off sticking with FFs in FPGAs/CPLDs and even ASICs (unless extreme power and area conservation are primary preoccupations) unless you have very specific/unusual reasons to do otherwise - in programmable logic, the whole FF is there and using power either way.Article: 116616
S.T. wrote: > Hi Andy and all the nice guys who answered > > I cought a bad cold and was mainly listening to my pillow. Sorry for this > delay, i really appreaciate this feedback! > >> a) don't do this as a state machine -- you need to make the write >> process(es) separate from the read process(es) (or at least keep the >> read logic in a process separate from the write logic). One important >> point is that an FPGA's "single-port RAM" still has separate data-in >> and data-out ports (unlike a regular RAM chip, which has one >> bidirectional data port). This means that you don't have to worry >> about bus contention, etc., and you don't need a read enable. The read >> side code is simply > > I am aiming for the synthesis of dual-ported block ram. Am i right that your > comments aim at single ported ram? > >> b) The read has to be synchronous; otherwise it won't use block RAMs. > But in my book the read is synchronous? > > I have rewritten the stuff with your suggestions, still no success. Any more > ideeas, why the code below is not synthesized as block ram from xilinx xst > but as distributed ram? Does the code synthesize any sort of memory at all? To me, it looks like XST may have analyzed the code, determined that the memory was unnecessary and either optimized it away or replaced it by a few FFs. This is usually caused by undriven, unused and constant-value nets. XST also has a tendency of being quite overzealous with reorganizing pipelines and I have seen it manage to optimize away large chunks of nets and logic I had plugged on pseudo-random generators to prevent trivial optimization while sizing partial design implementations. If you want to prevent such optimizations, you have to make your controls and data depend on IOBs. When I infer BRAMs, my processes look like this: ---------------------- process(clk) begin if(rising_edge(clk)) then doA <= ram(conv_integer(addrA)); if(weA = '1') then ram(conv_integer(addrA)) <= diA; end if; end if; end process; ---------------------- This would be a read-before-write single-ported RAM on Spartan3, V4 and V5 but dual-ported on older Xilinx devices that do not support read-before-write access. For older devices, the write-before-read policy must be used and that code looks like this: ---------------------- process(clk) begin if(rising_edge(clk)) then if(weA = '1') then ram(conv_integer(addrA)) <= diA; doA <= diA; else doA <= ram(conv_integer(addrA)); end if; end if; end process; ----------------------Article: 116617
Hello Uncle Noah, I'm sorry you found the lack of a printed manual to be a hindrance in using our Spartan-3E Starter Kit. I can sympathize with you, because I much prefer to read paper, and somehow find it difficult to read detailed technical documents from the screen. As pointed out by others, a printed document would make the kit more expensive for everybody. Another concern (although not a major issue) is that electronic delivery of the documentation allows us to get the kit to market faster and also more easily maintain the document when we need to make changes/corrections. For all these reasons (and more, including "ease of use" for most customers) Xilinx decided to stop including printed manuals with the Spartan-3 Generation Starter Kits. I am also using UG230 extensively in a class I teach at SJSU. You can read more about the class here: http://www.engr.sjsu.edu/crabill where I have UG230 and my handouts (including a tutorial) in PDF format on-line. You are welcome to re-use anything that might help you. For a number of semesters, I had offered to have documents printed at the student print shop (including the board's user guide) if there was sufficient demand from the enrolled students. Even though I am not the copyright holder for the board's user guide, I figured Xilinx would not prosecute me for helping students learn how to use Xilinx FPGAs. I never received more than a handful of requests so I stopped asking -- and figured people who wanted a paper copy could go to the student print shop with a PDF file and get one made for about $10. EricArticle: 116618
Venu wrote: > As suggested by John, I replaced the BRAM generated by Xilinx Core > Generator with a Xilinx Primitive RAMB16_S9_S36. I did not change any > logic surrounding the memory modules. Now my memory is being addressed > in the ROW ORDER fashion. ( i.e. as expected from the Xilinx > Documentation ) > > I am not sure if the problem is with the address bit ordering , > because then the error should have shown up in both the > implementations . i.e. with the Core Generator as well as with the > Primitve. > > The only problem with using the primitive is that now I am using a > memory block of 1024 x 8 as opposed to the 128 x 8. That is eating up > a lot of the resources which I need in other modules. > > Thanks > Venu BRAMs are atomic 18kbits resources, any parts of them you do not use on either of their two ports are lost/wasted. With 1024x8 and 256x32 ports with overlapping ranges to produce a 8kbits 4:1 multiplexing memory, you are still wasting half a BRAM that nothing else in your design will ever be able to access. Unless you need to sacrifice address bits to improve timings, using 100% of a BRAM usually requires very little extra effort and resources, although it can sometimes be obscene overkill. It would be nice if V6/S4 introduced 1kbit BRAMs/FIFOs (1x1024 to 32x32 aspect ratios), at least in the first and last BRAM column where they could conveniently be used as flexible IO FIFOs. These would neatly complement ISERDES/OSERDES & all.Article: 116619
Hi, Has anyone had any success in programming a Xilinx XCF using C code in a MicroBlaze over the JTAG ports? Any information appreciated. Thanks!Article: 116620
4balaji@gmail.com wrote: > hi,this is balaji .I am doing my final year project using kcpsm3 > (picoblaze).Any one sugg. any application using this core.Which i can > complete in around 20 days. > thank u ,for responding > Display "Hello World" on an LCD? If your board has an AC97 chip, program the picoblaze to use button and LCD to build a simple volume controller. Or instead of the switches, you could put together a PS/2 keyboard or mouse interface instead and maybe even an RS232 serial console. Do some DSP between input and output if you want - program some BRAMs with FIR filter coefficients and select the filter(s) using whichever input method(s) you implemented. For a 20 days student project, there isn't much time to go much more complicated than that. ~30 days would have been enough to start doing some interesting things with VGA graphics... it took me about a week to build an usable VGA text console from scratch (except for the 8x8 character table ripped from my video card's BIOS) the first time around, after which I spent a few more days rewriting it clean, ruggedized and neatly pipelined for future-proofing so there wouldn't need to be a second time around. Be wary of ambitious projects, as they can be highly susceptible to massive temporal inflation.Article: 116621
can some one give me a hint on how to interface AD9229 a to d converter with stratix II lvds interface? the AD9229 output sample word of 12 bits, however the lvds serdes factor is 10 at the max. -thanksArticle: 116622
Hello Greg, thank you for your feedback. We do have to consider vibrations. I think the standard says something like [50Hz-500Hz]/3G. But it is a telecom test equipment that will be horizontal and static. So not so bad. Reading you, screws is the right option. Makes sense. PCB will have to be reinforced from underneath. To control the force that is applied by the scew, Xilinx mentions some spring based mechanism that prevents the screw to deform the solder balls. Thank you for taking the time to send me this. Jean-BaptisteArticle: 116623
Thanks Daniel! Daniel S. a =E9crit : > Ray Andraka wrote: > > jean-baptiste.nouvel@jdsu.com wrote: > > > >> Hi, > >> > >> Anybody has experience with heatsinks on FPGAs? > >> > >> In the V5 documentation, Xilinx says the heatsink can be glued to the > >> FPGA but that it > >> is safer to screw it to the board to avoid mechanical contraints to > >> the FPGA > >> ball when under vibrations. > >> > >> But then the screws take some space on the board that we can't really > >> afford... > >> This would be at the expense of signal integrity (longer PCB > >> tracks...). > >> > > I've been putting heatsinks on FPGAs for quite a while, including > > heatsinks with fans on them. Gluing is fine for in the lab, but if it > > is going into the field, you'll want a better mechanical connection to > > the FPGA if the heat sink has any mass to it. That can be done with > > screws to the board, or with some arrangement of springs on the chassis > > if your mechanical arrangement allows it. You could also fabricate a > > hold-down bracket that screws to the board, thereby only taking a little > > bit of board real-estate at two points (one we did had a bracket that > > went diagonally across the heatsink and held to the board with two scre= ws). > > Another small heatsing fastening method I have seen is a simple torsion b= ar hooked into a > pair of through-hole eyelets placed on opposite sides. PCB real-estate fo= r a pair of these > is something like 3-4 square milimeters. No screws, easy to service, negl= igible PCB area > and the eyelet tabs can be however long as necessary to clear nearby SMT = components.Article: 116624
"wzab" <wzab01@gmail.com> wrote in message news:1173815283.821184.126840@c51g2000cwc.googlegroups.com... > Hi All, > > I've found a wonderful tool for QEMU+SystemC cosimualtion: > http://cephis.uab.es/proj/public/qemu/ > However as my students are more familiar with VHDL, than with SystemC, > I'm looking for a similar solution based on VHDL simulator > (preferrably GHDL). > Has anybody tried to use QEMU or UML (user mode Linux) together with > GHDL for hardware-software cosimulation? What is the efficiency of > such solution? Hi Wojtek, I might be missing the point here, but why do you want to use such a complex solution for software/hardware co-simulation? Can you just install and run SystemC standalone? I wouldn't worry to much about the lack of SystemC knowledge since at the low level there is a lot of similarity between SystemC and VHDL (and Verilog). You can easily write SystemC at the "rtl" level but you might loose a lot of performance. Personally, I would give my students a quick course on SystemC. Then for their project work I would show them some standard templates for say FF, FSM's Counters, Instantiations etc and also show them how to write a testbench that dumps some VCD signals. Alternatively, speak to Mentor and see if they can give you a SystemC license for their student edition of Modelsim (http://www.model.com/resources/student_edition/student_download.asp). In this case you can mix VHDL and SystemC with is very simple :-) Hans www.ht-lab.com > -- > TIA & Regards, > Wojtek Zabolotny >
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