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On 15 Mrz., 10:12, Philip Freidin <phi...@fliptronics.com> wrote: > "Honey, I'm going to off with my mistress for the day" , and then > getting caught on film sitting at an X-Fest, studiously taking > notes, surrounded in a sea of engineers! "Yeah. If you have a wife and a mistress, they will each assume you are spending time with the other woman, and you can go to the lab and get some work done." Kolja SulimmaArticle: 116676
If you were analyzing a newer part, you could make use of 'debit', a tool available from http://www.ulogic.org/trac. I have only given it a cursory look, but it appears to reverse a bitstream into a custom textual netlist. So additional work would be required to take it to EDIF, XDL, or the like. But it does draw pretty fpga_editor-like pictures from bitstreams. Stephen On Mar 15, 6:09 am, "jbnote" <jbn...@gmail.com> wrote: > > Reverse engineering is generally very difficult, but it could perhaps be > > possible to extract the netlist, i.e. the low-level connections between the > > individual registers, LUTs, etc. Not that I have the skill/time/knowledge, > > but perhaps someone else has already done something similar. > > Oh. That would be *nasty*. > > JBArticle: 116677
> > 3) Additional timing paths. Sometimes the timing report is not > showing > your normal clock-to-output delay but rather the reset to output > delay. > This occurs if your reset term is synchronous to the clock. Thus for > example if rst_n was created on a rising edge of i_clk, the timing > report > will see a path from i_clk to rst_n through the reset of the output > flip-flop and finally to the output pad. Usually this is not a path > that needs to meet your OUT AFTER specification. You can use TIG on > your reset nets to avoid this. You can see this in the timing report > if you look at the path that fails and see the reset net somewhere in > the chain. However, if you take the TIG approach on synchronous reset nets, you might find out that the post-place-and-route simulation does not work. This might happen if the path between the reset flip-flop and the reset input of any other flip-flop is about the length of your clock period. In this case there will be a violation on reset input with respect to clock input, throwing an unknown at the output that will never be recovered, trashing all your simulation. There might be approaches to avoid this, but I don't know them. I only use TIG for asynchronous resets where you cannot predict when the reset signal will actually happen. Later I play with the reset timing in the testbench to make sure it does not interfere with the operation of my circuit during simulation. In general, I think it's good to add the following lines to your UCF file: ENABLE = reg_sr_q; NET "nreset" TIG; where "nreset" is an asynchronous signal. The "reg_sr_q" option enables the analysis of paths through the Reset and Set pins of your synchronous elements. The "nreset" signal will not be analysed since you TIG'ed it. However, any other synchronous resets that you might generate inside your circuit will be analysed to make sure things work as expected. Please correct me if I'm wrong. Regards.Article: 116678
Try to ask something more concrete.Article: 116679
In my case the clk frequency is 4.4MHZ, I need to have 5secs,10secs and 25secs delay,from my calculation the required is 20 bit counter,I have written the code below module delay(osc,count); input osc; output [19:0]count; reg [19:0]count; reg inter; always @(posedge osc) begin count <= count + 20'b00000000000000000001; end endmodule here i am not understanding how to use the delay from this counter.Is this is the correct way of coding? If not can you please post the correct code regards vishnuArticle: 116680
Hello, I would like to know if anyone experiences this misfunction in Xplorer tool. I'm using Xilinx ISE 8.2i. When I use Xplorer, it always finds the right implementation parameters on the third run (the report is attached below). Then it tells me that the best parameters will be updated in my project configuration within ISE. I check the command line that succeded (in 3rd run), and I check my configuration in ISE. They seem to match. However, if I inmediately implement it with those parameters without using Xplorer, my timing constraints are not met anymore. Does anyone know why this happens? Regards. ------------------------------------------------------- FPGA Xplorer (tm) Version 8.2.02i 2007-03-14 17:33:25 Command: xplorer mydesign.ngc -wd=/FPGA/synthesis -sd=. - uc=mydesign.ucf -p=xc2v2000-ff896-4 -max_runs=7 -intstyle=ise - ise=myproject.ise --------------------------------------------------------------------- Run 1 --------------------------------------------------------------------- Map options : -p xc2v2000-ff896-4 -timing - ol high -xe n Par options : -w -ol high -xe n Achieved Timing Score : 3419.00 Current Best (Lowest) Timing Score : 3419.00 Current Best Run : 1 --------------------------------------------------------------------- --------------------------------------------------------------------- Run 2 --------------------------------------------------------------------- Map options : -p xc2v2000-ff896-4 -timing - ol high -xe n -register_duplication -logic_opt on Par options : -w -ol high -xe n Achieved Timing Score : 3419.00 Current Best (Lowest) Timing Score : 3419.00 Current Best Run : 1 --------------------------------------------------------------------- --------------------------------------------------------------------- Run 3 --------------------------------------------------------------------- Map options : -p xc2v2000-ff896-4 Par options : -w -ol high -xe n Achieved Timing Score : 0.00 Current Best (Lowest) Timing Score : 0.00 Current Best Run : 3 --------------------------------------------------------------------- --------------------------------------------------------------------- BestRun : Run 3 --------------------------------------------------------------------- Map options : -p xc2v2000-ff896-4 Par options : -w -ol high -xe n Achieved Timing Score : 0.00 ---------------------------------------------------------------------Article: 116681
ravipativishnu@yahoo.co.in wrote: > In my case the clk frequency is 4.4MHZ, I need to have 5secs,10secs > and 25secs delay,from my calculation the required is 20 bit counter,I > have written the code below > > module delay(osc,count); > > input osc; > output [19:0]count; > reg [19:0]count; > reg inter; > > always @(posedge osc) > begin > count <= count + 20'b00000000000000000001; > end > endmodule > > here i am not understanding how to use the delay from this counter.Is > this is the correct way of coding? If not can you please post the > correct code > > > regards > vishnu > Hi Vishnu, You can't use a counter to delay the execution of statements in a software sense. You have to design a state machine for the functionality you want. For example, you can test the top bit of the counter every cycle and use it to trigger another event every 2^20 cycles. I think you have a fundamental misunderstanding how Verilog (and HDLs in general) work. Maybe take a look at the verilog tutorial at: http://www.asic-world.com/verilog/veritut.html RobArticle: 116682
"Daniel S." <digitalmastrmind_no_spam@hotmail.com> wrote in message news:Yy1Kh.140731$1%3.1893286@weber.videotron.net... > > I am still puzzled that Xilinx happily subsidizes $1300 to put these > boards into future logic engineers' hands and into universities' labs but > makes accessing the necessary tools so impractical. I heard even Xilinx's > sales reps are surprised when they hear about this situation for the first > few times. > > IMO, missing software easily tops a 'missing' printed manual. Like others > here have said, I prefer the searchable digital format. If I find myself > repeatedly referring to specific sections (like schematics), I can print > them as necessary and any way I want... from two pages per side duplex on > 8.5x11 for plain text to 11x17 for schematics. Considering universities can request the full tools for free its not a problem. http://www.xilinx.com/univ/ http://www.xilinx.com/univ/dtools.htm We have a xup board and have everything we need to work with it include ise , system generator , edk and chipscope pro. Its great that xilinx provides their tools like this. Its one if the reasons we still use xilinx cplds in the undergraduate course for programmable logic (its certainly not due to the schematic editor). Now if anyone knows of a good xilinx based sdr(software defined radio) kit, that would be a big help. Most of the visible fpga sdr projects seem to be using altera fpga's. AlexArticle: 116683
Need to find a decent fpga sdr board or kit - preferably xilinx. Trying to buy a premade kit rather than assembling our own (if possible). We have had a look at the lyrtech sdr boards and these are a bit limiting /don't meet the project needs. (adc not fast enough and to low rf output frequency) Looking at 4G mobile phone systems research. Thank you AlexArticle: 116684
thanks rob I will try coding my project using state machines ,still i have one doubt I am using QUARTUS-2 software in this events are not synthesizable so how to take care of events in that. regards vishnuArticle: 116685
"Pablo" <pbantunez@gmail.com> writes: > Hi everybody, I am working with Sundance modules, specifically I have > adquired Smt338vp30 which has a Virtex II Pro 30 (ff896-6). I have > bought Diamond FPGA too, but I need to work with the PowerPC builts in > the FPGA, so I have decided to use Xilinx EDK and ISE for this. I have > asked Sundance for Constraint (UCF) files to program it but at this > moment I have no experience with this kind of boards. > > Can anyone tell me if he/she has some experience with it ?? > We've used an SMT374, which has a V-II (non-pro) and 2 C6713 DSPs on. If you want to use EDK, you'll need more than a UCF though - you need a board description file for EDK to work with. Sundance may or may not have one. You can always write your own though... Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 116686
On Mar 15, 6:45 am, ravipativis...@yahoo.co.in wrote: > always @(posedge osc) > begin > count <= count + 20'b00000000000000000001; > end > endmodule > > here i am not understanding how to use the delay from this counter.Is > this is the correct way of coding? If not can you please post the > correct code Add an "if" clause to your always block which executes its enclosed statements only when the counter equals a particular value.Article: 116687
Hi John
You really made my day :-)! Tell me if you are around Darmstadt, Germany and
i will get you an drink of your choice ;-). (Yes, i know it's improbable,
but sometimes the world is a small place...)
> Since you want a dual-port rather than a single port, try defining two
> addresses (I'd use syn_keep attributes in Synplify) rather than using
> "addr" for both the read and the write.
>
I just hit the nail on the head. I am really happy that there is no need now
to explicitly instanticate block ram. After finding out that it's working i
tried removing the read and write processes. It didn't work. So i think
both suggestions:
* doing seperate processes for read and write access
* using seperate adresses (even if identical) for the read and write access
lead to the success.
> Also, is ramstyle "block" as opposed to "BlockRAM"?
>
It works for me (tm). I think copied this statement right out of the xst
manual.
Thanks to all who have taken time to help out.
ST
XST output:
Found 1024x16-bit dual-port block RAM for signal <RAM>.
-----------------------------------------------------------------------
| ram_style | block | |
-----------------------------------------------------------------------
| Port A |
| aspect ratio | 1024-word x 16-bit | |
| mode | write-first | |
| clkA | connected to signal <CLOCK> | rise |
| weA | connected to signal <we> | high |
| addrA | connected to signal <w_addr> | |
| diA | connected to signal <di> | |
-----------------------------------------------------------------------
| Port B |
| aspect ratio | 1024-word x 16-bit | |
| clkB | connected to signal <CLOCK> | rise |
| enB | connected to signal <re> | high |
| addrB | connected to signal <r_addr> | |
| doB | connected to signal <do> | |
-----------------------------------------------------------------------
corresponding test code:
entity BRAM_test is
port (CLOCK : in std_logic;
reset : in std_logic;
di : in std_logic_vector(15 downto 0);
do : out std_logic_vector(15 downto 0));
end BRAM_test;
architecture syn of BRAM_test is
type ram_type is array (1023 downto 0) of std_logic_vector (15 downto 0);
signal RAM : ram_type;
attribute ram_style : string;
attribute ram_style of RAM: signal is "block";
type STATE_TYPE is (P1, P2, P3 );
signal STATE : STATE_TYPE;
signal we: std_logic;
signal re: std_logic;
signal w_addr : std_logic_vector(9 downto 0);
signal r_addr : std_logic_vector(9 downto 0);
begin
main : process (CLOCK, reset)
begin
if (CLOCK'event and CLOCK = '1') then
if (RESET = '1') then
STATE <= P1;
w_addr <= (others => '0');
r_addr <= (others => '0');
we <= '0';
re <= '0';
else
case STATE is
when P1 =>
we<='1';
STATE <= P2;
when P2 =>
we<='0';
re<='1';
STATE <= P3;
when P3 =>
re<='0';
we<='0';
w_addr <= w_addr + '1';
r_addr <= r_addr + '1';
STATE <= P1;
end case;
end if;
end if;
end process main;
ram_write: process (CLOCK)
begin
if (CLOCK'event and CLOCK='1') then
if(we='1') then
RAM(conv_integer(w_addr)) <= di;
end if;
end if;
end process ram_write;
ram_read: process (CLOCK)
begin
if (CLOCK'event and CLOCK='1') then
if(re='1') then
do<=RAM(conv_integer(r_addr));
end if;
end if;
end process ram_read;
end syn;
Article: 116688
You didn't mention if you're using a DCM to buffer/deskew the input
clock. If you aren't using one, you have multiple sources for your
output delay:
a) the clock delay caused by the going through the input buffer and
BUFG onto the global clock line
b) the clock-to-Q delay of the flop
c) the delay from the flop to the output pad.
As a previous poster mentioned, make sure you have the tools set to
map the
flop into the IOB to eliminate routing delays (item c) above.
Item (a) can be a fairly large.
John Providenza
n Mar 14, 4:38 am, "uvbaz" <u...@stud.uni-karlsruhe.de> wrote:
> hi,
>
> I want to operate the XILINX Virtex-4 XC4VLX60(Speed -12) at a
> frequenz of 130 MHz. So i write the following constraints to my
> UCF(user constraint files).
>
> NET "i_clk_adc" PERIOD = 6 ns HIGH 50 %; # clock periode,
> 6ns(about 160MHz)
> OFFSET = IN 3 ns BEFORE "i_clk_adc" HIGH ; # Input signal must be
> ready, 3 ns before rising edge
> OFFSET = OUT 5 ns AFTER "i_clk_adc" HIGH ; # Output signal must be
> at the PAD, 5 ns after the rising edge.
>
> However, the constraints OFFSET = OUT 5 ns AFTER "i_clk_adc" HIGH ;
> cannot be met. Actual timing is about 7.8ns.
>
> The specification from XILINX says that, this device can be operated
> at about 300MHz. Why i cannt achieve this timing level?
>
> This is the code, i use this to test the device:
>
> output: PROCESS(rst_n, i_clk)
> BEGIN
> IF(rst_n = '0') THEN
> o_data <= '0';
> cnt_exp <= '0';
> ELSIF(RISING_EDGE(i_clk)) THEN
> cnt_exp <= NOT cnt_exp;
> IF(cnt_exp = '0') THEN
> o_data <= '0';
> ELSE
> o_data <= '1';
> END IF;
> debug_data <= i_data;
> END IF;
> END PROCESS;
>
> Thanks
> Cheng
From Tim@spamtrap.com Thu Mar 15 07:05:12 2007
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From: "Tim" <Tim@spamtrap.com>
Newsgroups: comp.arch.fpga
References: <1173807047.4904.0@proxy02.news.clara.net> <diVJh.28222$g24.5863@newsfe12.phx>
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"Colin Hankins" <Colin.Hankins@touit.com> wrote in message
news:diVJh.28222$g24.5863@newsfe12.phx...
>> 1 Detect phase to see if there's a receiver connected
>> 2 Send TS1s
>> 3 Send 1024 TS1 after at least one TS1 has been received
>
> Step 2 and 3 are combined and the transmitter must send 1024 TS1's and 8
> TS1 or TS2's must be received.
>
>> 4 Send TS2s and continue to send them until 8 TS2s have been received
>> 5 Send a further 16 TS2s
>
> Step 4 and 5 are combined as the count of 16 TS2's sent begins after
> receiving 1 of the 8 consecutive TS2's
>
>> 6 Send TS1s and wait for 2 TS1s with Link number rather than PAD symbol
>> 7 Return TS1s with Link number and wait to receive 2 TS1s with Lane
>> number
>> 8 Return TS1s with Link and lane number
>
> the lane number sent in step 8 may be different than the lane number
> received in step 7.
>
> 9 Continue sending TS1s with link # and lane #, wait for receipt of 2
> TS1's with same link # and a lane # different than the lane # beign
> transmitted, or receipt of 2 TS2's
> 10. Continue sending TS1s with link # and lane #, if 2 TS2's with matching
> link and lane numbers are received, move to next step. Otherwise if 2
> TS1's are received with matching link numbers and some of the lanes have
> matching lane numbers or are receiving TS1's with non-PAD lane numbers,
> make a decision about the number of usable lanes and go back to step 9.
> 11. Send TS2's with the link and lane numbers from the received TS2's.
> Must receive 8 TS2's with matching link and lane # and must send 16 TS2's
> after receiving one TS2
> 12. Send Idle data and transition to L0 after receiving 8 consecutive idle
> data symbols and transmitting 16 idle data symbols after receiving 1 idle
> data symbol.
>
>
> There are some other details, such as polarity inversion, N_FTS, and other
> configuration information, but as far as a straight shot initialisation,
> that is the gist of it.
>
> Colin
Many thanks for your reply - it's given me some confidence.
Article: 116689<stephen.craven@gmail.com> wrote in message news:1173957648.352542.207980@n76g2000hsh.googlegroups.com... > If you were analyzing a newer part, you could make use of 'debit', a > tool available from http://www.ulogic.org/trac. The link appears broken (Page not found), and the home page only displays "It works". Are you sure the link is correct? -Michael.Article: 116690
On Wed, 14 Mar 2007, Jonathan Bromley wrote: "On 14 Mar 2007 17:17:03 GMT, Colin Paul Gloster <Colin_Paul_Gloster@ACM.org> wrote: [..] > A circuit which is described >as "combinatorial" or its "combinational" in literature is one which >does not have an output of its as an input of its, unlike a >"sequential" (not in the VHDL sense) circuit. No-one was calling the *circuit* combinational; it's the *loop* that Kevin was so describing. In doing so he was conforming to long-established usage in the synthesis community for the description of any cycle in the network that is not broken by an explicit storage element. [..]" Thanks for the information.Article: 116691
I've taken the website down. I was not expecting the link to be spread. I'll do an announcement here when i'm ready for public release. JBArticle: 116692
On Mar 15, 11:40 am, "Bob Golenda" <bgoli...@nospam.net> wrote: > Of course, using GPIO pins. > > But, the question is, has anyone actually gotten this to work? I've done it with a Xilinx Spartan 3 programming from the .bit file (using a modification of the open source XC3Sprog package) and for Altera EPC4 config flash and also directly the Stratix-II FPGA, from .jam files using a modification of Altera's open source jam player. I haven't done a Xilinx config flash, but I don't imagine that would be too hard - one would just modify their reference XSVF player to control your microblaze as a proxy, or to run on your microblaze.Article: 116693
Hi, Here there are some examples in Verilog of functions DSP for FPGAs, some of these are: http://www.altera.com/support/examples/verilog/verilog.html * Achieving Unity Gain in IFFT+FFT Pair Using Block Floating Point Arithmetic * Fast Fourier Transform (FFT) With 32K-Point Transform Length * Coefficient Reload Finite Impulse Response (FIR) Filter * Discrete Cosine Transform (DCT) * Basic FIR Filter * Time Domain Multiplexed FIR Filter * Polyphase Decimation FIR Filter * Polyphase Interpolation FIR Filter * Two-Dimensional FIR Filter * Basic Infinite Impulse Response (IIR) Filter * Butterworth IIR Filter * Magnitude FunctionArticle: 116694
Hi, Of course, using GPIO pins. But, the question is, has anyone actually gotten this to work? Thanks! <cs_posting@hotmail.com> wrote in message news:1173909021.616924.228790@n76g2000hsh.googlegroups.com... > On Mar 13, 8:34 pm, "Bob Golenda" <bgoli...@nospam.net> wrote: > > > Has anyone had any success in programming a Xilinx XCF using C code in a > > MicroBlaze over the JTAG ports? > > Not exactly, but some closely related things, such as programming FPGA > and config flashes whose JTAG signals have been connected to GPIO pins > of ordinary (hardware) microcontrollers. > > I don't think you'll be able to program the config flash by driving > the FPGA's jtag pins, so you would need some seperate connections from > ordinary I/O pins. > > Once your microblaze can twiddle the config flash's jtag signals, you > have a software problem. My preferences has been to make the embedded > device behave like a jtag cable with some macro commands and act as a > proxy for a program running on a PC. You could of course embed the > whole thing, but that means putting the algorithm and the data into > the embedded processor. Your microblaze system may have the resources > for that, my embedded targets don't, so I use a much smaller block of > code that acts as a proxy. >Article: 116695
Hi Marc, Have you actually done this and gotten it to work? Thanks! <jetmarc@hotmail.com> wrote in message news:1173953588.688163.253930@o5g2000hsb.googlegroups.com... > > Has anyone had any success in programming a Xilinx XCF using C code in a > > MicroBlaze over the JTAG ports? > > You can do the following: > > - Use IMPACT and record the JTAG programming sequence to an XSVF file. > - Read XAPP058 and XAPP503 to learn about the XSVF file specification. > - Implement an XSVF player using C code in a Microblaze. > - Play the recorded JTAG programming sequence in your board. > > Using the batch mode of IMPACT, you can script this from your > makefile. > > Regards, > Marc >Article: 116696
rob.dimond@gmail.com wrote: > Hi, > > I'm working on a Virtex4 DDR2 interface based on the direct clocking > design from MIG 1.6 (XAPP701). I'm clocking the DDR2 (Micron 1Gb) at > 125MHz, so I would expect to see only one edge of DQS during > calibration using the IDELAY. However, from chipscope I see two edges > only approx 900ps apart. > I notice there are lots of IDELAY queries on here... can anyone > explain what is going on? > The design uses an IDELAYCTRL clocked at 200MHz from a DCM CLKFX with > a 50MHz clkin. > > The result is intermittant read errors, I suspect since the calibrated > data delay is totally wrong... > > Many thanks, > > Rob > Hi, I thought I would answer my own question in case anyone has a similar problem in the future. I wasn't resetting the IDELAYCTRL properly. The reset signal in the 200MHz clock domain is derived from the same reset used for the DCM itself, so is never asserted. According to the V4 user guide the behavior is 'unpredictable' without a reset... now I know what this means. Interestingly, some other reset signals in the MIG design look to have the same problem... RobArticle: 116697
Sorry for the slow reply - winter colds stink ;) I was actually hoping to get a list of the synthesized logic equations prior to conversion to the Xilinx primitives. I was able to get an EDIF netlist but that's a bit too far down the tool chain as what I want to look at is the optimized Boolean logic. Is that possible? I seem to recall that generic vendor tools like Synplify had the ability to export such information prior to the selection of a target technology. Adam On Mar 15, 2:33 am, Andreas Ehliar <ehl...@lysator.liu.se> wrote: > On 2007-03-15, John McCaskill <junkm...@fastertechnology.com> wrote: > > > Do you know if there is a way to get an xdl netlist back to an ngc > > netlist? > > Not that I know of. Well, you can use netgen to convert a .ncd > design to vhdl or verilog and it might be possible to synthesize > this one. However it would not contain routing information. > > > What I would like to do is to take some of my IO cores that I use on > > all of my designs and take them through PAR until I am happy with the > > results and then be able to use them as hard macros from then on. > > I've found conflicting information about routing in hard macros, > some says the routing cannot be locked down like the following:http://www.cse.ucsc.edu/classes/cmpe225/Fall01/hardmacro.html > > And some say that it is possible, such as a hard bus macro that is > used in partial reconfiguration. Perhaps you could download such > a bus macro and see how they are constructed? > > Mind you, I haven't tried this at all so I have no idea if it is > a good idea or not, but perhaps you could synthesize your I/O > macros one after one and place the result in one large XDL file which > you could then convert to NCD and use as a guide file for par. > It is a quite ugly solution though, there must be a better way. > > But if you find an easy way to create such hard macros I'd be > interested as well :) > > /AndreasArticle: 116698
> However, if I inmediately implement it with those parameters without > using Xplorer, my timing constraints are not met anymore. Have you tried running map and par with the xplorer parameters in command line mode (outside of the ISE GUI environment)? I suspect that there are some other options set by GUI, which xplorer doesn't use... /MikhailArticle: 116699
Hi, All The ChipScope gave me the message "Waiting for core to be armed" while the program can run on the board at the same time. I have a small test project which includes a MicroBlaze with a DCM, a RS232 interface and other necessary components. The DCM divides the input clock from 100MHz to 50Mhz. An application prints out something through the RS232 will be shown on the hyperterminal. It works fine on the board even after I insert the ILA core. But I just can't get any sample data. It is said on Xilinx web that this is because of clock. So I tried to connect the chipscope clock to different place, DCM feedback clock, input clock after global buffer. And I also include a second DCM with the exactly same configuration with the first DCM because I saw on the group somebody pointed out that DCM can't be locked when connected to both user logic and chipscope. I used the second DCM just for the Chipscope. I can't connect the the sys_clk_pin to the chipscope clock input direclty otherwise Xilinx will give me error because it is connected directly to non-global buffer logic in the ILA core. Can somebody give me any hint? I think my clock should works fine because I can see messages print out at hyperterminal. Thanks a lot, Rebecca.
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