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I used the latest version of MIG to generate pinouts for a Virtex 4 DDR2 interface. In addition to all the usual Address, Data, and Control I/Os, MIG assigned an I/O pin for a signal called SYS_RESET_IN_N. What is the function of this pin?Article: 131326
"Joel Koltner" <zapwireDASHgroups@yahoo.com> wrote: >"Hal Murray" <hal-usenet@ip-64-139-1-69.sjc.megapath.net> wrote in message >news:JdudnXIVmePbjJTVnZ2dnUVZ_vfinZ2d@megapath.net... >>> I always draw components with their actual >>>pin-outs. >> What does that mean? > >I suspect he means that the schematic symbol he draws have the pins arranged >with the same placement as that which occurs on the physical device. > >I've drawn some symbols like this at times, as it works OK for small devices, >but of course has problems as soon as someone hits the "mirror" button on your >symbol... and becomes intractable for devices with hundreds or even thousands >of pins. Mirroring is not allowed ofcourse :-) And yes, it won't work for BGA packages. The largest common QFP device is approx 200 pins which is still workable. -- Programmeren in Almere? E-mail naar nico@nctdevpuntnl (punt=.)Article: 131327
Dear all, I've designed a macro, and put "ring.nmc" file in my project dir. In my verilog module file, I wrote ... ring r1(.en(en),.ro(ro)); ... to instantiate ring macro, but failed. Any one could give some hint? Thank you!Article: 131328
Distributors nowadays are pushed to fairly tight margins so you may find won't a lot of interest in a low volume, low value, projects. Digikey mentioned elsewhere is good if you are in the small numbers production and even have stock in many cases. Stock is a rarer item at both NuHorizons and Silica/Avnet but sometimes they do have items. We use all three of these distributors can particularly fault any of them and use whatever one is most suitable for any given project. Distributors also like to "claim" projects as they get paid a margin on any project they support and hence all the questions they ask. If you want minimm hassle in this respect then Digikey wins. If you are on a high volume project then Nuhorizons or Silica will be the better open for volume purchases. John Adair Enterpoint Ltd. On 18 Apr, 19:17, "Raban" <or09...@hotmail.com> wrote: > Hello, > > I am new to this FPGA stuff and I wanted to purchase a starter kit and get= > volume pricing for a few Xilinx FPGA's > > If one where to buy through Avnet or maybe NuHorizons, would anyone like t= o > share your past experiences when working with them? > > It seems all they care are who you are, what company you work with, what y= ou > exactly are you doing. In other words, how many parts are you going to buy= > from us before I spend any time with you. > > Do you have to be a big company or are they trying to discourage small > startups or students or whoever? > > Like what do you have to purchase, software or hardware or what dollar > amount to do you have to purchase just to get =A0few questions answered, s= ales > wise for pricing or even worse, tech support? > > Thanks.Article: 131329
In article <3023a7dd-d8cc-40ec-9cc5-8d22b17ea2ec@c65g2000hsa.googlegroups.com>,
John Adair <g1@enterpoint.co.uk> writes:
|> Distributors nowadays are pushed to fairly tight margins so you may
|> find won't a lot of interest in a low volume, low value, projects.
|> Digikey mentioned elsewhere is good if you are in the small numbers
|> production and even have stock in many cases.
My experience with Digikey was a bit doubtful with respect to the "freshness" of
their stock. The first delivery of a few XC3S1600 in late 2006 was OK, so I built
my first prototypes, they worked perfect. The chips in the second delivery in
early 2007 had huge problems with the DCM. Either it didn't work at all or a
phase shift step killed it.
It took a while until I discovered that they had sent me A0-revisions. In A0 the
DCM is (IMO) quite useless as the maximum input and output frequency is only
90MHz... No wonder my 132MHz DDR-stuff didn't work...
--
Georg Acher, acher@in.tum.de
http://www.lrr.in.tum.de/~acher
"Oh no, not again !" The bowl of petunias
Article: 131330Joel Koltner wrote: > "Joerg" <notthisjoergsch@removethispacbell.net> wrote in message > news:tq7Oj.1556$FF6.588@newssvr29.news.prodigy.net... >> All I know from here (CA) is that their benefits are mind-boggling... > > Well, it's entirely reasonable to have retirement benefits for public > employees be comparable to what private companies offer... I just hope that > public employee salaries will then become comparable as well (which implies a > pay raise), since otherwise I don't see how the gov't. expects they'll get > comparable quality out of their workers. > Private companies generally offer zilch in retirement benefits. Those days are long gone. > One problem with the government seems to be that they don't expect their > employees to be agile over time. See this article: > http://www.gcn.com/print/24_30/37174-1.html -- Someone the government ends up > with a bunch of 70 year old programmers and therefore has to hire IBM to build > them the modernized e-filing systems? Surely there must be some new hires in > the past, say, 40 years who could have been working on this and hence, on > average, would only be middle-aged today!? > A 70 year old programmer can be better than a 40 year old. At least that's my impression when I see all the "modern" bloatware ;-) >> Oh, and then lots of jobs have the retirement benefit tied to the last work >> year. > > I expect that was implemented to help people who were *forced* to move? > > It seems like it needs reworking to differentiate between cases where the > government wants to move you vs. you just voluntarily wanting to do so. > Or you just have to have the right connections to make that happen ... Anyhow, why should retirement checks be based on the last year of service? IMHO that's wrong. For everyone else it sure doesn't work that way. -- Regards, Joerg http://www.analogconsultants.com/ "gmail" domain blocked because of excessive spam. Use another domain or send PM.Article: 131331
Nico Coesel wrote: > Dave <dhschetz@gmail.com> wrote: > >> Does anybody out there have a good methodology for determining your >> optimal FPGA pinouts, for making PCB layouts nice, pretty, and clean? >> The brute force method is fairly maddening. I'd be curious to hear if >> anybody has any 'tricks of the trade' here. > > I start thinking about how the PCB should be routed the minute I start > to draw a schematic. I always draw components with their actual > pin-outs. This helps to group pins together and it helps to > troubleshoot the circuit when the prototype is on your bench (no need > to lookup the pinouts because they are in your diagram). > For quad opamps like the LM324 as well? That can make a schematic harder to read and will also cause a nightmare if the layouter wants to swap amp A with amp C and stuff like that. [...] -- Regards, Joerg http://www.analogconsultants.com/ "gmail" domain blocked because of excessive spam. Use another domain or send PM.Article: 131332
Hello, I am writing my report on a university project. The project work involved an FPGA implementation of a neural network. I have created two versions of the design; a serial and a parallel version. Both synthesise and work in hardware. I am comparing the two in terms of performance. I would also like to compare them in terms of how much FPGA resources they consume. Could somebody please give me some advice on what elements of synthesis would be good for comparison? I'm currently comparing Max Clock. Frequency, Number of Slices, Number of Bonded IOBs. ThanksArticle: 131333
Moikel wrote: > I'm currently comparing Max Clock. Frequency, Number of Slices, Number > of Bonded IOBs. I like Fmax, LUTs, and Flops. -- Mike TreselerArticle: 131334
In article <PLsOj.7522$GE1.332@nlpi061.nbdc.sbc.com>, notthisjoergsch@removethispacbell.net says... > Joel Koltner wrote: > > "Joerg" <notthisjoergsch@removethispacbell.net> wrote in message > > news:tq7Oj.1556$FF6.588@newssvr29.news.prodigy.net... > >> All I know from here (CA) is that their benefits are mind-boggling... > > > > Well, it's entirely reasonable to have retirement benefits for public > > employees be comparable to what private companies offer... I just hope that > > public employee salaries will then become comparable as well (which implies a > > pay raise), since otherwise I don't see how the gov't. expects they'll get > > comparable quality out of their workers. > > > > Private companies generally offer zilch in retirement benefits. Those > days are long gone. I don't know about "gone". The age of the "defined benefit" is pretty much gone in private industry but several still have "defined contribution" plans. Now, 401Ks make up for a lot of what's been lost and are portable. > > One problem with the government seems to be that they don't expect their > > employees to be agile over time. See this article: > > http://www.gcn.com/print/24_30/37174-1.html -- Someone the government ends up > > with a bunch of 70 year old programmers and therefore has to hire IBM to build > > them the modernized e-filing systems? Surely there must be some new hires in > > the past, say, 40 years who could have been working on this and hence, on > > average, would only be middle-aged today!? > > > > A 70 year old programmer can be better than a 40 year old. At least > that's my impression when I see all the "modern" bloatware ;-) Maybe. There are better things to do at 70, though. ;-) > > >> Oh, and then lots of jobs have the retirement benefit tied to the last work > >> year. > > > > I expect that was implemented to help people who were *forced* to move? > > > > It seems like it needs reworking to differentiate between cases where the > > government wants to move you vs. you just voluntarily wanting to do so. > > > > Or you just have to have the right connections to make that happen ... > > Anyhow, why should retirement checks be based on the last year of > service? IMHO that's wrong. For everyone else it sure doesn't work that way. The last years' is indicative of the final salary. Most "defined benefit" plans do take the last year, or last couple of years into account. What most private pensions *don't* do, that public plans do is include overtime in the formula. It's not hard to double one's income for a couple of years. There is no way the tax payer should pay that forever. -- KeithArticle: 131335
krw wrote: > In article <PLsOj.7522$GE1.332@nlpi061.nbdc.sbc.com>, > notthisjoergsch@removethispacbell.net says... >> Joel Koltner wrote: >>> "Joerg" <notthisjoergsch@removethispacbell.net> wrote in message >>> news:tq7Oj.1556$FF6.588@newssvr29.news.prodigy.net... >>>> All I know from here (CA) is that their benefits are mind-boggling... >>> Well, it's entirely reasonable to have retirement benefits for public >>> employees be comparable to what private companies offer... I just hope that >>> public employee salaries will then become comparable as well (which implies a >>> pay raise), since otherwise I don't see how the gov't. expects they'll get >>> comparable quality out of their workers. >>> >> Private companies generally offer zilch in retirement benefits. Those >> days are long gone. > > I don't know about "gone". The age of the "defined benefit" is > pretty much gone in private industry but several still have "defined > contribution" plans. Now, 401Ks make up for a lot of what's been > lost and are portable. > Sure, but 401(k) is generally funded by the employee. Occasionally the company throws in a little extra but that is mostly a mere drop in the bucket in contrast to the lavish pension plans that cover many state workers. >>> One problem with the government seems to be that they don't expect their >>> employees to be agile over time. See this article: >>> http://www.gcn.com/print/24_30/37174-1.html -- Someone the government ends up >>> with a bunch of 70 year old programmers and therefore has to hire IBM to build >>> them the modernized e-filing systems? Surely there must be some new hires in >>> the past, say, 40 years who could have been working on this and hence, on >>> average, would only be middle-aged today!? >>> >> A 70 year old programmer can be better than a 40 year old. At least >> that's my impression when I see all the "modern" bloatware ;-) > > Maybe. There are better things to do at 70, though. ;-) Yes, definitely. OTOH completely quitting a career has brought many fine engineers into the grave within less than a year. My father who worked as a data processing engineer continued as a consultant and gradually tapered it off. He said that there was a rash of unexpected deaths of otherwise quite healthy colleagues right after retirement, and it was among the group of engineers who shut their careers down more or less overnight after the first retirement check arrived. >>>> Oh, and then lots of jobs have the retirement benefit tied to the last work >>>> year. >>> I expect that was implemented to help people who were *forced* to move? >>> >>> It seems like it needs reworking to differentiate between cases where the >>> government wants to move you vs. you just voluntarily wanting to do so. >>> >> Or you just have to have the right connections to make that happen ... >> >> Anyhow, why should retirement checks be based on the last year of >> service? IMHO that's wrong. For everyone else it sure doesn't work that way. > > The last years' is indicative of the final salary. Most "defined > benefit" plans do take the last year, or last couple of years into > account. What most private pensions *don't* do, that public plans > do is include overtime in the formula. It's not hard to double > one's income for a couple of years. There is no way the tax payer > should pay that forever. > But it's happening. And we are all paying for that. -- Regards, Joerg http://www.analogconsultants.com/ "gmail" domain blocked because of excessive spam. Use another domain or send PM.Article: 131336
Hi there - I am slowly teaching myself VHDL this weekend. I am getting an error that I do not understand: "parse error, unexpected IF". My very simple code is at the bottom of this post, and the error is being caused by the "if switches(0)=0 then" line. Can somebody tell me what I'm doing wrong? I'm sure it's terribly simple - but coming from a C background I am having trouble understanding what I'm doing wrong. Thanks! -Michael library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity hello_world is port ( clk, enc_a, end_b : in std_logic; switches : in std_logic_vector (3 downto 0); led : out std_logic_vector (7 downto 0) ); end hello_world; architecture rtl of hello_world is signal cnt : std_logic_vector (30 downto 0); signal enccnt : std_logic_vector (7 downto 0); begin process(clk) begin if rising_edge(clk) then cnt <= cnt + 1; end if; end process; if switches(0)=0 then led <= cnt(30 downto 23); else led <= enccnt; end if; end rtl;Article: 131337
In article <ovwOj.2084$pS4.1733@newssvr13.news.prodigy.net>, notthisjoergsch@removethispacbell.net says... > krw wrote: > > In article <PLsOj.7522$GE1.332@nlpi061.nbdc.sbc.com>, > > notthisjoergsch@removethispacbell.net says... > >> Joel Koltner wrote: > >>> "Joerg" <notthisjoergsch@removethispacbell.net> wrote in message > >>> news:tq7Oj.1556$FF6.588@newssvr29.news.prodigy.net... > >>>> All I know from here (CA) is that their benefits are mind-boggling... > >>> Well, it's entirely reasonable to have retirement benefits for public > >>> employees be comparable to what private companies offer... I just hope that > >>> public employee salaries will then become comparable as well (which implies a > >>> pay raise), since otherwise I don't see how the gov't. expects they'll get > >>> comparable quality out of their workers. > >>> > >> Private companies generally offer zilch in retirement benefits. Those > >> days are long gone. > > > > I don't know about "gone". The age of the "defined benefit" is > > pretty much gone in private industry but several still have "defined > > contribution" plans. Now, 401Ks make up for a lot of what's been > > lost and are portable. > > > > Sure, but 401(k) is generally funded by the employee. Occasionally the > company throws in a little extra but that is mostly a mere drop in the > bucket in contrast to the lavish pension plans that cover many state > workers. It's quite normal for a company to add significantly to the 401K, sometimes with strings attached, sometimes without. My PPOE had a fairly decent 401K (in addition to pension plans for everyone joining before '06, or so). They matched 1:1 up to 6% of salary (plus bonusus) and had no management fees for the normal funds. I understand it's gotten better since they've dropped the pension plans for the newbs. > >>> One problem with the government seems to be that they don't expect their > >>> employees to be agile over time. See this article: > >>> http://www.gcn.com/print/24_30/37174-1.html -- Someone the government ends up > >>> with a bunch of 70 year old programmers and therefore has to hire IBM to build > >>> them the modernized e-filing systems? Surely there must be some new hires in > >>> the past, say, 40 years who could have been working on this and hence, on > >>> average, would only be middle-aged today!? > >>> > >> A 70 year old programmer can be better than a 40 year old. At least > >> that's my impression when I see all the "modern" bloatware ;-) > > > > Maybe. There are better things to do at 70, though. ;-) > > > Yes, definitely. OTOH completely quitting a career has brought many fine > engineers into the grave within less than a year. My father who worked > as a data processing engineer continued as a consultant and gradually > tapered it off. He said that there was a rash of unexpected deaths of > otherwise quite healthy colleagues right after retirement, and it was > among the group of engineers who shut their careers down more or less > overnight after the first retirement check arrived. I got quite bored, once I wasn't allowed to make messes at home anymore. Good thing that only lasted a week or two. ;-) > > >>>> Oh, and then lots of jobs have the retirement benefit tied to the last work > >>>> year. > >>> I expect that was implemented to help people who were *forced* to move? > >>> > >>> It seems like it needs reworking to differentiate between cases where the > >>> government wants to move you vs. you just voluntarily wanting to do so. > >>> > >> Or you just have to have the right connections to make that happen ... > >> > >> Anyhow, why should retirement checks be based on the last year of > >> service? IMHO that's wrong. For everyone else it sure doesn't work that way. > > > > The last years' is indicative of the final salary. Most "defined > > benefit" plans do take the last year, or last couple of years into > > account. What most private pensions *don't* do, that public plans > > do is include overtime in the formula. It's not hard to double > > one's income for a couple of years. There is no way the tax payer > > should pay that forever. > > > > But it's happening. And we are all paying for that. Precisely. It's not going to get better. The government requires others to have fully funded retirement plans, but would have none of it for themselves. -- KeithArticle: 131338
Michael wrote: > Hi there - I am slowly teaching myself VHDL this weekend. I am getting > an error that I do not understand: "parse error, unexpected IF". My > very simple code is at the bottom of this post, and the error is being > caused by the "if switches(0)=0 then" line. Can somebody tell me what > I'm doing wrong? I'm sure it's terribly simple - but coming from a C > background I am having trouble understanding what I'm doing wrong. You can't use IF outside of processes, a bit like that you can't use the C IF outside of functions. You could write it like this: led <= cnt(30 downto 23) when switches(0)=0 else enccnt; A bit like the ?-operator in C. -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 131339
Joerg <notthisjoergsch@removethispacbell.net> wrote: >Nico Coesel wrote: >> Dave <dhschetz@gmail.com> wrote: >> >>> Does anybody out there have a good methodology for determining your >>> optimal FPGA pinouts, for making PCB layouts nice, pretty, and clean? >>> The brute force method is fairly maddening. I'd be curious to hear if >>> anybody has any 'tricks of the trade' here. >> >> I start thinking about how the PCB should be routed the minute I start >> to draw a schematic. I always draw components with their actual >> pin-outs. This helps to group pins together and it helps to >> troubleshoot the circuit when the prototype is on your bench (no need >> to lookup the pinouts because they are in your diagram). >> > >For quad opamps like the LM324 as well? No. Those (and simple logic) have very few pins. -- Programmeren in Almere? E-mail naar nico@nctdevpuntnl (punt=.)Article: 131340
On Apr 18, 2:57=A0pm, Nemesis <gnemesis2...@gmail.com> wrote: > On Apr 17, 9:58 am, Martin Thompson <martin.j.thomp...@trw.com> wrote: > > > > I just tested the new bitfile with the 200ms DCM reset ... it seems to= > > > work fine. > > > We'll see :-) > > > Excellent - and I see I'll have to go and peruse the datasheet > > further! =A0200ms is alot longer than I recall! > > It is reported on the Virtex 4 User Guide ... but before reading it I > was using the ISE online help manuals ... and I didn't find any > mention to 200ms ... if I remember correctly. *** Always refer to most-recent datasheet! (updates from xilinx.com) *** People usually are amazed at the datasheet changes from Xilinx for its FX devices :-)Article: 131341
Michael a écrit : > Hi there - I am slowly teaching myself VHDL this weekend. I am getting > an error that I do not understand: "parse error, unexpected IF". My > very simple code is at the bottom of this post, and the error is being > caused by the "if switches(0)=0 then" line. Can somebody tell me what > I'm doing wrong? I'm sure it's terribly simple - but coming from a C > background I am having trouble understanding what I'm doing wrong. Hello There are a few points that need clarifying, besides you "unexpected if" problem which has already been dealt with. > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > use IEEE.STD_LOGIC_ARITH.ALL; > use IEEE.STD_LOGIC_UNSIGNED.ALL; NEVER, in any case, use these non-standard libraries called std_logic_arith, std_logic_signed and std_logic_unsigned. Use numeric_std instead. With this library, declare your signal cnt as unsigned instead of std_logic_vector [...] > > if switches(0)=0 then > led <= cnt(30 downto 23); > else > led <= enccnt; > end if; Your if statement should be inside a process, as has already been said. Second point : signal switches is an array of std_logic, not an array of integers. std_logic litteral constants must be written betwen single quotes: if switches(0) = '0' then led <= std_logic_vector(led(30 downto 23)); Since cnt is now unsigned, you need to cast it to std_logic_vector before assigning to led. NicolasArticle: 131342
On Apr 19, 10:41=A0pm, Frank Buss <f...@frank-buss.de> wrote: > Michael wrote: > > Hi there - I am slowly teaching myself VHDL this weekend. I am getting > > an error that I do not understand: "parse error, unexpected IF". My > > very simple code is at the bottom of this post, and the error is being > > caused by the "if switches(0)=3D0 then" line. Can somebody tell me what > > I'm doing wrong? I'm sure it's terribly simple - but coming from a C > > background I am having trouble understanding what I'm doing wrong. > > You can't use IF outside of processes, a bit like that you can't use the C= > IF outside of functions. You could write it like this: > > led <=3D cnt(30 downto 23) when switches(0)=3D0 else enccnt; > > A bit like the ?-operator in C. Hi Frank - thanks for clearing that up. I had not realized that limitation of IF. Why can ifs only be used inside processes? That strikes me as an odd limitation, though I'm sure there's a good reason behind it. I tried your suggestion for the change, but I got this error: "can not have such operands in this context.". That strikes me as an odd error - as led, cnt, and enccnt are of the same type. Any idea what is wrong? Thanks again! -MichaelArticle: 131343
On Apr 20, 9:05 am, Michael <nleah...@gmail.com> wrote: > On Apr 19, 10:41 pm, Frank Buss <f...@frank-buss.de> wrote: > > > Michael wrote: > > > Hi there - I am slowly teaching myself VHDL this weekend. I am getting > > > an error that I do not understand: "parse error, unexpected IF". My > > > very simple code is at the bottom of this post, and the error is being > > > caused by the "if switches(0)=0 then" line. Can somebody tell me what > > > I'm doing wrong? I'm sure it's terribly simple - but coming from a C > > > background I am having trouble understanding what I'm doing wrong. > > > You can't use IF outside of processes, a bit like that you can't use the C > > IF outside of functions. You could write it like this: > > > led <= cnt(30 downto 23) when switches(0)=0 else enccnt; > > > A bit like the ?-operator in C. > > Hi Frank - thanks for clearing that up. I had not realized that > limitation of IF. Why can ifs only be used inside processes? That > strikes me as an odd limitation, though I'm sure there's a good reason > behind it. > > I tried your suggestion for the change, but I got this error: "can not > have such operands in this context.". That strikes me as an odd error > - as led, cnt, and enccnt are of the same type. > > Any idea what is wrong? Thanks again! > > -Michael Hello again - I took Nicholas's suggestion to change the comparison to: switches(0)='0' (I added single quotes around the 0) - and that fixed the problem. The code synthesized properly and is now running as expected on my Spartan-3E dev board! Thanks! -MichaelArticle: 131344
Michael wrote: > Hi Frank - thanks for clearing that up. I had not realized that > limitation of IF. Why can ifs only be used inside processes? That > strikes me as an odd limitation, though I'm sure there's a good reason > behind it. I don't know if there is a reason, sometimes VHDL looks a bit random to me, e.g. I always forget where I need a semicolon and where it is forbidden. Maybe the language designers have designed the IF/WHEN difference, because IF doesn't need an ELSE, but then you need a latch and WHEN is pure combinatorial logic. > I tried your suggestion for the change, but I got this error: "can not > have such operands in this context.". That strikes me as an odd error > - as led, cnt, and enccnt are of the same type. See the other answer: Unlike in C (char/char*) you have to use '0' instead of just 0 for elements of std_logic_vector (and e.g. "010" for a "string"). -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 131345
On Apr 20, 9:05=A0am, Michael <nleah...@gmail.com> wrote: > On Apr 19, 10:41=A0pm, Frank Buss <f...@frank-buss.de> wrote: > > > Michael wrote: > > > Hi there - I am slowly teaching myself VHDL this weekend. I am getting= > > > an error that I do not understand: "parse error, unexpected IF". My > > > very simple code is at the bottom of this post, and the error is being= > > > caused by the "if switches(0)=3D0 then" line. Can somebody tell me wha= t > > > I'm doing wrong? I'm sure it's terribly simple - but coming from a C > > > background I am having trouble understanding what I'm doing wrong. > > > You can't use IF outside of processes, a bit like that you can't use the= C > > IF outside of functions. You could write it like this: > > > led <=3D cnt(30 downto 23) when switches(0)=3D0 else enccnt; > > > A bit like the ?-operator in C. > > Hi Frank - thanks for clearing that up. I had not realized that > limitation of IF. Why can ifs only be used inside processes? That > strikes me as an odd limitation, though I'm sure there's a good reason > behind it. > > I tried your suggestion for the change, but I got this error: "can not > have such operands in this context.". That strikes me as an odd error > - as led, cnt, and enccnt are of the same type. > > Any idea what is wrong? Thanks again! > > -Michael Hello again - I took Nicholas's suggestion and put single quotes around the '0' in the switches(0)=3D'0' comparison - and now it works exactly as expected! Thanks! -MichaelArticle: 131346
On Apr 20, 6:37=A0am, Nicolas Matringe <nicolas.matri...@fre.fre> wrote: > Michael a =E9crit : > > > Hi there - I am slowly teaching myself VHDL this weekend. I am getting > > an error that I do not understand: "parse error, unexpected IF". My > > very simple code is at the bottom of this post, and the error is being > > caused by the "if switches(0)=3D0 then" line. Can somebody tell me what > > I'm doing wrong? I'm sure it's terribly simple - but coming from a C > > background I am having trouble understanding what I'm doing wrong. > > Hello > There are a few points that need clarifying, besides you "unexpected if" > problem which has already been dealt with. > > > library IEEE; > > use IEEE.STD_LOGIC_1164.ALL; > > use IEEE.STD_LOGIC_ARITH.ALL; > > use IEEE.STD_LOGIC_UNSIGNED.ALL; > > NEVER, in any case, use these non-standard libraries called > std_logic_arith, std_logic_signed and std_logic_unsigned. Use > numeric_std instead. > With this library, declare your signal cnt as unsigned instead of > std_logic_vector Hi Nicholas! I must admit I did not make a conscious choice to use those libraries - they were put in automatically by Xilinx ISE. So you're saying for my purposes, that section should just look like this?: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.all; > [...] > > > > > =A0 =A0if switches(0)=3D0 then > > =A0 =A0 =A0 =A0 =A0 =A0led <=3D cnt(30 downto 23); > > =A0 =A0else > > =A0 =A0 =A0 =A0 =A0 =A0led <=3D enccnt; > > =A0 =A0end if; > > Your if statement should be inside a process, as has already been said. > Second point : signal switches is an array of std_logic, not an array of > integers. std_logic litteral constants must be written betwen single quote= s: > if switches(0) =3D '0' then > =A0 =A0led <=3D std_logic_vector(led(30 downto 23)); Ah - perfect! Adding those quotes just fixed one of my problems! > Since cnt is now unsigned, you need to cast it to std_logic_vector > before assigning to led. > > Nicolas So is a cast in VHDL just like a cast in C? I must admit this is the first I've heard of VHDL having that ability. Thanks! -MichaelArticle: 131347
Hi Michael, This might help you... Cheers, Syms. http://www.synthworks.com/papers/vhdl_math_tricks_mapld_2003.pdfArticle: 131348
As my current project is about the security that Xilinx embeds in the Virtex 5 , i have some points that i couldn't understand and really i need help to advance in my project : - first how we can prove that really the AES 256 (cbc mode) is used to crypt the Bitstream +> is it possible to know this by taking advantages from the .rbt file ? starting from the .rbt file for encrypted design how can i extract the IV (init vector) , and from wich part exactly start the enryption ? after the header information ? -second , where exactly the key is stored ? articles said " the key is stored in dedicated memory" ... the key is stored some where in the surface shown by FPGA Editor or elsewhere ?? -third , what is the effeciency of the side channel attack to break AES 256 ? regards joeArticle: 131349
Hi, I am wondering if anyone of you have experienced this before. Here goes the reset problem I am facing now. asynchronous reset in FPGAs are usually a big NO-NO. from the articles I am reading, the async reset, normally results in more logic being used to stitch up LUTs together. However, the design I am currently working on requires only one of the blocks to run at 1/4 that of the original clock speed. I am using a DCM to clock divide the master clock, and the output goes into this block. The problem happens when - the reset signal which resets the DCM, is the same reset which goes into this same block. - This will result in a problem, as the clock-divide-by-4 as I call it, will not emit a clock pulse in reset state, as the DCM has not locked yet. the synchronous reset will thus not work for this block. 1) Any ideas of how to circumvent this problem? I would like to use synchronous resets, but also use the divide by 4 clock for the block. 2) Are my concepts of synchronous resets correct? that synchronous resets on FPGA are better than asynchronous resets? thanks Chris
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