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RealInfo wrote: > Hi > > I want to get into FPGA design after long time I was out of it. > > I did some work with ALTERRA long ago . > > I mainly did VHDL models for asic . > > I want to buy some FPGA board and to do some projects on it with VHDL > to get into that field again . > > My question is which board and which FPGA vendor is reccomanded > according to your > experience. > > Thanks in advance > ec. Dear ec, If you are unable to use Google to help yourself, perhaps you should stay out of FPGA design. Now, be a good chap, and do some research before you post. Condescendingly, Syms. http://catb.org/~esr/faqs/smart-questions.html#before to find http://www.fpga-faq.com/FPGA_Boards.shtmlArticle: 131501
Come on Symon. He said a "long time". When the first FPGAs appeared, there where not internet or Google! Luiz CarlosArticle: 131502
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Dear Symon the same advice to you if you can not understand simple =
english ...=20
"My question is which board and which FPGA vendor is reccomanded =
according to=20
your experience "
Does GOOGLE have any experince in FPGA so it/he/she whatever can give =
some advise ?=20
Thanks any way ...
"Symon" <symon_brewer@hotmail.com> =EB=FA=E1 =
=E1=E4=E5=E3=F2=E4:fun8t6$fv7$1@aioe.org...
> RealInfo wrote:
>> Hi
>>
>> I want to get into FPGA design after long time I was out of it.
>>
>> I did some work with ALTERRA long ago .
>>
>> I mainly did VHDL models for asic .
>>
>> I want to buy some FPGA board and to do some projects on it with VHDL
>> to get into that field again .
>>
>> My question is which board and which FPGA vendor is reccomanded
>> according to your
>> experience.
>>
>> Thanks in advance
>> ec.
>=20
> Dear ec,
> If you are unable to use Google to help yourself, perhaps you should =
stay=20
> out of FPGA design. Now, be a good chap, and do some research before =
you=20
> post.
> Condescendingly, Syms.
> http://catb.org/~esr/faqs/smart-questions.html#before
> to find
> http://www.fpga-faq.com/FPGA_Boards.shtml=20
>=20
>
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<DIV><FONT face=3DArial size=3D2>Dear Symon the same advice to you if =
you can not=20
understand simple english ... </FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2>"My question is which board and which =
FPGA vendor=20
is reccomanded <STRONG>according to <BR> your=20
experience "<BR></STRONG></FONT></DIV>
<DIV><FONT face=3DArial size=3D2><STRONG>Does GOOGLE have any experince =
in FPGA=20
so it/he/she whatever can give some <U><FONT=20
size=3D4>advise</FONT></U> ? </STRONG></FONT></DIV>
<DIV><FONT face=3DArial size=3D2><STRONG></STRONG></FONT> </DIV>
<DIV><STRONG><FONT face=3DArial size=3D2>Thanks any way =
...</FONT></STRONG></DIV>
<DIV><STRONG><FONT face=3DArial size=3D2></FONT></STRONG> </DIV>
<DIV><FONT face=3DArial size=3D2> </DIV></FONT>
<DIV><FONT face=3DArial size=3D2><STRONG></STRONG></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2> </DIV></FONT>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2>"Symon" <</FONT><A=20
href=3D"mailto:symon_brewer@hotmail.com"><FONT face=3DArial=20
size=3D2>symon_brewer@hotmail.com</FONT></A><FONT face=3DArial =
size=3D2>> =EB=FA=E1=20
=E1=E4=E5=E3=F2=E4:fun8t6$fv7$1@aioe.org...</FONT></DIV><FONT =
face=3DArial size=3D2>>=20
RealInfo wrote:<BR>>> Hi<BR>>><BR>>> I want to get =
into FPGA=20
design after long time I was out of it.<BR>>><BR>>> I did =
some work=20
with ALTERRA long ago .<BR>>><BR>>> I mainly did VHDL models =
for=20
asic .<BR>>><BR>>> I want to buy some FPGA board and to do =
some=20
projects on it with VHDL<BR>>> to get into that field again=20
.<BR>>><BR>>> My question is which board and which FPGA =
vendor is=20
reccomanded<BR>>> according to your<BR>>>=20
experience.<BR>>><BR>>> Thanks in advance<BR>>> =
ec.<BR>>=20
<BR>> Dear ec,<BR>> If you are unable to use Google to help =
yourself,=20
perhaps you should stay <BR>> out of FPGA design. Now, be a good =
chap, and do=20
some research before you <BR>> post.<BR>> Condescendingly, =
Syms.<BR>>=20
</FONT><A =
href=3D"http://catb.org/~esr/faqs/smart-questions.html#before"><FONT=20
face=3DArial=20
size=3D2>http://catb.org/~esr/faqs/smart-questions.html#before</FONT></A>=
<BR><FONT=20
face=3DArial size=3D2>> to find<BR>> </FONT><A=20
href=3D"http://www.fpga-faq.com/FPGA_Boards.shtml"><FONT face=3DArial=20
size=3D2>http://www.fpga-faq.com/FPGA_Boards.shtml</FONT></A><FONT =
face=3DArial=20
size=3D2> <BR>> <BR>></FONT></BODY></HTML>
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Article: 131503On Apr 23, 5:33=A0am, ee_ether <xjjzdv...@sneakemail.com> wrote: > Hi, > > Crux of the matter: =A0Do you need to define values for outputs of your > state machine in EVERY state, or do you only need to define values for > outputs in states where you want the output to update/change? > It doesn't matter. The same synthesized output can result from more than one source code representation. > Skip to the chase: =A0At end of message is a Verilog state machine that > does NOT define outputs in all states. =A0Is this acceptable Verilog or > unacceptable (targeting FPGA)? If it implements the required function than it is acceptable. > If not, how would you re-write it? =A0 If it's not broken, don't fix it. > If > yes, what are the implications? =A0When you write a SM in Verilog can > you "abbreviate" your output logic and let the synthesizer infer > storage registers for flags assuming you don't define output condition > for all states? > If you get paid by the line of code then you might want to set those outputs in every state. > For the code below, the synthesizer (Altera Quartus II v7.1) produces > DFF with MUXes in front ; no latches synthesized. =A0The register is fed > back its value when NOT in the states where value is updated. =A0This is > gleaned from using RTL Viewer in Quartus II. =A0I am curious what ISE > 10x would do with this Verilog too... > Why the curiousity? Run it through and satisfy your curiousity, that's the best teacher. > Colleague: =A0Verilog/RTL is supposed to provide a reasonable > abstraction, so if you have a state machine where you are updating a > flag (i.e. set the bit/flag in one state, clear it in some other), you > only need to define the output in those states where the bit will be > set or cleared. =A0The synthesizer will then produce a register and only > update the value(register) in the correct state. =A0Coding values of ALL > outputs in ALL states would be too tedious and negates advantage of > RTL. > Whether one *should* code outputs in every state or not can depend on how many different paths there can be through the state machine. One that is fairly simple (like a simple loop) it is likely just as clear to the reader to only explicitly set the outputs when they need to change. Another more complicated one where there is all sorts of branching dependent on various conditions might benefit from coding the output values in more (or all) of the states. The other thing that influences the decision (possibly even more) is whether or not you, from a design perspective, inherently 'know' what the output should be while you're in a particular state. Many state machines might not care what the value of output 'xyz' should be while they're in state 'state_abc'. Those types of state machines will be more clearly written in the style of specifying output changes rather than explicitly setting them. The example that the colleague mentioned sounds to me like a case where coding only the changes (as he suggests) would be best because it more clearly captures the intent. > My perspective is : You must define output in every state otherwise > the synthesizer will produce a latch, or some other kind of unwanted > feedback vs. decoding the output based off state registers (and > possibly any other asynchronous inputs). =A0 Not true at all...state machines are synchronous things clocked by a clock, there will be no latches ever produced. You're getting confused with the 'two process' style where this can happen (which is why the 'two process' style is considered inferior by most skilled designers). > When I wrote VHDL I would > always define output of SM (mealy or moore) and it would result in > unpleasant to read RTL but synthesized to what I want. =A0FWIW, I prefer > to combine output statements and next-state logic in one process since > I can follow the logic more easily; if I want a set/clear type flag > then I define SET_FLAG and CLEAR_FLAG signals and they are driven in > every state; a clocked process is used to check SET and CLEAR to > synchronously toggle output (flag). > And there is the main criteria you should use....how easy is it to read and understand the resulting code because that is what one will need to maintain down the road. Clarity of intent in the source code is second only to correct function in my book. Kevin JenningsArticle: 131504
http://toolbox.xilinx.com/docsan/xilinx92/books/docs/cgd/cgd.pdfArticle: 131505
Alan Nishioka wrote: > Xilinx is canceling the Virtex-E XCV1000E-FG860. > > We are currently shipping a product that uses 13 of these chips on 4 > different boards. > > Does anyone have any ideas on how to deal with this? > > One possibility is to rev the boards to use the XCV1000E-FG900, making > minimal changes to the boards around the fpga. > > Complete re-design of the boards for this old system is out of the > question. Stockpiling a bunch of parts won't work because we don't > know what future quantities will be and the parts are very expensive. > > Alan Nishioka > alan@nishioka.com Hi Alan, Maybe an interposer would work? Mount the FG900 on that, mount the interposer on your board? Somethign like this... http://advanced.com/pdf/AIC_BGA_Interposer_DataSheet_revJun07.pdf HTH., Syms.Article: 131506
Real, I suggest visiting: http://www.digilentinc.com/ The 3E starter kit is used by tens of thousands of students every day, so there is a LOT of stuff out their on the web. It is also easy to use. If you can break away from your 'Altera' past, AustinArticle: 131507
On Wed, 23 Apr 2008 02:33:32 -0700 (PDT), ee_ether <xjjzdv402@sneakemail.com> wrote: >Hi, > >A colleague and I are having a friendly debate on coding state >machines in Verilog, targeting synthesis for FPGAs. Comments are very >appreciated. I am NOT trying to start a holy war here regarding >syntax style (one process vs. two process, etc). > >Crux of the matter: Do you need to define values for outputs of your >state machine in EVERY state, or do you only need to define values for >outputs in states where you want the output to update/change? In either one process or two process designs, you only need to write to the next state when you need to change it. In one process, the registers by definition remember their state so there is no chance of getting a latch. In two states, you assign the next state to the current state at the top of the process so if they don't get written again later, they keep their current state so no latches either.Article: 131508
On Wed, 23 Apr 2008 15:25:33 GMT, Muzaffer Kal <kal@dspia.com> wrote: >On Wed, 23 Apr 2008 02:33:32 -0700 (PDT), ee_ether ><xjjzdv402@sneakemail.com> wrote: > >>Hi, >> >>A colleague and I are having a friendly debate on coding state >>machines in Verilog, targeting synthesis for FPGAs. Comments are very >>appreciated. I am NOT trying to start a holy war here regarding >>syntax style (one process vs. two process, etc). >> >>Crux of the matter: Do you need to define values for outputs of your >>state machine in EVERY state, or do you only need to define values for >>outputs in states where you want the output to update/change? > >In either one process or two process designs, you only need to write >to the next state when you need to change it. In one process, the >registers by definition remember their state so there is no chance of >getting a latch. In two states, you assign the next state to the this should say "in two process implementation..." of course >current state at the top of the process so if they don't get written >again later, they keep their current state so no latches either. here are some example for my points: always@(posedge clk) if (enable) count <= count+1; in this case there is no need for else count <= count; because if not enable counter registers remember their state so in a state machine, there is no reason to write to states/outputs which don't need changing. In two process design, you say always @(*) begin next_state = state; case (state) foo: next_state = bar; bar: output_x = 6; // no state change ... end in this case the first line always assigns next_state so if later not reassigned it remembers that value so there is no latch for next_state, strictly combinational of off state.Article: 131509
Hi I am just wondering if somebody has some good sources for a superscalar processor implementation in VHDL? I have found a lot simple Implementations but struggle to find a superscalar one. Especially the logic design of the dispatcher unit would be interesting for me where the independet instructions are identified and then issued Thanks for some helpful tips! PeterArticle: 131510
On Apr 23, 11:34 am, Muzaffer Kal <k...@dspia.com> wrote: > On Wed, 23 Apr 2008 15:25:33 GMT, Muzaffer Kal <k...@dspia.com> wrote: > >On Wed, 23 Apr 2008 02:33:32 -0700 (PDT), ee_ether > ><xjjzdv...@sneakemail.com> wrote: > > >>Hi, > > >>A colleague and I are having a friendly debate on coding state > >>machines in Verilog, targeting synthesis for FPGAs. Comments are very > >>appreciated. I am NOT trying to start a holy war here regarding > >>syntax style (one process vs. two process, etc). > > >>Crux of the matter: Do you need to define values for outputs of your > >>state machine in EVERY state, or do you only need to define values for > >>outputs in states where you want the output to update/change? > > >In either one process or two process designs, you only need to write > >to the next state when you need to change it. In one process, the > >registers by definition remember their state so there is no chance of > >getting a latch. In two states, you assign the next state to the > > this should say "in two process implementation..." of course > > >current state at the top of the process so if they don't get written > >again later, they keep their current state so no latches either. > > here are some example for my points: > > always@(posedge clk) > if (enable) > count <= count+1; > > in this case there is no need for > else > count <= count; > > because if not enable counter registers remember their state so in a > state machine, there is no reason to write to states/outputs which > don't need changing. > > In two process design, you say > always @(*) > begin > next_state = state; > case (state) > foo: next_state = bar; > bar: output_x = 6; // no state change > ... > end > > in this case the first line always assigns next_state so if later not > reassigned it remembers that value so there is no latch for > next_state, strictly combinational of off state. I think what Kevin was getting at was that in the two-process style, every output signal in the asynchronous process needs to be assigned for every case. The fact that there is a default assignment doesn't change this - every output is defined for every possible case. Even if there is a default assignment, you still need to specify the output when the output differs from the default, which is different from saying that the output needs to be specified only when it changes. You could omit the output assignment for a case, and it might still change from a non-default value to the default value. The default assignment does not imply memory, it's just a shorthand notation to keep the code more readable. DaveArticle: 131511
austin wrote: > What is your present volume? It is only about 10 Xilinx parts per month. But the parts started out at $1000 each, so it adds up. Alan NishiokaArticle: 131512
Alan, I think the interposer suggestion is really the best one. With the small volume, re-design of the pcb is just not going to be worth the money spent (you will never recover it), where the interposer is a fixed cost, and a known set of issues, and although "clunky" does work... The reality is that Xilinx does everything it can to NOT obsolete anything that is making money (or even breaking even), but we do have to look at what is NOT selling, and make some hard decisions from time to time. I do apologize: there is no way I can tell you what will be a top seller, and what will not be a top seller (part, package, or otherwise)! I can say that I would always look carefully at the package/part/family roadmap, and choose a part that has both up, and down, resource/pins, in the chart. Now that all V5 family members have identical pinouts (can move from LX to LXT, to SXT, to FXT, in any package without relayout*), I think things should get easier (at least that is what our customers are telling us). Austin *If you plan for it. For example, if you go from LXT to FXT, you do need to change one supply for the gigabit transceivers from 1.2 to 1.0 volts, but the pins are still the same pins. Alan Nishioka wrote: > austin wrote: >> What is your present volume? > > It is only about 10 Xilinx parts per month. But the parts started out > at $1000 each, so it adds up. > > Alan NishiokaArticle: 131513
Hi,
> Crux of the matter: Do you need to define values for outputs of your
> state machine in EVERY state, or do you only need to define values
> for outputs in states where you want the output to update/change?
It depends on the type of output. If the output is a combinational function
of the current state, or a combinational function of the current state and
the inputs, then you must describe the output values for all possible
conditions. This is how you model combinational logic; it doesn't matter if
it is part of an FSM or not.
On the other hand, if you have outputs which are a registered function of
the current state, or a registered function of the current state and the
inputs, then you do not need to describe the output values for all possible
conditions. Since you will be modeling these assignments to something that
maintains state in a clocked process, using a reg datatype, the absence of
an assignment for a given condition implies "retain the previous value".
Here's a short presentation on a "textbook" FSM:
http://www.engr.sjsu.edu/crabill/vlogfsm.pdf
To paraphrase what someone else wrote, if it solves the problem -- it's
correct. However, I think it's a good practice to fully understand what you
are creating when you write the code solve a given problem.
If you look at the code you provided in the context of a "textbook" FSM, I
would suggest that your FSM state variable is actually more than just
"state". It's
{ackb,cpu_lw_read,cpu_hw_read,cpu_lw_write,cpu_hw_write,state} and by way of
what is a custom state assignment implemented in the next state logic, you
are able to use certain bits of the state directly as outputs (Moore type
outputs) with no combinational decoding logic required to generate those
outputs.
Eric
Article: 131514On Apr 22, 12:11=A0pm, Alan Nishioka <a...@nishioka.com> wrote: > Xilinx is canceling the Virtex-E XCV1000E-FG860. > > We are currently shipping a product that uses 13 of these chips on 4 > different boards. > > Does anyone have any ideas on how to deal with this? > > One possibility is to rev the boards to use the XCV1000E-FG900, making > minimal changes to the boards around the fpga. > > Complete re-design of the boards for this old system is out of the > question. =A0Stockpiling a bunch of parts won't work because we don't know= > what future quantities will be and the parts are very expensive. > > Alan Nishioka > a...@nishioka.com Alan, I checked a few options: It is the package that is is being obsoleted, so there is no pin-out compatible way out =2E Simplest solution: Use the "last-time buy" option, order before June 008 for delivery by June 2009, which might give you enough parts to see you through 2010 or even longer, your choice. More work, but much (much!) lower component price: Redesign for Spartan XC3S1500, or take the opportunity to combine into a few larger Spartan3 devices. Remember, the '1000E was introduced 8 years ago... Regards Peter Alfke, XilinxArticle: 131515
austin wrote: > Real, > > I suggest visiting: > > http://www.digilentinc.com/ > > The 3E starter kit is used by tens of thousands of students every day, > so there is a LOT of stuff out their on the web. > > It is also easy to use. > > If you can break away from your 'Altera' past, > And if not, the Terasic kits are quite good and very well priced: http://www.terasic.com.tw/ -hpaArticle: 131516
Heey Austin and Mikhail, Thanks for the replies, it's still a bit difficult for me to make sens of it all because i have to learn more about these "buffers" (IBUFG and BUFG) but some more research on the internet will probably do the trick. It's clear now that these DCM's are internal and no physical pins are involved. A little fight with ISE to get the DCM IP-block work will be needed :) Offcourse if anyone has made a little program with a DCM involved, any code of how it's implemented is welcome. Once again: thanks! Mr.MArticle: 131517
On 23 Apr., 18:51, Peter Alfke <pe...@xilinx.com> wrote: > On Apr 22, 12:11 pm, Alan Nishioka <a...@nishioka.com> wrote: > > > Xilinx is canceling the Virtex-E XCV1000E-FG860. > > > We are currently shipping a product that uses 13 of these chips on 4 > > different boards. > > > Does anyone have any ideas on how to deal with this? > > > One possibility is to rev the boards to use the XCV1000E-FG900, making > > minimal changes to the boards around the fpga. > > > Complete re-design of the boards for this old system is out of the > > question. Stockpiling a bunch of parts won't work because we don't know > > what future quantities will be and the parts are very expensive. > > > Alan Nishioka > > a...@nishioka.com > > Alan, I checked a few options: > > It is the package that is is being obsoleted, so there is no pin-out > compatible way out > . > Simplest solution: Use the "last-time buy" option, order before June > 008 for delivery by June 2009, which might give you enough parts to > see you through 2010 or even longer, your choice. > > More work, but much (much!) lower component price: > Redesign for Spartan XC3S1500, or take the opportunity to combine into > a few larger Spartan3 devices. > > Remember, the '1000E was introduced 8 years ago... > Regards > Peter Alfke, Xilinx Hi Peter, I have another suggestion: why does Xilinx not offer "package" matching options for discontiued packages, sure only where possible and demand is? so it would be not Alan making FG900-FG860 bga adapter (with his 100KUSD+ yearly Xilinx buying for one project) but maybe also others who would benefit? just a suggestion. AnttiArticle: 131518
Sry, Should have written "shared variables" won't infer memory. lc Mike Treseler wrote: > LC wrote: >> Indeed some deviation from the recommended. >> corrected now. >> >> Main culprit was however QII requires a "signal" >> "variables" won't infer memory ! > > Not true. > > http://home.comcast.net/~mike_treseler/block_ram.vhdArticle: 131519
hi, I have ISE 9.1 + EDK 9.1 (all updates) Now i have downloaded the xilinx sysgen 10.1 (60 day trial) as 9.1 is not available also I have matlab R2006b will threre be any problem with versions , in near future -- othrewise i will search 9.1 , Thanks n RegardsArticle: 131520
I need to send video stream over a bluetoth link , case 1 ) the video lise is some format (suggest a easy format) in CF compact flash card , I need to read this file and send it through UART, Kindly give me any link to do this case 2 ) I have vidoe starter kit and video is need to be captured and processed and then I will send it through UART which case will be easy ? another problem is , I have bluetooth Kit (ROK101007) which has protocol stack upto HCI layer - I need to transfer stream via bluetooth , so inorder to transfer data I think i need to make HCI Interface layer in VHDL and put the data in HCI data format and then transmit it via UART connection,, suggest me what to do,, I ultimater goal is to transfer video data (either live stream or file stored in CF card ) via Bluetooth Link, I have bluetooth Kit (contains layer upto HCI ) -- see it diagram at -- http://bp3.blogger.com/_AOehQh51ooE/R722ZML8iII/AAAAAAAAAVk/o92AjwOZe78/s1600-h/1.png Thanks n RegardsArticle: 131521
HI, I'm struggling with an EDK project and a HydraXC here. First of all I can't get the Hydra to work. I loaded a sample design (PPC linux) from the CD onto the SD card, inserted it and turned on the power. Shouldn't I see some output on the RS232 (set to 19200). About the power. I found in the documentation that it needs a 3,3 V supply but the leds on the board only turn on if I use 5V. the HydraXC (its a XC50) is sitting on an eval board (Evalboard S V1.0) so I assume there is a 5V to 3,3 regulator but I cant find any documentation for it. Any ideas or links here? The other thing is with my EDK Design. I'm using a power pc in it and just wanted to create s simple "hello world" for now. I generate the bit file and then copy it onto the SD card right? Is there perhaps a tutorial for how to create an EDK project for the hydra? I can't really find any documentation or tutorial for the hydra besides the HydraXC user manual (V 2006). thanks UrbanArticle: 131522
Symon wrote: > Alan Nishioka wrote: >> Xilinx is canceling the Virtex-E XCV1000E-FG860. > > Maybe an interposer would work? Mount the FG900 on that, mount the > interposer on your board? Something like this... > http://advanced.com/pdf/AIC_BGA_Interposer_DataSheet_revJun07.pdf > HTH., Syms. I fear that an interposer won't work at 75MHz. It was hard enough to get to work as it is. But it is worth some thought. I wonder how much it costs? Thank you everyone for your responses. I figured it was worth a shot if anyone had a radical idea. Alan NishiokaArticle: 131523
If you get an answer I would be interested to know as I have some un- released modules than would suit the low-tech market if the technique works. A lot projects use SDRAM because it is simple especially if the frequency drops down to 25-50 makes easy timing. Do the same with DDR and then the barrier to use of DDR for these projects is gone. John Adair Enterpoint Ltd. On Apr 21, 8:15=A0pm, adubinsky...@gmail.com wrote: > Hi, > > There's been a few discussions about this the last couple years, but > it seems nothing ended with firm conclusions. What I would like to do > is to run DDR2 at 25MHz (DDR50). I understand that to do this I have > to turn off the DLL (which can't work at below 125MHz) and that this > should work but is not supported. My question is, what happens then? > > Ie: How do the DQS signals behave during read? Do they turn off, > become random, are synchronized with the clock? Is it safe to just > read the data a quarter cycle after the clock edge, or is it more > complicated than that? I haven't designed an sdram core before, but > I'm going to have to do this for this project and have many other, > more general questions. If someone knows some good reading material, > please let me know. > > Aleksandr DubinskyArticle: 131524
On 24 Apr., 15:34, "u_stad...@yahoo.de" <u_stad...@yahoo.de> wrote: > HI, > > I'm struggling with an EDK project and a HydraXC here. First of all I > can't get the Hydra to work. I loaded a sample design (PPC linux) from > the CD onto the SD card, inserted it and turned on the power. > Shouldn't I see some output on the RS232 (set to 19200). > About the power. I found in the documentation that it needs a 3,3 V > supply but the leds on the board only turn on if I use 5V. the HydraXC > (its a XC50) is sitting on an eval board (Evalboard S V1.0) so I > assume there is a 5V to 3,3 regulator but I cant find any > documentation for it. > Any ideas or links here? > > The other thing is with my EDK Design. I'm using a power pc in it and > just wanted to create s simple "hello world" for now. I generate the > bit file and then copy it onto the SD card right? Is there perhaps a > tutorial for how to create an EDK project for the hydra? I can't > really find any documentation or tutorial for the hydra besides the > HydraXC user manual (V 2006). > > thanks > Urban you should info as needed from there: http://www.ebmhydraxc.com/ but support from there links to site maintained by ME, and I just now did take it offline. anyway EDK reference designs are delivered on the support DVD, so just take it from there. Antti Lukats
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