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For behavioral sim you could go with a brand agnostic tool like ghdl
and iverilog are both free, and I've used them sucessfully for simple
to quite large designs. I find the Xilinx and Altera tools to be too
slow and cumbersome, but I haven't compared those sim tools to ghdl or
iverilog.
Basically you write your test bench in the same language as a module
that uses your hardware module, but does not have to be synthesizable
and can use all those extra language pragmas like $monitor(),
$fprintf(), $system(), etc. It is also easy to pipe the data into/out
of the testbench for external processing and verification. Waveforms
can be viewed with gtkwave.
taken from
http://www.eda.ncsu.edu/wiki/Tutorial:ASIC_Design_Tutorials#Tutorial1:_Introduction_to_Simulation_and_Synthesis
and
http://www.ece.ncsu.edu/erl/tutorials/asic.php#bs
---------------------------
test.v---------------------------------------------------------------------------------------
module test_fixture;
reg clock100 = 0 ;
reg latch = 0;
reg dec = 0;
reg [3:0] in = 4'b0101;
wire zero;
initial //following block executed only once
begin
$monitor("%b", u1.value);
$dumpfile("count.vcd"); // waveforms in this file..
//$dumpvars; // saves all waveforms
#16 latch = 1; // wait 16 ns
#10 latch = 0; // wait 10 ns
#10 dec = 1;
#100 $finish; //finished with simulation
end
always #5 clock100 = ~clock100; // 10ns clock
// instantiate modules -- call this counter u1
counter
u1( .clock(clock100), .in(in), .latch(latch), .dec(dec),
.zero(zero));
endmodule /*test_fixture*/
------------------------------------------------------------------------
--------------------
counter.v--------------------------------------------------
/*module************************************
*
* NAME: counter
*
* DESCRIPTION:
* downcounter with zero flag and synchronous clear
*
* NOTES:
*
* REVISION HISTORY
* Date Programmer Description
* 7/10/97 P. Franzon ece520-specific version
*
*M*/
/*======Declarations===============================*/
module counter (clock, in, latch, dec, zero);
/*-----------Inputs--------------------------------*/
input clock; /* clock */
input [3:0] in; /* input initial count */
input latch; /* `latch input' */
input dec; /* decrement */
/*-----------Outputs--------------------------------*/
output zero; /* zero flag */
/*----------------Nets and Registers----------------*/
/*---(See input and output for unexplained variables)---*/
reg [3:0] value; /* current count value */
wire zero;
// Count Flip-flops with input multiplexor
always@(posedge clock)
begin // begin-end not actually need here as there is only one
statement
if (latch) value <= in;
else if (dec && !zero) value <= value - 1'b1;
end
// combinational logic for zero flag
assign zero = ~|value;
endmodule /* counter */
---------------------------------
run:
iverilog counter.v test.v
./a.out
then:
gtkwave count.vcd
This is a very quick way to debug and is very similar to
On Apr 15, 3:42 pm, "HT-Lab" <han...@ht-lab.com> wrote:
> "Michael" <nleah...@gmail.com> wrote in message
>
> news:d46de822-ec69-411f-9c02-1d98727b9f46@d26g2000prg.googlegroups.com...
> On Apr 15, 12:43 pm, "HT-Lab" <han...@ht-lab.com> wrote:
>
>
>
> > "Kevin Neilson" <kevin_neil...@removethiscomcast.net> wrote in message
>
> >news:fu2ku0$aep3@cnn.xsj.xilinx.com...
>
> > > Michael wrote:
> > >> Howdy - I'm just getting started with FPGAs. In college I remember we
> > >> used ModelSim with ISE for FPGA simulation. We were able to get a
> > >> license through our school for free. Like a fool I no longer have that
> > >> license, so what free options are out there? I saw that there is
> > >> something called ModelSim Xilinx Edition III Starter (http://
> > >>www.xilinx.com/ise/mxe3/download.htm). I can't tell if that is just a
> > >> limited feature package, or a time limited package. Is that what I
> > >> want? Or is there something else I should be looking at?
>
> > >> Thanks!
>
> > >> -Michael
>
> > > The ModelSim starter is limited. I think the main limitation is that it
> > > is programmed to get radically slower as the number of lines of HDL
> > > increases. -Kevin
>
> > Starter edition slows down to 1% of PE (basically grinds to a halt) after
> > 10000 lines (executable lines), below 10000 lines it operates at 30% of
> > PE.
>
> > MXE3 edition operates at 40% of PE and slows down to 1% after 50000 lines.
>
> > There is no swift, mixed language or SystemC support in either version.
>
> > Hanswww.ht-lab.com
> >Hi Hans - thanks for the information. I'm not terribly worried about
> >speed at the moment - I'm just trying to learn the basics for now. Do
> >you know how the student edition (http://www.model.com/resources/
> >student_edition/student_default.asp) compares to these?
>
> I believe it is the same speed as PE but I am not 100% sure.
>
> >It can't handle mixed HDL designs which seems a bit of a handicap -
>
> I agree, some companies (I don't want to mention any names
> *cough*Micron*cough*) decided to only provide models in one language forcing
> users to spend extra money on a dual language license, perhaps they are
> sponsored by the EDA industry? :-)
>
> Hanswww.ht-lab.com
Article: 131226Roger wrote: > It sounds like there won't be a 64 bit Webpack - which is a shame as the > devices covered by it are sufficient for my work and I've got a PC with > Vista 64 bit on it! Won't the 32-bit WebPACK run on that? On Linux, 32-bit software generally runs fine on 64-bit kernels.Article: 131227
Kevin Neilson wrote: > Verilog is better, ^^^^^^^^^^^^^^^^^ That's far too broad a generalization. Verilog might have some advantages, but it's not clearly *better*. > but VHDL is used more in FPGAs. I'm not sure whether that's actually true overall, though it seems to be true in some geographic areas.Article: 131228
lm317t wrote: > The syntax for Verilog will be a bit more familiar to you if you > program in C/C++. Which is a drawback, not a benefit, since the actual langauge semantics are almost nothing like C. The superficial similarity of the syntax seems to cause a lot of confusion for new Verilog designers.Article: 131229
On Apr 15, 9:01 pm, Eric Smith <e...@brouhaha.com> wrote: > lm317t wrote: > > The syntax for Verilog will be a bit more familiar to you if you > > program in C/C++. > > Which is a drawback, not a benefit, since the actual langauge semantics > are almost nothing like C. The superficial similarity of the syntax > seems to cause a lot of confusion for new Verilog designers. I'm just stating my anecdotal experience, but for me the syntax similarity helped me by not forcing me to learn new syntax. How does this cause confusion? I think the biggest source of confusion for new HDL designers in general is thinking in parallel hardware, not sequential instructions like with a programming language. This is true regardless of HDL. I can't say I've heard of the C syntax causing confusion with C vs. VHDL. Anyone else here have any relevant experience or evidence for this?Article: 131230
On 15 Apr., 22:18, Mike Treseler <mike_trese...@comcast.net> wrote: > main : process(reset, clock) is > -- declarations > begin -- process template > if reset = '1' then > init_regs; > elsif rising_edge(clock) then > update_regs; > end if; > update_ports; > end process main; > end architecture synth; This is a good style beside the fact, that a tool i recently use (I think synopsys dc, not 100% shure) didn't accept the update_ports part of such an process. Thats why I update ports usualy outside the process. bye ThomasArticle: 131231
Hi, After following the the section titled "Reconfiguring the C0 Counter" gives a step by step description of how to reconfigure the PLL to change the C0 clock output. I get the divided output clock successfully. However,when I reconfig the PLL with pre-scale counter n and multiply counter m, the output clock is not equal to the Fin*m/n.(note:Fin is the input clock), Additionally,when I change the m from 1to 10,the output clock is not change at the same time . Does anyone have a step-by-step example with code and/or drawings that explains how to really design with the ALTPLL_RECONFIG and ALTPLL megawizard functions with m,n? Thanks !Article: 131232
Hi all,
I'm using a Virtex4 DCM with this configuration shown at the end of
the article.
I have 100MHz as input and I get as outputs 100MHz,50MHz,25MHz,200MHz.
The problem is that sometimes, apparently random, the DCM doesn't get
locked ... but I'm sure that the input is ok, I have to send to or
three resets in order to make it lock.
I also noticed that if I remove the clock and put it back the DCM
looses the locking and doesn't get it again.
I used the same configuration on a Virtex2 and I did not have these
problems.
Do you think I'm doing something wrong?
SYSTEM_DCM: DCM
generic map (
CLKFX_DIVIDE => 8,
CLKFX_MULTIPLY => 2
)
port map (
CLKIN => adc1_clk_in,
CLKFB => sys_clock_dcmfb,
DSSEN => '0',
PSINCDEC => '0',
PSEN => '0',
PSCLK => '0',
RST => my_dcm_reset,
CLK0 => sys_clock_dcm,
CLKDV => sys_clock_x05_i,
CLK2X => sys_clock_x2_i,
CLKFX => sys_clock_fx_i,
LOCKED => sys_lock
);
-- BUFG Instantiation
sys_clock_dcm_bufg: BUFG port map( I => sys_clock_dcm, O =>
sys_clock_dcmfb); --100MHz
sys_clock_x05_bufg: BUFG port map( I => sys_clock_x05_i, O =>
sys_clock_x05_o); --50MHz
sys_clock_fx_bufg : BUFG port map( I => sys_clock_fx_i, O =>
sys_clock_fx_o); --25MHz
sys_clock_2x_bufg : BUFG port map( I => sys_clock_x2_i, O =>
sys_clock_x2_o); --200MHz
ddc_pc_bufg : BUFG port map( I => sys_clock_x05_i, O =>
sys_clock_ddc_pc);
ddc_pc_x05_bufg : BUFG port map( I => sys_clock_fx_i, O =>
sys_clock_ddc_pc_x05);
ddc_pc_x2_bufg : BUFG port map( I => sys_clock_dcm, O =>
sys_clock_ddc_pc_x2);
Article: 131233What I read on the Web site seems to say it won't. I admit I haven't tried though. Does anyone know to save me the hassle? Rog. "Eric Smith" <eric@brouhaha.com> wrote in message news:m33apmvgr4.fsf@donnybrook.brouhaha.com... > Roger wrote: >> It sounds like there won't be a 64 bit Webpack - which is a shame as the >> devices covered by it are sufficient for my work and I've got a PC with >> Vista 64 bit on it! > > Won't the 32-bit WebPACK run on that? > > On Linux, 32-bit software generally runs fine on 64-bit kernels.Article: 131234
Nemesis <gnemesis2001@gmail.com> writes: > Hi all, > I'm using a Virtex4 DCM with this configuration shown at the end of > the article. > I have 100MHz as input and I get as outputs 100MHz,50MHz,25MHz,200MHz. > > The problem is that sometimes, apparently random, the DCM doesn't get > locked ... but I'm sure that the input is ok, I have to send to or > three resets in order to make it lock. > I also noticed that if I remove the clock and put it back the DCM > looses the locking and doesn't get it again. > > I used the same configuration on a Virtex2 and I did not have these > problems. How long is your reset pulse? There's a min pulse width requirement on Step 1 devices, and as I recall, it's a few clock cycles, whereas (again IIRC) on V-II is was only 2 ns. Also, how long are you leaving it to lock, it can take a while (well, 10ms for the FX outputs). Is your clock definitely within spec before you release the reset? Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 131235
On Apr 16, 12:38 pm, Martin Thompson <martin.j.thomp...@trw.com> wrote: > How long is your reset pulse? There's a min pulse width requirement > on Step 1 devices, and as I recall, it's a few clock cycles, whereas > (again IIRC) on V-II is was only 2 ns. It is about 4 us. But right now I read on the V4 user guide that 200ms is required!! I implemented a pulse stretcher ...and I'm waiting the generating process. > Also, how long are you leaving it to lock, it can take a while (well, > 10ms for the FX outputs). It has all the time it needs :-) It simply doesn't get locked (sometimes) it is not a matter of time. I can wait also 3 sec if I'm sure it get locked :-) > Is your clock definitely within spec before you release the reset? Yes, it should be ... to be clear .. it is in spec also before rising the reset. Thank you for the reply.Article: 131236
On Tue, 15 Apr 2008 14:15:25 -0400, Fei Liu <fei.liu@gmail.com> wrote: >Michael wrote: >> Howdy - I'm just beginning with FPGAs. I am using a Spartan 3E Starter >> Kit with Xilinx ISE. I am an electrical engineer by training and did >> some verilog in my collegiate days - but that was quite some time ago >> and it is all very fuzzy now. I have decided that as an EE I should be >> familiar with FPGAs - so I'm re-educating myself. With that said - >> which would be more useful to learn in the industrial world: Verilog >> or VHDL? >> >> Thanks! >> >> -Michael > >I personally found verilog very intuitive with my software engineering >background. VHDL on the other hand seems weird to me. YMMY. I personally found both Verilog and C very weird, with my software engineering background. VHDL on the other hand seems much better designed, like Modula-2. YMMV. - BrianArticle: 131237
hey,everyone! Now ,I have a board with cycloneII70 and a 91c111 ethernet controller,and I want to control the 91c111 including receive packet and send packet and so on ,but I don't want to use the ucos operating system and the lwip stack,is there anyone do the samething can give some advice,Thanks!Article: 131238
On Apr 16, 12:48 pm, Nemesis <gnemesis2...@gmail.com> wrote: > > How long is your reset pulse? There's a min pulse width requirement > > on Step 1 devices, and as I recall, it's a few clock cycles, whereas > > (again IIRC) on V-II is was only 2 ns. > > It is about 4 us. But right now I read on the V4 user guide that 200ms > is required!! > I implemented a pulse stretcher ...and I'm waiting the generating > process. I just tested the new bitfile with the 200ms DCM reset ... it seems to work fine. We'll see :-)Article: 131239
Thomas Stanka wrote:
> On 15 Apr., 22:18, Mike Treseler <mike_trese...@comcast.net> wrote:
>
>> main : process(reset, clock) is
>> -- declarations
>> begin -- process template
>> if reset = '1' then
>> init_regs;
>> elsif rising_edge(clock) then
>> update_regs;
>> end if;
>> update_ports;
>> end process main;
>> end architecture synth;
>
> This is a good style beside the fact, that a tool i recently use (I
> think synopsys dc, not 100% sure) didn't accept the update_ports part
> of such an process. Thats why I update ports usually outside the
> process.
Thanks for the report.
This style works with quartus, ise, mentor, verific and others.
Updating ports outside the process works also
but I resist adding wires when they are not
logically required.
-- Mike Treseler
Article: 131240On Apr 15, 1:23 pm, "vijayant.rutg...@gmail.com" <vijayant.rutg...@gmail.com> wrote: > hi, > i have got xilinx fft IP core from coregen. Is there any way that i > can get asic gate count for this ? Any help / hint is greatly > appreciated. > > thanks, > vijayant. You aren't going to get a corgen part into an ASIC. Just ain't gonna happen. If you build the core into a Xilinx part, then multiply the "marketing size" of the FPGA by the percentage used, you'll get a number that will give you an idea of the order of magnitude of an ASIC solution. G.Article: 131241
Michael wrote: > On Apr 15, 2:10 pm, Kevin Neilson > <kevin_neil...@removethiscomcast.net> wrote: >>> Also - is there a Xilinx simulator that is built into ISE? I am >>> following a Xilinx tutorial (http://www.xilinx.com/support/techsup/ >>> tutorials/tutorials9.htm) and it first says "Whether you use >>> the ModelSim simulator or the ISE Simulator with this tutorial, you >>> will achieve the same results." suggesting there is a fully functional >>> tutorial built into ISE, and then two paragraphs down it says "In >>> order to use this tutorial, you must install ModelSim on your >>> computer.". So that just confused me. >>> Thanks! >>> -Michael >> The most recent version of ISIM (the ISE simulator) is much faster and >> has a new parser so it supports the language(s) much better. The user >> interface is a bit coarser and the waveform viewer is not as nice as >> Modelsim's, but it might work well for you. I didn't consider this >> because it's not really free, since ISE isn't free, but if you already >> have ISE it might be a good option. -Kevin > > I'm confused - I just downloaded the "ISE WebPACK 9.2i" a couple days > ago and didn't pay a thing. (and it never asked me to pay a thing). > Does this have a built in simulator, or is it only the version that > you pay for that has a built in simulator? Thanks, > > -Michael I'm not sure if ISIM is in there--check for the executables vlogcomp.exe, vhpcomp.exe, and fuse.exe. (They should be under ise/bin/nt.) -KevinArticle: 131242
I am using xilinx xst to do the synthesis and generate a ngc file . I not using EDK at all. I tried using chipscope pro on the ngc file but it doesnt show me the inner signals. It just shows me the one main block which is the outermost level. It doesnt show the signals inside its inner blocks. I tried using the ngcbuiild -i option but still doesnt resolve the issue. -DArticle: 131243
Hi, I am trying to use the ICAP_VIRTEX4 primitive and I have two questions: 1.- There is very little documentation. I've only found information at the Virtex-4 Libraries Guide for HDL Designs. But then again, it doesn't say much about the protocol. Have anybody find more info, or successfully worked with it before? 2.- The manual says I can setup the I/O width to 8, but it doesn't seem to be working. I am using ISE 9.2 SP3 Any information will be appreciated. alonzo. -- Message posted using http://www.talkaboutelectronicequipment.com/group/comp.arch.fpga/ More information at http://www.talkaboutelectronicequipment.com/faq.htmlArticle: 131244
Hi all, I'm working on interfacing a custom IP core to a TSK3000 (Altium's P/H:MIPS-like soft processor) over WISHBONE bus and it seems I've run into some endianness problems. I've always been confused by endianness issues and now, after a few days of debugging both hardware and software, my head is ready to explode. The TSK3000's datasheet states that the processor uses only BIG endian byte ordering, so I started from that. After I created the interface for my core, connected it through Altium's "Configurable Wishbone Interconnect" and started running test apps, I observed a strange behavior which led me to further debugging and eventually to hooking up a logical analyzer to the bus. I've hardcoded WISHBONE SLAVE DAT_O(31 downto 0) to 0x44332211 and have tried different pointer games with the design and this is what bothers me: When I read form the interface using uint32_t *, I get the same hardcoded data (0x44332211). The WISHBONE specification states that the byte ordering for 32-bit BIG endian ports with byte granularity is... well.. big-endianny. I.e. BYTE(0) of a 32-bit word should be the one at DAT_O(31 downto 24), and BYTE(3) should be at DAT_O(7 downto 0). So I expect that my C variable should be 0x11223344 (?). This behavior seems a bit little-endiany to me... On the other hand, when I access the interface though uint8_t *, only SEL_I(3) is active and 0x44 is read which is the correct big endian BYTE(0). What am I doing/thinking wrong? *nisc_ctrl_8Any help/ideas would be greatly appreciated! Thanx! R.G.Article: 131245
There has to be a way to do this, right?
If I want to test a signal in the UUT, I just have to do this in my
testbench:
if(txcomstart /= '0') then
error <= x"0103";
end if;
But what if the UUT contains an instance, instance_1 (instance.vhd) and the
signal I want to test is in there?
I can bring it out of instance_1 and into the UUT and test it, but isn't
there an easier way?
like maybe:
if(/instance_1/txcomstart /= '0') then
error <= x"0103";
end if;
or maybe its this???:
if(\instance_1\txcomstart /= '0') then
error <= x"0103";
end if;
or:
if(UUT/instance_1/txcomstart /= '0') then
error <= x"0103";
end if;
I've tried just about everything I can think of and nothing seems to work.
Thanks
Dan
Article: 131246
Dan K wrote:
...
> if(UUT/instance_1/txcomstart /= '0') then
> error <= x"0103";
> end if;
> I've tried just about everything I can think of and nothing seems to work.
Maybe google for a vhdl testbench example to get started.
Here's one:
http://home.comcast.net/~mike_treseler/test_uart.vhd
-- Mike Treseler
Article: 131247On Apr 16, 12:21 am, Thomas Stanka <usenet_nospam_va...@stanka-web.de> wrote: > This is a good style beside the fact, that a tool i recently use (I > think synopsys dc, not 100% shure) didn't accept the update_ports part > of such an process. Why am I not surprised... Synopsys synthesis support for VHDL has never been very good. Now they own Synplicity, so it may get better (or it may get worse, if they direct Synplicity to remove incompatibilities with DC!) AndyArticle: 131248
On Apr 16, 3:59 pm, ni <nbg2...@gmail.com> wrote: > I am using xilinx xst to do the synthesis and generate a ngc file . I > not using EDK at all. I tried usingchipscopepro on the ngc file but > it doesnt show me the inner signals. It just shows me the one main > block which is the outermost level. It doesnt show the signals inside > its inner blocks. > I tried using the ngcbuiild -i option but still doesnt resolve the > issue. > > -D Try to set the option to keep_hierarchy during synthesis with xst. That should do it. PatrickArticle: 131249
On Wed, 16 Apr 2008 10:25:36 -0700 (PDT), ghelbig@lycos.com wrote: >On Apr 15, 1:23 pm, "vijayant.rutg...@gmail.com" ><vijayant.rutg...@gmail.com> wrote: >> hi, >> i have got xilinx fft IP core from coregen. Is there any way that i >> can get asic gate count for this ? Any help / hint is greatly >> appreciated. >> >> thanks, >> vijayant. > >You aren't going to get a corgen part into an ASIC. Just ain't gonna >happen. Not necessarily true. It is sometimes possible to buy the RTL from Xilinx for the coregen part in question. If not, one can always pay someone (ahem :-) to develop another module which duplicates the behavior.
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