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austin <austin@xilinx.com> writes:
> The CRC32 used internally is not a standard.
That's unfortunate. I can't imagine why a standard CRC polynomial
wouldn't have been used.
I wrote a brute-force CRC polynomical finder in C a few years ago:
http://nonpareil.brouhaha.com/download/crc/gencrc.c
More recently someone wrote another more general brute-force CRC parameter
finder in Perl:
http://www.lammertbies.nl/forum/viewtopic.php?t=246
I doubt that either program would be practical to find a 32-bit CRC
polynomial, though.
Article: 131751Brad Smallridge wrote: > > I haven't done any elaborate dual port BRAMs because everthing > I have done fits into a single or maybe two BRAMs. Yeah, I suppose > spreading init data among several BRAMs is not trivial and the > combining of addresses and outputs. So maybe you should spill > your requirements and see if someone can help? The whole point of inferring BRAMs is that the synthesis tool figures that out for you. You infer a single memory of whatever size you need, with whatever init data you need, and the synthesis tool figures out how to divide it up among primitives and wire them up, adding any necessary miscellaneous logic. And the synthesis tool does this just as well as coregen.Article: 131752
Hi, Is there any software/website that you guyz know that can give me rough estimate ? I tried chip estimate but it doesnt have gate counts for IPs like FIR filter. It has got a bunch of IPs without gate count estimation. Any help is greatly appreciated. Thanks, Vijayant Bhatnagar On Apr 16, 9:28=A0pm, Muzaffer Kal <k...@dspia.com> wrote: > On Wed, 16 Apr 2008 10:25:36 -0700 (PDT), ghel...@lycos.com wrote: > >On Apr 15, 1:23 pm, "vijayant.rutg...@gmail.com" > ><vijayant.rutg...@gmail.com> wrote: > >> hi, > >> i have got xilinx fft IP core from coregen. Is there any way that i > >> can get asic gate count for this ? Any help / hint is greatly > >> appreciated. > > >> thanks, > >> vijayant. > > >You aren't going to get a corgen part into an ASIC. =A0Just ain't gonna > >happen. > > Not necessarily true. It is sometimes possible to buy the RTL from > Xilinx for the coregen part in question. If not, one can always pay > someone (ahem :-) to develop another module which duplicates the > behavior.Article: 131753
Vijayant wrote:
> Is there any software/website that you guyz know that can give me
> rough estimate ? I tried chip estimate but it doesnt have gate counts
> for IPs like FIR filter.
Maybe that's because a FIR filter could use
500 gates or 500K gates.
Until you have a rough design,
you can use this estimate:
91 Wed Apr 30 /evtfs/home/tres> python
Python 2.4.2 (#1, Jan 10 2008, 17:45:02)
|>>> from random import *
|>>> randint(1e3, 1e6)
376575
-- Mike Treseler
Article: 131754Hi,everybody,I am a fresher of NIOSII,and in the passed days ,I have been familar with the nios II system,also write some test program about the gpio,timer,uart and can work properly,today I add the flash controoler(CFI),but it doesn't work.And I use the signal tap to watch the wave and the address bus is active but the read,write and cs is always '1',I don't know why,can someone give me some advice and debug methods.Article: 131755
Hi looks like ARM is easing up Cortex licensing, so it is no only available for M1 enabled Actel but pretty much ALL FPGA vendors, available at the moment however seems to be only Altera Cyclone III version distributed by Arrow for 2500 for the devkit 1 year license and license to distribute 1000 copies AnttiArticle: 131756
Thank you very much for your help. I will work on all ideas because I'm a beginner in all that, so I need time to understand everything :) XArticle: 131757
On 1 May, 11:40, Antti <Antti.Luk...@googlemail.com> wrote: > Hi > > looks like ARM is easing up Cortex licensing, so it is no only > available for M1 enabled Actel but pretty much ALL FPGA vendors, > available at the moment however seems to be only Altera Cyclone III > version > > distributed by Arrow for 2500 for the devkit 1 year license and > license to distribute 1000 copies LUTs + FMax? Cheers, JonArticle: 131758
On 1 Mai, 13:36, Jon Beniston <j...@beniston.com> wrote: > On 1 May, 11:40, Antti <Antti.Luk...@googlemail.com> wrote: > > > Hi > > > looks like ARM is easing up Cortex licensing, so it is no only > > available for M1 enabled Actel but pretty much ALL FPGA vendors, > > available at the moment however seems to be only Altera Cyclone III > > version > > > distributed by Arrow for 2500 for the devkit 1 year license and > > license to distribute 1000 copies > > LUTs + FMax? > > Cheers, > Jon 2600 LE 100mhz i think check altera web AnttiArticle: 131759
On Apr 30, 10:52=A0pm, Duane Clark <u...@domaininvalid.com> wrote: > Brad Smallridge wrote: > > > I haven't done any elaborate dual port BRAMs because everthing > > I have done fits into a single or maybe two BRAMs. =A0Yeah, I suppose > > spreading init data among several BRAMs is not trivial and the > > combining of addresses and outputs. So maybe you should spill > > your requirements and see if someone can help? > > The whole point of inferring BRAMs is that the synthesis tool figures > that out for you. You infer a single memory of whatever size you need, > with whatever init data you need, and the synthesis tool figures out how > to divide it up among primitives and wire them up, adding any necessary > miscellaneous logic. And the synthesis tool does this just as well as > coregen. Well, I have certainly got the message that those who have replied to this post think that inferred units work as well as the cores (except for certain applications such as FFTs). I don't know whether the core comparator and adder work any better than inferred modules. I haven't run any tests, nor do I intend to. My thinking is that the cores for those modules are likely to work at least as well as inferred modules and since they are already incorporated into the design, I will let well enough alone. I come to sites like this to learn from others who have more experience than I in certain areas, and I am learning. I am not a champion of cores--I don't know enough about them to be either an advocate or a detractor. In the case of the dual-port memory, I have no current application for it -- I just gave that as an example. I have used dual-port memory in other designs, but these were commercially available units not internal to an FPGA. Thanks for all of the replies; even the snippy ones are helpful. CharlesArticle: 131760
charles.elias@wpafb.af.mil wrote:
> In the case of the dual-port memory, I have no current application for
> it -- I just gave that as an example. I have used dual-port memory in
> other designs, but these were commercially available units not
> internal to an FPGA.
>
> Thanks for all of the replies; even the snippy ones are helpful.
This thread has not yet covered your original concern:
>> My problem is that I don't know how to simulate the ROM.
The big advantage of using hdl templates to
infer special features is that simulation
is simple. The synthesis code and the
simulation model are the same thing.
-- Mike Treseler
Article: 131761On May 1, 2:27 am, "bjzhan...@gmail.com" <bjzhan...@gmail.com> wrote: > Hi,everybody,I am a fresher of NIOSII,and in the passed days ,I have > been familar with the nios II system,also write some test program > about the gpio,timer,uart and can work properly,today I add the flash > controoler(CFI),but it doesn't work.And I use the signal tap to watch > the wave and the address bus is active but the read,write and cs is > always '1',I don't know why,can someone give me some advice and debug > methods. Here are two helpful links: <http://www.google.com/search?q=debug+nios> <http://www.google.com/search?q=simulate+nios> Here's something to read while you're trying to figure out how to use google's search feature: <http://www.altera.com/literature/an/an351.pdf> You really should learn about Google's search feature; it works pretty well. And it's free for google-mail users (such as yourself), and the rest of the internet. Cheers, G.Article: 131762
charles.elias@wpafb.af.mil wrote: > > Thanks for all of the replies; even the snippy ones are helpful. I apologize if I came off as snippy. Tone is hard to convey in postings, and I'll definitely try to work on that.Article: 131763
On May 1, 10:36=A0am, Duane Clark <u...@domaininvalid.com> wrote: > charles.el...@wpafb.af.mil wrote: > > > Thanks for all of the replies; even the snippy ones are helpful. > > I apologize if I came off as snippy. Tone is hard to convey in postings, > and I'll definitely try to work on that. No reason to apologize. Your posting was professional, and not "snippity". Peter AlfkeArticle: 131764
charles.elias@wpafb.af.mil wrote: > > ... I come to sites like this to learn from others who > have more experience than I in certain areas, and I am learning. I am > not a champion of cores--I don't know enough about them to be either > an advocate or a detractor. I'll make one additional comment about inferring versus core generation or instantiation. The cores and instantiated models tend to simulate very slow in comparison to inferred models. I don't know whether it will be significant for comparators and adders, but inferred memory simulates much faster. And while having complex cores like FFTs available is a nice thing, the model for the FFT simulates *extremely* slowly. It is enough to make me want to write my own, if I can just get enough free time ;)Article: 131765
Hi ! I have tried to enter the FPGA league for many years and I'm about to receive (at least ! the order was paid 6 months ago) my first prototype board with an Actel ProASIC. At last, I'll be able to go from the VHDL simulator to the VHDL synthesizer. And today, in my favorite broker's "trash bin", i find a pair of unused Xilinx parts that may also serve me, but past experiences with unmounted FPGA chips make me cautious : I have already found XC3000 parts, some in PGA packages... Even an IKOS emulator http://ygdes.com/ikos/ with hundreds of FPGAs, but that are not supported anymore :-( The reference of today's find : Virtex XCV400 HQ240AFP0241 So it's a 240-pin PQFP package that i can rather easily solder :-) but the marking implies a 2002 fab date, and i don't know if it's still possible to find SW that supports this part ... Would it be worth it to create a small dev PCB ? (and if the synth SW can run on Linux, that's a plus) A google search will give results but not tell me if it is useful, and if there is some hope to configure it to something fun. Because besides the 2 FPGA, i have also found a bunch of SDRAM chips and 2MB FLASH chips :-) (plus a whole lot of things i already have) yg, puzzled and clueless ....Article: 131766
Ok. I have my design finalized. The fir length would be 64 operating on 32 bit wide word. Now could you please hint me on estimating gate count ? Help appreciated, Vijayant. On May 1, 2:30=A0am, Mike Treseler <mike_trese...@comcast.net> wrote: > Vijayantwrote: > > Is there any software/website that you guyz know that can give me > > rough estimate ? I tried chip estimate but it doesnt have gate counts > > for IPs like FIR filter. > > Maybe that's because a FIR filter could use > 500 gates or 500K gates. > > Until you have a rough design, > you can use this estimate: > > 91 Wed Apr 30 /evtfs/home/tres> python > Python 2.4.2 (#1, Jan 10 2008, 17:45:02) > |>>> from random import * > |>>> randint(1e3, 1e6) > 376575 > > =A0 =A0 -- Mike TreselerArticle: 131767
"XSterna" <XSterna@gmail.com> wrote in message news:6e540612-5af3-4031-851e-ed4a27d20bc8@m3g2000hsc.googlegroups.com... > > I will work on all ideas because I'm a beginner in all that, so I need > time to understand everything :) Basically your supervisor told you that the FPGA will be used to store an arbitrary waveform and to send it to the DAC. No math is supposed to be done in it. You are supposed to use MATLAB to design the waveform and then upload (or is it download? :)) it to the memory in the FPGA. The FPGA will then simply read it back with the DAC sample rate... If you don't need to change your waveform quickly and/or you need to be able to "play back" some other waveforms then it is the way to go. Otherwise you could drop the MATLAB part and design your own hardware chirp generator as Kevin described. /MikhailArticle: 131768
whygee wrote: > Hi ! > > I have tried to enter the FPGA league for many years and I'm about > to receive (at least ! the order was paid 6 months ago) my first > prototype board with an Actel ProASIC. > At last, I'll be able to go from the VHDL simulator > to the VHDL synthesizer. > > And today, in my favorite broker's "trash bin", i find > a pair of unused Xilinx parts that may also serve me, > but past experiences with unmounted FPGA chips make me cautious : > I have already found XC3000 parts, some in PGA packages... > Even an IKOS emulator http://ygdes.com/ikos/ with hundreds > of FPGAs, but that are not supported anymore :-( > > The reference of today's find : > Virtex XCV400 > HQ240AFP0241 > > So it's a 240-pin PQFP package that i can rather easily solder :-) > but the marking implies a 2002 fab date, and i don't know if it's > still possible to find SW that supports this part ... > Would it be worth it to create a small dev PCB ? > (and if the synth SW can run on Linux, that's a plus) That is definitely a very large (for it's time) and useful part. And it looks like even webpack now supports it, and webpack is now available for Linux. So sure, I would say go for it.Article: 131769
whygee wrote: > Hi ! > > I have tried to enter the FPGA league for many years and I'm about > to receive (at least ! the order was paid 6 months ago) my first > prototype board with an Actel ProASIC. > At last, I'll be able to go from the VHDL simulator > to the VHDL synthesizer. > > And today, in my favorite broker's "trash bin", i find > a pair of unused Xilinx parts that may also serve me, > but past experiences with unmounted FPGA chips make me cautious : > I have already found XC3000 parts, some in PGA packages... > Even an IKOS emulator http://ygdes.com/ikos/ with hundreds > of FPGAs, but that are not supported anymore :-( By the way, Xilinx is pretty good about making available old versions of their software to use on older parts. And while some of the older software is not available in Linux versions, most of it ran quite well under Wine.Article: 131770
On Apr 30, 9:03 am, austin <aus...@xilinx.com> wrote: Hi Austin, That was exactly our problem, however for a slightly different reason than I originally indicated. We were actually using the CLKFX outputs, which don't have that limitation, but using the LOCKED signal to enable the rest of the system, and it wasn't asserting due to the input frequency being too low. The new batch is indeed from a newer lot of FPGAs and apparently they're much less tolerant than the previous batch. Thanks for your help, Mike.Article: 131771
On May 1, 3:44 pm, whygee <why...@yg.yg> wrote: > Hi ! > > I have tried to enter the FPGA league for many years and I'm about > to receive (at least ! the order was paid 6 months ago) my first > prototype board with an Actel ProASIC. > At last, I'll be able to go from the VHDL simulator > to the VHDL synthesizer. Ugh. Those flash based FPGAs are not fun at all compared to SRAM based ones. Hope you get everything right in the simulator (and can simulate it all) because the programming cycle takes drastically longer. If you want to get something done by way of gaining experience, get a modern inexpensive dev board with a spartan or cyclone part.Article: 131772
thanks for the comment, cs_posting@hotmail.com wrote: > On May 1, 3:44 pm, whygee <why...@yg.yg> wrote: >> Hi ! >> >> I have tried to enter the FPGA league for many years and I'm about >> to receive (at least ! the order was paid 6 months ago) my first >> prototype board with an Actel ProASIC. >> At last, I'll be able to go from the VHDL simulator >> to the VHDL synthesizer. > > Ugh. Those flash based FPGAs are not fun at all compared to SRAM based ones. well, a long time ago, I had a lot of fun with ... antifuse parts :-) there were Actel A1020 dev tools at my engineers' school and I was fond of this architecture, not to mention the Mentor Graphics GUI ! (on oooooold HP Apollo workstations, oh God..... now, THAT was slow even by that day's standards.) I'm targetting "embedded applications", so the startup time and the parts count also matter. Going for Actel is also because I'm fed up of having to choose between the 2 other leaders. > Hope you get everything right in the simulator (and can simulate it all) because > the programming cycle takes drastically longer. sure, that's part of the deal :-) but even a slow devkit would be infinitely faster than ... nothing :-) > If you want to get something done by way of gaining experience, get a > modern inexpensive dev board with a spartan or cyclone part. well, maybe this couple of Virtex chips is another opportunity for this. Furthermore, I aim at maximal VHDL source code compatibility with the major architectures, so a second "target" is not a bad thing. Now, let's hope that my broker will dump not too old Altera parts. YGArticle: 131773
Thanks for the encouraging and very fast answers ! Duane Clark wrote: >> And today, in my favorite broker's "trash bin", i find >> a pair of unused Xilinx parts that may also serve me, >> but past experiences with unmounted FPGA chips make me cautious : >> I have already found XC3000 parts, some in PGA packages... >> Even an IKOS emulator http://ygdes.com/ikos/ with hundreds >> of FPGAs, but that are not supported anymore :-( > > By the way, Xilinx is pretty good about making available old versions of > their software to use on older parts. And while some of the older > software is not available in Linux versions, most of it ran quite well > under Wine. Let's see in my oldienosaur collection : 4x Xilinx XC4010-5 PG191C (191-pin ceramic PGA) 2x XC3195A-4 PP175C (175-pin plastic grid array) A year ago, i was not able to find any support for them :-/ Now for the "big players" : 23x Altera Flex10K marked EPF10K130VBC600-2 / ABA340007 that's 2000-dated parts in terrifying 600-pin fine pitch BGA. I got them 1 year ago and have been unsuccessful with them. The Xilinx parts in the IKOS Pegasus emulator are all BGA, and they are ok as they are soldered, but i have no idea of the PCB interconnexion .... so despite finding some basic documentation about them, they are desperately useless too :-( (see http://ygdes.com/ikos/boards.jpg ) In fact the only way to use it would be to find all the SW and schematics of the original manufacturer, which AFAIK has been bought (swallowed, assimilated and crushed) a loooong time ago by Mentor... what should I do ? (I have no use for the 1000A 3,3V power supply as is) Just for the information : one of my applications for FPGA is to implement http://yasep.org/, and I also want to develop some crude digital camera processing similar to the CMUcam. So unlike with F-CPU, I don't need extreme speed and densities, just something that works and can interface with 5V or 3,3V parts borrowed from other electronic stuffs (SRAM, SDRAM, microcontrollers, ISA buses, ...) Regards, ygArticle: 131774
rossalbi wrote: > > Hi people... > > I am trying to find a vhdl code for 3x3 sobel algorithm to implement > on a Spartan 3, FPGA. > > I have found many papers on the subject but they are all from a high > level of abstraction and none include any actual code. > > Any help would be greatly appreciated. > > Ross Albi The greatest challenge probably isn't the Sobel computer itself but the memory management. If the image/video frame is too large to fit in the FPGA, you'll have to have an external memory controller and line buffers, etc. -Kevin
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