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I am trying to get rams in xilinx to synthesize in synplify pro. I am a novice in syplify pro. I used the core generator to generate BRAM and then since for brams we cannot generate edif files I used ngc2edif to convert it to .ndf. I then added these ndf files into the project. Howewver I seem to get an error with the synplify pro.The core is a simple dual port RAM with a write port A and a read port B The error is following. I dont know how the synplify pro picksup the component from unisim. I have given the components name as ramb16_s18_s18. ERROR : Port web of entity unisim.ramb16_s18_s18 is unconnected The error is regarind port web which is a writ eenable prot of b . but port b is just a read port with we disabled.Article: 130801
Frank Buss wrote:
> austin wrote:
>
>
>>It is shipping, as ES. Right now.
>>
>>The early access program is now over, and we have already been shipping
>>ES parts, for quite awhile.
>
>
> What means ES? At your online store:
>
> http://www.xilinx.com/onlinestore/silicon/online_store_v5.htm
>
> I don't see it. How much will it cost?
>
> I'm working for a company, who plans a new product and we are evaluating
> new chips. Do you know the new AT91SAM9263?
>
> http://www.atmel.com/dyn/resources/prod_documents/6249s.pdf
>
> This chip costs about $19 for 100 units ( http://tinyurl.com/36wbud ) and I
> have quotes of $13 for 1000 units. But our product needs some FPGA and DSP
> power, too. A single chip solution like the Virtex-5 FXT, sounds like an
> interesting idea, but how much does the IP cost for USB, ethernet, LCD
> controller, 2D graphics accelerator etc., which I get for free with the
> Atmel chip, a free Linux distribution included?
Custom, high volume silicon will always be cheaper than FPGA - so you
should do as much with std blocks as possible, and use the smallest
FPGA that will sweep-up the rest.
NXP also have some new ARM 9 releases ?
http://www.standardics.nxp.com/products/lpc3000/lpc32x0/
"Pricing: Ranges from $6.95 to $8.25 in 10K volumes.
Availability: Sampling in April with volume shipping in the third
quarter of 2008."
>
> The Atmel chip, with some small integrated FPGA capabilities, like Spartan,
> would be the ideal solution for our product. Currently we are planning to
> use an additional small FPGA and some inexpensive DSPs from Freescale.
You have seen the AT91CAP9 and AT91CAP7 series ?
These have NRE, but DO combine Low power CPU and a FPGA.
The prototype flow I think uses Altera.
-jg
From invalid@dont.spam Tue Apr 01 20:46:32 2008
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From: Phil Hays <invalid@dont.spam>
Subject: Re: ISE 10.1 - Initial experience
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Andy Peters wrote:
> I really wanna know: when are they going to shitcan the binary ISE project
> file and go back to a text file? You know, some of us actually LIKE things
> we can put into our source-code control systems.
I'd like to think we are making progress on this. I've been preaching
"Source Control Friendly" for a while, and some seem to be listening.
With 10.1, you don't need to rely on the binary .ise file. You can use Tcl
for a project file. Check out the Project => generate Tcl script... feature.
To use this script as the project file you need just a bit of other Tcl to
handle setup of a project directory and saving the script, if you export
it.
As an example: save what follows to a Tcl script (project.tcl in a "src"
directory at the same level as your current ise directory. Open Project
Navigator and export a Tcl script to the default name and location. I
suggest having the top radio button checked:
(All properties with complete script).
Then exit Project Navigator. Copy this script to the src directory. Edit
the script to make the names match. Save the bld directory if there is
anything in it. This script does assume that none of your source files
are in the ise directory. There are other ways to use the exported Tcl
script, this is an example.
Assuming Windows, create a shortcut (Linux "Launcher") with a command of:
xtclsh path_to_your_project\src\project.tcl
Set the directory to start in to:
path_to_your_project\src\
Double click the shortcut. Script takes about 30 seconds to run. YMMV
Assuming you don't want a shortcut or launcher (Also easier to debug
if the shortcut doesn't work):
Open a terminal window.
cd path_to_your_project/src/
xtclsh project.tcl
Every time you run the project.tcl script, it creates a temporary .ise file.
You can save settings by just "project => generate Tcl script..." again,
and the saved settings will be copied back to the src directory. If you
don't save settings, the script in src doesn't change. Check the project.tcl
and the somename.tcl files into source control, and remove the .ise file.
If you don't like it, please let me know why.
Phil Hays
--- Save as project.tcl ----
#######################################################
#
# Set these to match your project name
#
set myProject "somename.ise"
set myScript "somename.tcl"
#
puts "loading project settings from $myScript"
#
# Now get the procedures loaded from the script file
#
source "$myScript"
#
puts "Done with $myScript. Making fresh build directory"
cd ..
file delete -force bld
file mkdir bld
cd bld
puts "Start of rebuild_project procedure"
#
# This is a call to a procedure defined by myScript. This project builds
# an ise project from the settings saved.
# We know that there isn't an existing project file as we just created the
# directory, otherwise this was copied from "rebuild_project"
global myScript
global myProject
project new $myProject
set_project_props
add_source_files
create_libraries
create_partitions
set_process_props
puts "$myScript: project rebuild completed."
# Note: catch is needed as ise throws off bogus return messages
if {[catch {exec ise $myProject} isemessage] } {
puts "ISE returned: $isemessage"
} else {
puts "ISE returned no message (normal exit)"
}
if {[file exists $myScript] } {
puts "Saving updated Tcl Export file"
file rename -force [file join "../src/" $myScript] \
[file join "../src/" $myScript.old]
file copy $myScript [file join "../src/" $myScript]
}
#
puts "Done"
#
From invalid@dont.spam Tue Apr 01 21:11:35 2008
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From: Phil Hays <invalid@dont.spam>
Subject: Re: ISE 10.1 - Initial experience
User-Agent: Pan/0.14.2.91 (As She Crawled Across the Table)
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Newsgroups: comp.arch.fpga
References: <06f833f3-110b-427c-baa2-96c012ea2e80@d21g2000prf.googlegroups.com> <3b97b9f0-a29a-4645-a64d-ef5d7e2275bf@b5g2000pri.googlegroups.com> <pan.2008.04.02.03.46.32.154258@dont.spam>
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Phil Hays wrote:
Yes, talking to myself.
At least in my newreader, the script is kinda munged. Sorry.
Try this:
http://mysite.verizon.net/fastfpga/project.tcl
--
Phil Hays
Article: 130802"Torsten Landschoff" <t.landschoff@gmx.de> wrote in message news:ee7e1353-2896-4df0-b1dc-bc05315e9848@t54g2000hsg.googlegroups.com... > > Also, while the time from the FF > to the pad is well defined, I can't be sure how the routing delay from > the DCM-generated clock to the pad will be. The standard solution is to regenerate the output clock with a DDR register in IOB. Check the following link for how it can be done: http://www.xilinx.com/support/answers/15194.htm If you put your data output register in IOB as well you will have a well defined source-synchronous interface. Its timing will only get better in any future silicon... /MikhailArticle: 130803
Hi Mikhail, On 2 Apr., 07:22, "MM" <mb...@yahoo.com> wrote: > > Also, while the time from the FF > > to the pad is well defined, I can't be sure how the routing delay from > > the DCM-generated clock to the pad will be. > > The standard solution is to regenerate the output clock with a DDR register > in IOB. Check the following link for how it can be done:http://www.xilinx.com/support/answers/15194.htm Thanks for the pointer. I also found application note xapp265 about high speed data (de-)serialization.But it feel like a lot of overkill to use all this Xilinx magic to drive a simple 50 MHz SPI device... After all I have a 5 ns window on the serial data line to set up the next bit - it can't be too hard to achieve this with a Virtex 4 while keeping the behavioural, portable VHDL design!? Also, I fear that having a falling clock and changing the data line at the same instant could be too critical - I'd rather have the clock transition a bit before the data setup. (The DAC requires a hold time equal to the clock high period). > If you put your data output register in IOB as well you will have a well > defined source-synchronous interface. Its timing will only get better in any > future silicon... I placed the output FFs into the IOB, and I now meet the timing constraints defined below. But I don't know how long the clock takes to travel from the BUFG to the pad. Assuming that it takes 0 - 5 ns, all will be fine for my requirements. Thanks for your suggestions! TorstenArticle: 130804
Hi again, On 2 Apr., 07:22, "MM" <mb...@yahoo.com> wrote: > If you put your data output register in IOB as well you will have a well > defined source-synchronous interface. Its timing will only get better in any > future silicon... I forgot to mention that we are going to connect the same DAC so a Spartan 3E as well, which I expect to have a slower timing (did not check though). Would be nice if we could just reuse the interface code. :) Greetings, TorstenArticle: 130805
Hi, I have added Chipscope to my design, but it seems to be incompatible because of BSCANS: Number of BSCANs: 2 out of 1 200% (OVERMAPPED). The reason is that I need to use OPB_MDM since I have to download the executable.elf. I have read that it is possible to use OPB_MDM and Chipscope if they share the BSCAN. Could someone tell me how could i configure it? RegardsArticle: 130806
On 2 Apr., 11:01, Pablo <pbantu...@gmail.com> wrote: > Hi, I have added Chipscope to my design, but it seems to be > incompatible because of BSCANS: > Number of BSCANs: 2 out of 1 200% (OVERMAPPED). The reason is that I > need to use OPB_MDM since I have to download the executable.elf. > > I have read that it is possible to use OPB_MDM and Chipscope if they > share the BSCAN. Could someone tell me how could i configure it? > > Regards Hi Pablo, I know that from silicon side it is possible, but Xilinx SW can not handle it. Best RegardsArticle: 130807
On Wed, 2 Apr 2008 04:32:07 -0700 (PDT), tarmopalm@gmx.de wrote: >On 2 Apr., 11:01, Pablo <pbantu...@gmail.com> wrote: >> Hi, I have added Chipscope to my design, but it seems to be >> incompatible because of BSCANS: >> Number of BSCANs: 2 out of 1 200% (OVERMAPPED). The reason is that I >> need to use OPB_MDM since I have to download the executable.elf. >> >> I have read that it is possible to use OPB_MDM and Chipscope if they >> share the BSCAN. Could someone tell me how could i configure it? >> >> Regards > >Hi Pablo, > >I know that from silicon side it is possible, but Xilinx SW can not >handle it. > Xilinx SW does handle it. What I see is you are using some silicon with only one BSCAN. Which piece is it?Article: 130808
On 2 Apr., 11:01, Pablo <pbantu...@gmail.com> wrote: > I have read that it is possible to use OPB_MDM and Chipscope if they > share the BSCAN. Could someone tell me how could i configure it? A bit of googling turned up this answer: You must create a new chipscope icon with Disable Boundary Scan Component Instance. hta will give you an Icon with more ports than usual, these ports must be connected to the corresponding ports of the opb_mdm component (use Show ports with default connections when connecting ports) Source: http://groups.google.de/group/comp.arch.fpga/browse_frm/thread/5ca58a14fdf4b389/54152b6f02c203ec?lnk=gst&q=You+must+create+a+new+chipscope+icon+with+Disable+Boundary+Scan#54152b6f02c203ec HTH, TorstenArticle: 130809
Jon, Read the news articles: "over 1,000 devices shipped to over 100 customers." I didn't know if this was a secret, but since it has been published in two separate magazines, I will quote them, quoting us. AustinArticle: 130810
On Apr 1, 8:50 pm, "Symon" <symon_bre...@hotmail.com> wrote: > paragon.j...@gmail.com wrote: > > On Apr 1, 10:59 am, austin <aus...@xilinx.com> wrote: > >>http://biz.yahoo.com/prnews/080331/aqm029a.html?.v=7 > > >> Ta Da! > > >> Austin > > > I am salivating over the SX240T. Any idea of when it will be > > available and for how much? > > Ding ding. > > http://en.wikipedia.org/wiki/Ivan_Pavlov > > HTH, Syms. This isn't a matter of Pavlov. I actually do have applications where an SX240T would be far more appropriate than any previously available chip.Article: 130811
Hey, Im trying some synthesis with Xilinx Xst in ISE 9.2 and i'm getting this error ERROR:Xst:2259 - Unit <chip> has internal Xst_Choice nodes Anyone know what an Xst_Choice node is? I've no idea what it is - maybe something to do with my coregen cores? Can't find an explanation for ERROR 2259 anywhere either??? Any help wud be cool, Cheers, Rob.Article: 130812
A choice not is an pseudo gate in a netlist data structure. At it's fanin the choice node presents multiple alternatives to compute the same result. The mapper must than choose one of the alternatives. After mapping there should be no more choicenodes left in the circuit. Apparently the mappter forgot some in your case. See also: http://embedded.eecs.berkeley.edu/Respep/Research/mvsis/techmapping.html Kolja Sulimma On 2 Apr., 15:20, robquig...@gmail.com wrote: > Hey, > > Im trying some synthesis with Xilinx Xst in ISE 9.2 and i'm getting > this error > > ERROR:Xst:2259 - Unit <chip> has internal Xst_Choice nodes > > Anyone know what an Xst_Choice node is? I've no idea what it is - > maybe something to do with my coregen cores? > > Can't find an explanation for ERROR 2259 anywhere either??? > > Any help wud be cool, > > Cheers, > > Rob.Article: 130813
ni wrote:
> I am trying to get rams in xilinx to synthesize in synplify pro. I am
> a novice in syplify pro. I used the core generator to generate BRAM
> and then since for brams we cannot generate edif files I used ngc2edif
> to convert it to .ndf. I then added these ndf files into the project.
> Howewver I seem to get an error with the synplify pro.The core is a
> simple dual port RAM with a write port A and a read port B
> The error is following. I dont know how the synplify pro picksup the
> component from unisim.
> I have given the components name as ramb16_s18_s18.
>
> ERROR : Port web of entity unisim.ramb16_s18_s18 is unconnected
>
> The error is regarind port web which is a writ eenable prot of b . but
> port b is just a read port with we disabled.
>
Rather than actually answer the question, can I suggest that you infer
BRAM rather than go through that complicated process? As a bonus,
inferred BRAM simulates much faster. You would infer BRAM something like:
architecture synth of pp_ram is
constant MEM_DEPTH : integer := 2**AWIDTH;
type mem_array is array(0 to MEM_DEPTH-1) of
std_logic_vector(DWIDTH-1 downto 0);
signal ram : mem_array;
signal rd_addr_ram : unsigned(AWIDTH-1 downto 0);
signal ADDRA : unsigned(AWIDTH-1 downto 0);
signal ADDRB : unsigned(AWIDTH-1 downto 0);
signal DIA : std_logic_vector(DWIDTH-1 downto 0);
signal DOB : std_logic_vector(DWIDTH-1 downto 0);
begin
-- infer block RAM
wr_p: process(CLKI)
begin
if rising_edge(CLKI) then
if WE = '1' then
ram(to_integer(ADDRA)) <= std_logic_vector(DIA);
end if;
end if;
end process wr_p;
rd_p: process(CLKO)
begin
if rising_edge(CLKO) then
rd_addr_ram <= ADDRB;
end if;
end process rd_p;
DOB <= ram(to_integer(rd_addr_ram));
Article: 130814
I installed the 10.1 ISE Webpack. The pack installed successfully
except for the driver. I have found(http://www.rmdir.de/~michael/
xilinx/) that in 10.1 the driver is prepackaged. I enabled the
environment variable(XIL_IMPACT_USE_LIBUSB to 1) and tried to
reinstall the driver. This resulted in the same error as before:
Wed Apr 02 11:58:45 TZ 2008:: summary= Driver installation failed.
Please check the <Install Destination Directory>/.xinstall/install.log
file for more information on the cause of the installation failure.
Any ideas as to how to resolve this?
Here is the entire install.log:
--Driver versions in this package: windrvr=900, xpc4drvr=1041
--Script name = /home/b/Xilinx/10.1/common/bin/lin/install_script/
install_drivers/install_drivers
--Current working dir = /home/b/10webinstall
--Script location = /home/b/10webinstall
**********************************
Wed Apr 02 11:45:59 TZ 2008:: version= 10.1
Wed Apr 02 11:45:59 TZ 2008:: summary= previous:
Wed Apr 02 11:45:59 TZ 2008:: summary= update:
Wed Apr 02 10:54:16 TZ 2008:: summary= destination directory: /home/b/
Xilinx/10.1
Wed Apr 02 10:54:16 TZ 2008:: summary= registration id:
18DEAGY42MJXSWSEXHYNG35KP
Wed Apr 02 10:54:16 TZ 2008:: summary= selected: /home/b/Xilinx/10.1
Wed Apr 02 10:54:16 TZ 2008:: summary= selected: Launch XilinxUpdate
Wed Apr 02 10:54:16 TZ 2008:: summary= selected: Install Cable
Drivers
Wed Apr 02 10:54:16 TZ 2008:: summary= selected:
Wed Apr 02 10:54:16 TZ 2008:: summary= selected: ISE Design Tools
Wed Apr 02 10:54:16 TZ 2008:: summary= selected: Install Path: /home/
b/Xilinx/10.1/ISE
Wed Apr 02 10:54:16 TZ 2008:: summary= selected: XILINX = /home/b/
Xilinx/10.1/ISE
Wed Apr 02 10:54:16 TZ 2008:: summary= selected: PATH = ${XILINX}/
bin/${PLATFORM}
Wed Apr 02 10:54:16 TZ 2008:: summary= selected: LMC_HOME = $
{XILINX}/smartmodel/${PLATFORM}/installed_${PLATFORM}
Wed Apr 02 10:54:16 TZ 2008:: summary= selected: LD_LIBRARY_PATH = $
{XILINX}/lib/${PLATFORM}:/usr/X11R6/lib:${LMC_HOME}/lib/linux.lib:$
{LMC_HOME}/lib/amd64.lib
Wed Apr 02 10:54:16 TZ 2008:: summary= selected: Design Environment
Tools
Wed Apr 02 10:54:16 TZ 2008:: summary= selected: CPLD
Wed Apr 02 10:54:16 TZ 2008:: summary= selected: All FPGA devices
except Virtex4 and Virtex5
Wed Apr 02 10:54:16 TZ 2008:: summary= selected: Virtex4 and Virtex5
FPGA devices
Wed Apr 02 10:54:16 TZ 2008:: summary= selected: Enable WebTalk
Wed Apr 02 10:54:16 TZ 2008:: summary= selected: Set Xilinx Registry
Wed Apr 02 11:45:14 TZ 2008:: summary= Post-GUI updates completed.
Wed Apr 02 11:45:49 TZ 2008:: summary= Driver installation failed.
Please check the <Install Destination Directory>/.xinstall/install.log
file for more information on the cause of the installation failure.
Wed Apr 02 11:45:58 TZ 2008:: summary= fileset.txt written.
Wed Apr 02 11:45:59 TZ 2008:: summary= Install has
completed.
--Driver versions in this package: windrvr=900, xpc4drvr=1041
--Script name = /home/b/Xilinx/10.1/common/bin/lin/install_script/
install_drivers/install_drivers
--Current working dir = /home/b/10webinstall
--Script location = /home/b/10webinstall
**********************************
Wed Apr 02 11:58:48 TZ 2008:: version= 10.1
Wed Apr 02 11:58:48 TZ 2008:: summary= previous:
Wed Apr 02 11:58:48 TZ 2008:: summary= update:
Wed Apr 02 11:58:28 TZ 2008:: summary= destination directory: /home/b/
Xilinx/10.1
Wed Apr 02 11:58:28 TZ 2008:: summary= registration id:
18DEAGY42MJXSWSEXHYNG35KP
Wed Apr 02 11:58:28 TZ 2008:: summary= selected: /home/b/Xilinx/10.1
Wed Apr 02 11:58:28 TZ 2008:: summary= selected: Launch XilinxUpdate
Wed Apr 02 11:58:28 TZ 2008:: summary= selected: Install Cable
Drivers
Wed Apr 02 11:58:28 TZ 2008:: summary= selected:
Wed Apr 02 11:58:28 TZ 2008:: summary= selected: ISE Design Tools
Wed Apr 02 11:58:28 TZ 2008:: summary= selected: Install Path: /home/
b/Xilinx/10.1/ISE
Wed Apr 02 11:58:28 TZ 2008:: summary= selected: XILINX = /home/b/
Xilinx/10.1/ISE
Wed Apr 02 11:58:28 TZ 2008:: summary= selected: PATH = ${XILINX}/
bin/${PLATFORM}
Wed Apr 02 11:58:28 TZ 2008:: summary= selected: LMC_HOME = $
{XILINX}/smartmodel/${PLATFORM}/installed_${PLATFORM}
Wed Apr 02 11:58:28 TZ 2008:: summary= selected: LD_LIBRARY_PATH = $
{XILINX}/lib/${PLATFORM}:/usr/X11R6/lib:${LMC_HOME}/lib/linux.lib:$
{LMC_HOME}/lib/amd64.lib
Wed Apr 02 11:58:28 TZ 2008:: summary= selected: Set Xilinx Registry
Wed Apr 02 11:58:45 TZ 2008:: summary= Driver installation failed.
Please check the <Install Destination Directory>/.xinstall/install.log
file for more information on the cause of the installation failure.
Wed Apr 02 11:58:47 TZ 2008:: summary= fileset.txt written.
Wed Apr 02 11:58:48 TZ 2008:: summary= Install has completed.
Article: 130815On 1 Apr., 14:31, "Nial Stewart" <nial*REMOVE_TH...@nialstewartdevelopments.co.uk> wrote: > I've read all the posts here but have lost track of how you're > getting on. > > Can you post an update and describe what the problem turned out > to be? > > Nial. Quote from Actel website: "In March 2008, it was discovered that a potential advanced optimization could cause a logic gating of a global signal. This optimization is part of a set of other routing optimizations that could be invoked if a user sets the Routing High Effort Mode in the Advanced Option of the Layout." This is fixed in Libero 8.3 released march 31 2008 I use the exact target device and setting as described at actel website, so I assume at least some of the mess i have had may as well be caused by this global signal gating in high effort mode. Folks, dont think I am not trying hard enough, I am, but the tools sometimes choke as well. The code that I currently have, and that is randomly failing, whatever constraints, in any normal FPGA fabric with no tool injected mess, it SHOULD WORK, but it isnt. Of course, the tools should be the last thing to blaim on, but sometimes they are the root of evil I try the 8.3 tools and hope it is fixing the issues i have AnttiArticle: 130816
disq <rettura@gmail.com> wrote: > I installed the 10.1 ISE Webpack. The pack installed successfully > except for the driver. I have found(http://www.rmdir.de/~michael/ > xilinx/) that in 10.1 the driver is prepackaged. I enabled the > environment variable(XIL_IMPACT_USE_LIBUSB to 1) and tried to > reinstall the driver. This resulted in the same error as before: If you have an USB cable, the driver probably doesn't need to be installed any longer. Did you actually try run run impact with XIL_IMPACT_USE_LIBUSB set? If you run with the LD_PRELOAD method at least no driver needs to be installed. -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 130817
On Apr 1, 8:46 pm, Phil Hays <inva...@dont.spam> wrote: > Andy Peters wrote: > > I really wanna know: when are they going to shitcan the binary ISE project > > file and go back to a text file? You know, some of us actually LIKE things > > we can put into our source-code control systems. > > I'd like to think we are making progress on this. I've been preaching > "Source Control Friendly" for a while, and some seem to be listening. > > With 10.1, you don't need to rely on the binary .ise file. You can use Tcl > for a project file. Check out the Project => generate Tcl script... feature. > > To use this script as the project file you need just a bit of other Tcl to > handle setup of a project directory and saving the script, if you export > it. > > If you don't like it, please let me know why. I like it! -aArticle: 130818
On Apr 2, 11:35 am, Duane Clark <u...@domaininvalid.com> wrote: > ni wrote: > > I am trying to get rams in xilinx to synthesize in synplify pro. I am > > a novice in syplify pro. I used the core generator to generate BRAM > > and then since for brams we cannot generate edif files I used ngc2edif > > to convert it to .ndf. I then added these ndf files into the project. > > Howewver I seem to get an error with the synplify pro.The core is a > > simple dual port RAM with a write port A and a read port B > > The error is following. I dont know how the synplify pro picksup the > > component from unisim. > > I have given the components name as ramb16_s18_s18. > > > ERROR : Port web of entity unisim.ramb16_s18_s18 is unconnected > > > The error is regarind port web which is a writ eenable prot of b . but > > port b is just a read port with we disabled. > > Rather than actually answer the question, can I suggest that you infer > BRAM rather than go through that complicated process? As a bonus, > inferred BRAM simulates much faster. You would infer BRAM something like: > > architecture synth of pp_ram is > > constant MEM_DEPTH : integer := 2**AWIDTH; > type mem_array is array(0 to MEM_DEPTH-1) of > std_logic_vector(DWIDTH-1 downto 0); > signal ram : mem_array; > signal rd_addr_ram : unsigned(AWIDTH-1 downto 0); > > signal ADDRA : unsigned(AWIDTH-1 downto 0); > signal ADDRB : unsigned(AWIDTH-1 downto 0); > signal DIA : std_logic_vector(DWIDTH-1 downto 0); > signal DOB : std_logic_vector(DWIDTH-1 downto 0); > > begin > -- infer block RAM > wr_p: process(CLKI) > begin > if rising_edge(CLKI) then > if WE = '1' then > ram(to_integer(ADDRA)) <= std_logic_vector(DIA); > end if; > end if; > end process wr_p; > rd_p: process(CLKO) > begin > if rising_edge(CLKO) then > rd_addr_ram <= ADDRB; > end if; > end process rd_p; > DOB <= ram(to_integer(rd_addr_ram)); My confusion is if I write this code to infer RAMS then once I do the synthesis and then go to place and route then would it still be considered as a BRAM? I thought Xilinx brams(generated through CORE Generator ) would be much more optimised then inferred RAMS in synplify since ultimately we would be using xilinx PAR.Article: 130819
>removing the 100mhz oscillator :) Didn't that defeat the purpose of the pcb ..? :) >that PCB proto was SO BAD that no powersupply bypassing helped.. i >tried and looked with the scope So a new pcb was made..?, what was explicitly changed..? >BTW it was weird, i was also using lab power supply, so while sweeping >the VCC i could see the JTAG ID to change from virtex to spartan and >then failing completly sweeping Vcc?, iee overlaying a variable amplitude and frequency signal onto Vcc? By the way.. is switch regualator ripple a big issue for spartan fpga?Article: 130820
I'm getting a fatal error when I try and simulate a Virtex 5 VHDL project with a block memory core built with coregen. The Virtex 5 Coregen is only allowing Block Memory Generator V2.6 to be used. I see these files in the $XILINX\vhdl\src\XilinxCoreLib directory, but they do not show up in the ModelSim workspace under xilinxcorelib which only goes up to blk_mem_gen_v2_4. Does anyone know what I need to do to get ModelSim to start using these (newer) block mem gen files? Thanks DanArticle: 130821
ni wrote: > > My confusion is if I write this code to infer RAMS then once I do the > synthesis and then go to place and route then would it still be > considered as a BRAM? I thought Xilinx brams(generated through CORE > Generator ) would be much more optimised then inferred RAMS in > synplify since ultimately we would be using xilinx PAR. Using coregen definitely does not result in optimization during PAR (or MAP for that matter). When Synplify (or any synthesis tool) creates the edif file that will be used by the Xilinx tools, it puts primitives in there including BRAMs if they are correctly inferred in your code. It is useful to check the log file of the synthesis tool to verify that the expected number of BRAMs were inferred. If not, that might point to something you did wrong when inferring them.Article: 130822
On Mar 27, 10:19=A0am, Jon Elson <el...@pico-systems.com> wrote: > Georg Acher wrote: > > Jon Elson <el...@pico-systems.com> writes: > > >>Georg Acher wrote: > > >>>I have XCS10XL in TQFP100 from around 1999/2000 and they also have prin= ted > >>>labels. They were obtained from the official German distri at that time= > >>>(Metronik/Unique). So I guess that white ink labels are no sign of unof= fical > >>>chips... > > >>But, I have no other examples of Spartan chips which DON'T have > >>the Spartan(tm) marking right below the Xilinx(tm) logo. =A0That > >>was one of the things that made me curious, although I don't > >>know why a counterfeiter would miss something that obvious. > > > My XCS10XL have 5 lines: Xilinx-logo, type, package and date code, lot c= ode and > > speed grade. No "Spartan". Maybe it's not on the TQFP/VQFP100 package be= cause > > auf the limited area... > > OK, well that's good to know. =A0But, the chips in question are > TQ144, I have some just 20 weeks newer, and they have the > Spartan logo on them, the label otherwise looks very similar. > Anyway, I sent photos to Xilinx, and am waiting to hear if they > can tell anything from a picture. =A0I'm on pins and needles not > knowing if I have some kind of process-related problem or a > batch of bad chips. =A0I have shipped half of this batch already, > so if the chips are failing slowly, they are going to be seeing > problems too. =A0Not a good feeling! > > Jon- Hide quoted text - > > - Show quoted text - Hello all, I am a Quality manager at Xilinx, and I have asked to provide specific guidance on the question of counterfieting. I would like to start by saying that the ONLY way to protect yourself is to purchase your devices from an authorized Xilinx distributor. A list can be found at this link. http://www.xilinx.com/company/sales/ww_disti.htm If you a buying outside of this channel you are taking on a fair amount of risk. Over the past 1.5 years Xilinx along with the Dept of Homeland Security have become aware of an escalatng issue out of SE Asia, where Xilinx component are being marked up for sale into grey market channels. We currently are looking into how to limit this activity. The real simple rule is that if you go to they brokers or independent distributors you have absolutely no way of validating devices. Even if that entity provides what may appear to be legitimate documentation, the supply chain is broken and the care, custody, and control of the material is suspect. In many cases Xilinx will not be able to assist you in determining if those suspect devices are legitimate or usable. We must sustain our valid authorized sale and distribution channels and in nearly all cases will not be able to assist or lend resources to unvalidated supply chains. That is not to say that we do not want to support our customer base, but this ever escalating pollution of the supply chain with grey market materials will ultimately strain available resources that would historically assist in these cases. Please help eliminate this issue by only purchasing though authorized Xilinx sources, and you will avoid, completely, these types of issue. Best regardsArticle: 130823
Hello all, I am a Quality manager at Xilinx, and I have asked to provide specific guidance on the question of counterfieting. I would like to start by saying that the ONLY way to protect yourself is to purchase your devices from an authorized Xilinx distributor. A list can be found at this link. http://www.xilinx.com/company/sales/ww_disti.htm If you a buying outside of this channel you are taking on a fair amount of risk. Over the past 1.5 years Xilinx along with the Dept of Homeland Security have become aware of an escalatng issue out of SE Asia, where Xilinx component are being marked up for sale into grey market channels. We currently are looking into how to limit this activity. The real simple rule is that if you go to they brokers or independent distributors you have absolutely no way of validating devices. Even if that entity provides what may appear to be legitimate documentation, the supply chain is broken and the care, custody, and control of the material is suspect. In many cases Xilinx will not be able to assist you in determining if those suspect devices are legitimate or usable. We must sustain our valid authorized sale and distribution channels and in nearly all cases will not be able to assist or lend resources to unvalidated supply chains. That is not to say that we do not want to support our customer base, but this ever escalating pollution of the supply chain with grey market materials will ultimately strain available resources that would historically assist in these cases. Please help eliminate this issue by only purchasing though authorized Xilinx sources, and you will avoid, completely, these types of issue. Best regardsArticle: 130824
On Apr 2, 4:04 pm, Duane Clark <u...@domaininvalid.com> wrote: > ni wrote: > > > My confusion is if I write this code to infer RAMS then once I do the > > synthesis and then go to place and route then would it still be > > considered as a BRAM? I thought Xilinx brams(generated through CORE > > Generator ) would be much more optimised then inferred RAMS in > > synplify since ultimately we would be using xilinx PAR. > > Using coregen definitely does not result in optimization during PAR (or > MAP for that matter). When Synplify (or any synthesis tool) creates the > edif file that will be used by the Xilinx tools, it puts primitives in > there including BRAMs if they are correctly inferred in your code. It is > useful to check the log file of the synthesis tool to verify that the > expected number of BRAMs were inferred. If not, that might point to > something you did wrong when inferring them. Thanks, I will try that and see.
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