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>and as new feature added to EDK: >*Usability improvements as well as Simplified Installation and >Registration process >unfortunatly that new feature (added in 10.1) COMPLETLY prevents the >download of any of the 10.1 tools!! This seems the normal way of business these days. Where "improvement" means broken etc.. :) >so we can download xilinx programming tools only - as simple one file >download of 916 MEGA BYTE only :) You might try something like this: wget -O- http://host/file.. | tar -xzvpf -Article: 130476
On Mar 25, 11:09 am, mh <moazzamhuss...@gmail.com> wrote: > > > i) We want to make SOC designs used for image processing, path > > > planning, motion control for our robots which need both processor and > > > dedicated hardware. Since this type of design has not been used so far > > > here, we are actually trying to introduce it and hence finding it > > > difficult to select the best way. > > > Once started it will continue with newer students every year. > > I am afraid that you may have to design a custom board for this > application, I myself > thought that I could try a Xilinx Virtex-4 (FX) device for such a > research activity but had > to design a custom board employing TI-tms320c64x processor with Xilinx > Virtex-4 device > to meet computational demands of parallel image processing > applications. May be you find > some off the shelf board with such horse power of computational > capability. > Right now we are not in a position to design a custom board. Since using an embedded platform with FPGA and softcore like microblaze, itself is challenging for us since we have not done it so far and we don't have any professor who have experience in it. So we would like to buy one standard board that too under $400, budget is again important. > > > ii) We want to complete a project with a working robot that could > > > track some colored object or some specific shaped object. Finding such > > > object in a room. > > Even the basic 2-D template matching algorithms are computationally > demanding, and the > algorithms for ATR (automatic target recognition) are far more > complex. > > > Looking at the Spartan-3A board it seems it could be better. I'm still > > not clear about if we can use some softcore processor in this board's > > FPGA. What about extra cost for the license (if required) to use, say, > > microblaze. > > Putting it in simpler way, we want to have an embedded platform where > > we could use FPGA for designing hardwares like pwm generators, > > quadrature phase decoders, display controllers, parallel algorithms > > for image processing, and then we could use the processor present in > > it to do planning, some AI and high level tasks. > > I recommend you to do more research and get a clear idea of algorithms > that > you want to implement. Try to calculate the number of multiplications, > additions, > square roots etc that may be needed per second. Only then you will > have a good > number of required computations and you can identify a target device. > May be > some FPGA from Virtex-4/5 meet your demands. > > Best of luck !!! > > /MH Right now we want to be able to use FPGA's with processors in robot and its capability can be varied as their is not fixed goal on the level of complexity or the function of the robot. We want to implement the concept of SOC design in robotics and then let more research be in this field in coming years by our juniors in our club. So the complexity can be reduced but again we are actually just learning image processing so to know much more about it would itself take time. By the time we'd have good knowledge in algorithms, we would also like to be experienced with using SOC design in these kind of boards so that we could really start designing the system.Article: 130477
Hi, I am working on DDR2 memory controller for Dual-rank SODIMM targeting virtex5. I wonder why Xilinx specifies that its MIG2.0 doesn't support DUAL-RANK DIMM? Thank you. AdamArticle: 130478
On 24 Mrz., 22:32, alud...@altera.com wrote: > In short, these are early days for parallel EDA and we're not at 4x > speedups yet, but we're busy laying the groundwork for the many-core > future to make sure we don't get left behind. Don't get me wrong: I believe it's a good thing to work on that. I am just surprise that you are doing this development in you production toolchain. This seems to be a lot of risk and effort for a minor improvement. I would probably wait until I could present a bigger improvement. But that is your decision. As a sidenote: At least in designs with an utilization below 70% or so it should be relatively easy to partition the design and then run the whole toolfllow on the partitions. That also is something that probably can be done on the makefile level using the toolflows for dynamic reconfiguration. Might be a nice master thesis. Kolja SulimmaArticle: 130479
On 25 Mrz., 11:02, Uwe Bonnes <b...@hertz.ikp.physik.tu-darmstadt.de> wrote: > Roling out a multi-hundred or even Gigabyte distribution is some heavy load > for any server farm. But if you know that in advance, there are two simple solutions: - use torrents (yes, those are not only for illegal file sharing) or - buy on demand bandwidth from Amazon or other providers. Kolja SulimmaArticle: 130480
Hi, I tried to use the EDK 9.2 MicroBlaze tutorial in Virtex-4 but at the end of the Base System Builder Wizard I found some problems. I opened the project with Xilinx ISE, imported the new peripheral (named custom_ip), followed all points and created a new directory called custom_ip_v1_00_a in the pcores directory. When the guide says: "Select the system.xmp source file and double click on the View HDL Instantiation Template. Once the process has completed the editor window will contain the instantiation template called system.vhl" the process doesn't synthetizes. why? thank youArticle: 130481
On 25 Mrz., 14:40, Kolja Sulimma <ksuli...@googlemail.com> wrote: > On 25 Mrz., 11:02, Uwe Bonnes <b...@hertz.ikp.physik.tu-darmstadt.de> > wrote: > > > Roling out a multi-hundred or even Gigabyte distribution is some heavy load > > for any server farm. > > But if you know that in advance, there are two simple solutions: > - use torrents (yes, those are not only for illegal file sharing) > or > - buy on demand bandwidth from Amazon or other providers. > > Kolja Sulimma no that aint the problem I think Xilinx has bandwidth as much as needed they just have web application problems that prevent registrations, etc... download speeds are >=300 Kbyte seconds AnttiArticle: 130482
sky465nm@trline4.org wrote: >>> it only 6.7 GB download :) >>> >>> Antti > >> Why don't they use bit torrent? It would save them a packet (hoho) in >> bandwidth costs... > I would not imagine that bit torrent would be so popular among professional users - most companies' networks will (should!) block bit torrent traffic. It would help for some users (especially if there were a number of slave servers contributing to the swarm), but don't believe bit torrent (or any other p2p sharing) is popular in corporate networks. > That and slave servers around the world. Like other large internet projects > handle this kind of issue. Ie why have 100 ppl download over a slow pipe when > you can download it fast from a local server. > > A response from xilinx on this matter would be nice. >Article: 130483
Hi Antti, everyone, Antti wrote: > no that aint the problem I think Xilinx has bandwidth as much as > needed > they just have web application problems that prevent registrations, > > download speeds are >=300 Kbyte seconds In my opinion, Xilinx did quite a nice job: registration and everything went very smoothly and I just downloaded the new WebPack in under an hour (apx. 5.7Mb/s). The download menu offers options to use a webinstall or download manager, but with some perseverance you can still download the file using plain old wget (the machine that runs my webbrowser is not the machine where I wanted to download this 2.3GB tarball) - very nice to have that option available as well. Regards, Paul Boven.Article: 130484
Hi Antti, I encountered similar problems last night (PM Pacific Time, 24-MAR-2008) but was far more successfull this morning (AM Pacific Time, 25-MAR-2008). I agree, last night was very frustrating as the site just fails; no mention of heavy traffic. Steve Knapp Prevailing Technology, Inc. "Antti" <Antti.Lukats@googlemail.com> wrote in message news:3b7035a6-61cd-4ea2-848e-4885ed74bf79@13g2000hsb.googlegroups.com... >I can not imagine that the server overload is such a real problem that > Xilinx hasnt been able to solve it during the many years of repeated > webserver problems. > > Getting the company website and downloads working reliable isnt magic. > Its way less complicated the making FPGA's > > Sure probably there are just too many download requests of 10.1 but, > but still it should be possible to get the servers managed > > > ======== > Error > > We cannot fullfill your request due to technical difficulties. Please > try again later. > > Please do NOT click the back button. Please try again later, and email > webmaster@xilinx.com if you receive this error repeatedly. > > ========Article: 130485
Hi! Is there anyone that has made a design for Actels MP7 Arm core on Fusion FPGA? I'am looking for an example project to check my design as it is not functional. I'm just using internal RAM, so it is a quite simple design. Cheers DanielArticle: 130486
On 25 Mrz., 16:36, "Steve Knapp" <steveD.O.TknappA.Tprevailing- technologyD.O.Tcom> wrote: > Hi Antti, > > I encountered similar problems last night (PM Pacific Time, 24-MAR-2008) but > was far more successfull this morning (AM Pacific Time, 25-MAR-2008). > > I agree, last night was very frustrating as the site just fails; no mention > of heavy traffic. > > Steve Knapp > Prevailing Technology, Inc. > > "Antti" <Antti.Luk...@googlemail.com> wrote in message > > news:3b7035a6-61cd-4ea2-848e-4885ed74bf79@13g2000hsb.googlegroups.com... > > >I can not imagine that the server overload is such a real problem that > > Xilinx hasnt been able to solve it during the many years of repeated > > webserver problems. > > > Getting the company website and downloads working reliable isnt magic. > > Its way less complicated the making FPGA's > > > Sure probably there are just too many download requests of 10.1 but, > > but still it should be possible to get the servers managed > > > ======== > > Error > > > We cannot fullfill your request due to technical difficulties. Please > > try again later. > > > Please do NOT click the back button. Please try again later, and email > > webmas...@xilinx.com if you receive this error repeatedly. > > > ======== Hi Steve, it seems that I(we) fetched a bad time for our first attempts... only a few hours later all worked fine! Antti PS you have switched to dangerous company? ;) or maybe i dont know the exact meaning of "prevailing.."Article: 130487
On Mar 24, 8:29 pm, "KJ" <kkjenni...@sbcglobal.net> wrote: > "ni" <nbg2...@gmail.com> wrote in message > > news:1a0e6c96-03f8-4456-bd3d-7a5f1f60fde4@b1g2000hsg.googlegroups.com... > > >I wanted to perform a byte shifting of a 24bit vector . the resultant > > vector is a 48 bit vector . the following is the functinality needed > > > signal BV : std_logic_vector(23 downto 0); > > signal BYTE_SEL : std_logic_Vector(1 downto 0); > > signal BVOUT : std_logic_Vector(47 downto 0); > > > method 1 > > BVOUT <= x"000000" & BV when BYTE_SEL = "00" else > > x"0000" & BV & x"00" when BYTE_SEL ="01" else > > x"00" & BV & x"0000" when BYTE_SEL ="10" else > > BV & x"000000"; > > This will likely get implemented something like a 3 bit 'and for each bit > (i.e. bit 0 out = bit 0 in when byte_sel=00) , so basically 1 logic cell per > bit...not too bad. > > > > > I would like to know if the above method 1 of the behavioural > > statement is a good way of programming when I am implementing on the > > FPGa > > Yes it is. > > > or should I implement it using a ROM where I store a multiplier > > constant and use the byte_sel as an address to select it and then > > multiply with the pipelined BV to generate the output. > > Now you're obscuring your real design intent in the hopes of improving > either logic resource or performance (not sure which). Unless your > targetted part has 32 bit hardware multipliers, the resulting implementation > may consist of two smaller multipliers plus some logic to combine the > outputs into the final result or some logic on the front end into the > multiplier, a single multiplier and then some additional logic on the output > side. Possibly a better approach would be to break it down into two > independent 16 bit multipliers where one of the multipliers would end up > multiplying by 0, the other by either 1 or 256. > > In any case, I'm guessing that any solution along those lines would probably > have a hard time being better than the single level of logic per bit > required for method 1. > > > Or is there any other better way to implement it other than the above > > two methods. > > Possibly. But the best way to explore implementation ideas is with > synthesis software which allows you to implement the idea and get pretty > immediate feedback via their RTL and technology map viewers as well as logic > resource and timing performance so you can get a feel for which methods are > 'better' than others for how you intend to use it. > > One important thing you've done is tried to see the problem from different > perspectives. Method 1 is a view that is basically a 4>1 multiplexer view > whereas method 2 views the problem from an arithmetic view. It got a bit > convoluted by thinking of using a ROM lookup table when the multipliers are > a fairly trivial function of the input byte_sel. > > If you have ISE, Quartus, Synplify, etc. try out your ideas and you'll get > quicker turn around then the newsgroup approach. > > Kevin Jennings Thanks Kevin. -DArticle: 130488
David Brown <david@westcontrol.removethisbit.com> writes: > I would not imagine that bit torrent would be so popular among > professional users - most companies' networks will (should!) block bit > torrent traffic. Red Hat relies heavily on Bittorrent to distribute copies of the Fedora stuff. So, don't just assume "bittorrent == bad".Article: 130489
On Mar 25, 9:02=A0am, Antti <Antti.Luk...@googlemail.com> wrote: > On 25 Mrz., 16:36, "Steve Knapp" <steveD.O.TknappA.Tprevailing- > > > > technologyD.O.Tcom> wrote: > > Hi Antti, > > > I encountered similar problems last night (PM Pacific Time, 24-MAR-2008)= but > > was far more successfull this morning (AM Pacific Time, 25-MAR-2008). > > > I agree, last night was very frustrating as the site just fails; no ment= ion > > of heavy traffic. > > > Steve Knapp > > Prevailing Technology, Inc. > > > "Antti" <Antti.Luk...@googlemail.com> wrote in message > > >news:3b7035a6-61cd-4ea2-848e-4885ed74bf79@13g2000hsb.googlegroups.com... > > > >I can not imagine that the server overload is such a real problem that > > > Xilinx hasnt been able to solve it during the many years of repeated > > > webserver problems. > > > > Getting the company website and downloads working reliable isnt magic.= > > > Its way less complicated the making FPGA's > > > > Sure probably there are just too many download requests of 10.1 but, > > > but still it should be possible to get the servers managed > > > > =3D=3D=3D=3D=3D=3D=3D=3D > > > Error > > > > We cannot fullfill your request due to technical difficulties. Please > > > try again later. > > > > Please do NOT click the back button. Please try again later, and email= > > > webmas...@xilinx.com if you receive this error repeatedly. > > > > =3D=3D=3D=3D=3D=3D=3D=3D > > Hi Steve, > > it seems that I(we) fetched a bad time for our first attempts... > only a few hours later all worked fine! > > Antti > PS you have switched to dangerous company? ;) > or maybe i dont know the exact meaning of "prevailing.." Many years ago, when we packed our little kids into the station wagon for the 45 min trip to the beach, they would become impatient after a few miles and whine: "Aren't we there yet?". The whining here reminds me of those trips. PS: We always made it to the beach, the whining seems to be what parents are supposed to endure... Peter AlfkeArticle: 130490
On 25 Mrz., 18:14, Peter Alfke <pe...@xilinx.com> wrote: > On Mar 25, 9:02 am, Antti <Antti.Luk...@googlemail.com> wrote: > > > > > On 25 Mrz., 16:36, "Steve Knapp" <steveD.O.TknappA.Tprevailing- > > > technologyD.O.Tcom> wrote: > > > Hi Antti, > > > > I encountered similar problems last night (PM Pacific Time, 24-MAR-2008) but > > > was far more successfull this morning (AM Pacific Time, 25-MAR-2008). > > > > I agree, last night was very frustrating as the site just fails; no mention > > > of heavy traffic. > > > > Steve Knapp > > > Prevailing Technology, Inc. > > > > "Antti" <Antti.Luk...@googlemail.com> wrote in message > > > >news:3b7035a6-61cd-4ea2-848e-4885ed74bf79@13g2000hsb.googlegroups.com... > > > > >I can not imagine that the server overload is such a real problem that > > > > Xilinx hasnt been able to solve it during the many years of repeated > > > > webserver problems. > > > > > Getting the company website and downloads working reliable isnt magic. > > > > Its way less complicated the making FPGA's > > > > > Sure probably there are just too many download requests of 10.1 but, > > > > but still it should be possible to get the servers managed > > > > > ======== > > > > Error > > > > > We cannot fullfill your request due to technical difficulties. Please > > > > try again later. > > > > > Please do NOT click the back button. Please try again later, and email > > > > webmas...@xilinx.com if you receive this error repeatedly. > > > > > ======== > > > Hi Steve, > > > it seems that I(we) fetched a bad time for our first attempts... > > only a few hours later all worked fine! > > > Antti > > PS you have switched to dangerous company? ;) > > or maybe i dont know the exact meaning of "prevailing.." > > Many years ago, when we packed our little kids into the station wagon > for the 45 min trip to the beach, they would become impatient after a > few miles and whine: "Aren't we there yet?". > The whining here reminds me of those trips. > PS: We always made it to the beach, the whining seems to be what > parents are supposed to endure... > Peter Alfke eh kids kids (inside of men) they are all impatient :) the problem persisted only a few hours, so it really wasnt a big wait this time until it got fixed. AnttiArticle: 130491
I'm a bit new to FPGA configuration and I couldn't find any messages
that addressed my particular problem (although I'm sure this is a
common issue). I am using the Xilinx ISE Webpack to configure a
Spartan 3 FPGA. I am multiplexing a 16-bit data bus and routing it to
differend devices. I want to control the signal-to-signal skew of the
data bus.
Here is my code:
****************************************************************************************************
// Data muxes
always @*
case (1'b1)
(MPEGhostActive) : begin // MPEG host port
(addr decode of fcs1)
fd_mux_out = mpeg_hd;
end
(fcs2) : begin //IDE port
(fcs2)
fd_mux_out = ide_fd;
end
default : begin // fpga
fd_mux_out = fd;
end
endcase
assign fd = fd_oe ? fd_mux_out : 16'bz; // cpu read
*****************************************************************************************************
*These are data buses and thus bi-directional - code not shown.
I tried to control the timing in the ucf by using FROM and TO in the
following manner:
******************************************************************************************************
INST "ide_fd<*>" TNM = "ide_data_lines";
INST "fd<*>" TNM = "cpu_data_lines";
INST "mpeg_hd<*>" TNM = "mpeg_data_lines";
TIMESPEC "TS_FD2IDE" = FROM "cpu_data_lines" TO "ide_data_lines"
10;
TIMESPEC "TS_IDE2FD" = FROM "ide_data_lines" TO "cpu_data_lines"
10;
TIMESPEC "TS_FD2MPEG" = FROM "cpu_data_lines" TO "mpeg_data_lines"
10;
TIMESPEC "TS_MPEG2FD" = FROM "mpeg_data_lines" TO "cpu_data_lines"
10;
*****************************************************************************************************
Unfortunately the timing does not change wether I use the TIMESPEC
constraint or not; I just get a warning that "timing was not met" if I
use the constraint. Is there a constraint that will force the
implementation to meet timing? Signal to signal skew is more important
to me than propogation delay but these signals are asynchronous and I
could not find a constraint that meets that need - all the skew
constraints seem to involve a clock. The way I would implement this in
hardware would be to make all the signal traces the same length; is
there a similar constraint I can use in FPGA design?
Thanks,
Derek
Article: 130492
derived from the ISE 10.1 webpack infos
V5FXT device-package options
VFX70T FF665 FF1136
VFX100T FF1136 FF176
VFX130T FF176
VFX200T FF176
it looks like dual core devices are not offered
NEW info for V5 in generic, the OTP fuse information is BACK :)
it was in some initial documents, then was removed, now its is back,
there are 2 pins for the FUSE
VFS
R_FUSE
and some JTAG commands
"FUSE_UPDATE (11111111110000)," &
"FUSE_KEY (11111111110001)," &
"FUSE_ID (11111111110010)," &
"FUSE_USER (11111111110011)," &
"FUSE_CNTL (11111111110100)," &
not sure if complete information about the fuse is available or not
yet
Antti
Article: 130493Peter Alfke wrote: > On Mar 24, 11:58 am, Jon Elson <el...@wustl.edu> wrote: > >>sky46...@trline4.org wrote: >> >>>Jon Elson <el...@pico-systems.com> wrote: >> >>>>I got a batch of "Xilinx" Spartan XCS30 FPGAs from a Chinese >>>>seller, and am having problems with random failures at first >>>>power up. Sometimes it is a stuck I/O pin, sometimes a failure >>>>to configure. I first thought maybe we had an ESD problem, but >>>>I'm now thinking these may be counterfeit. They have white ink >>>>printed labels on the front, whereas other Xilinx chips have >>>>laser-etched labels. Also, these Spartan chips don't have the >>>>Spartan logo just below the Xilinx logo, like my other Xilinx >>>>chips. Anyone have any comments on this? >>> >>>Photo.. ? >> >>OK, where should I put the photos? >> >>Jon > > > You can send it to me,and I will pass it on. OK, I will do that. I'll have to see how "macro" my camera will go. Do you have any comment on some date code 1999 Spartans that are printed with white ink (not laser marked) and have the Xilinx logo but no Spartan logo under it? These are XCS30-3TQ144C parts. I just got them late last year and am having what looks like a 50%+ failure rate. In the past, when I got an occasional ESD damage event, I usually observed the chip running EXTREMELY hot or totally shorting out the power supply. These chips all run cool, but many have what seems to be a stuck output pin or they don't configure at all, and the pins that should be doing certain things when the PROG/ line is cycled don't do anything. I've used several hundred of this particular Xilinx part in previous boards and never ran into any problems like this. That combined with the different markings make me think they could be counterfeit, maybe poor quality wafers that were supposed to be recycled, or something like that. JonArticle: 130494
Hi Kolja, > Don't get me wrong: I believe it's a good thing to work on that. > I am just surprise that you are doing this development in you > production toolchain. > This seems to be a lot of risk and effort for a minor improvement. I > would probably > wait until I could present a bigger improvement. But that is your > decision. Lets say (hypothetically) that there are 100 places that we have to parallelize to get a 2X speed-up. I think it is far less risky to dribble out the improvements on 10 algorithms per release, climbing from 5% to 10% to 15% to 20% improvement, then it is to develop all 100, test them locally, then unleash all the changes on the world at once. Plus this way users get that 20% benefit sooner rather than later. > As a sidenote: At least in designs with an utilization below 70% or so > it should > be relatively easy to partition the design and then run the whole > toolfllow on the partitions. > That also is something that probably can be done on the makefile level > using the toolflows for > dynamic reconfiguration. Might be a nice master thesis. If the user is willing to partition their design, then they can already achieve some speed-up with Quartus by using the Quartus Incremental Compile capabilities in a bottom-up fashion. Each partition can be compiled with a separate execution of the Quartus flow (which can be parallelized), and the resulting partitions can then be combined. Another benefit is that only those partitions that are impacted by design modifications need to be recompiled. As for automatic partitioning: Our users tend to push design performance. If we pre-decide how to break up a design into completely separable partitions and then separately synthesize and place-and-route those partitions, yes, you can get a compile time speed-up. But how much performance is lost? Could you have got an equal speed-up by just dialing down the effort level in the flat, serial algorithm? Also, what do you do at the partition boundaries? Do you need to do some routing and timing analysis at the top level after synthesis/placement/routing on the sub-sections? If the partitions do not line up perfectly with clock domains or with keepers, then you have a slack dependency on signals that cross partition boundaries -- how do you solve that? I think that this is a good area of research. But I would not say it is "easy". Regards, Paul Leventis Altera Corp.Article: 130495
soxmax wrote: > I'm a bit new to FPGA configuration and I couldn't find any messages > that addressed my particular problem (although I'm sure this is a > common issue). I am using the Xilinx ISE Webpack to configure a > Spartan 3 FPGA. I am multiplexing a 16-bit data bus and routing it to > differend devices. I want to control the signal-to-signal skew of the > data bus. > > Here is my code: > **************************************************************************************************** > // Data muxes > always @* > case (1'b1) > (MPEGhostActive) : begin // MPEG host port > (addr decode of fcs1) > fd_mux_out = mpeg_hd; > end > (fcs2) : begin //IDE port > (fcs2) > fd_mux_out = ide_fd; > end > default : begin // fpga > fd_mux_out = fd; > end > endcase > > assign fd = fd_oe ? fd_mux_out : 16'bz; // cpu read > ***************************************************************************************************** > *These are data buses and thus bi-directional - code not shown. > > I tried to control the timing in the ucf by using FROM and TO in the > following manner: > ****************************************************************************************************** > INST "ide_fd<*>" TNM = "ide_data_lines"; > INST "fd<*>" TNM = "cpu_data_lines"; > INST "mpeg_hd<*>" TNM = "mpeg_data_lines"; > TIMESPEC "TS_FD2IDE" = FROM "cpu_data_lines" TO "ide_data_lines" > 10; > TIMESPEC "TS_IDE2FD" = FROM "ide_data_lines" TO "cpu_data_lines" > 10; > TIMESPEC "TS_FD2MPEG" = FROM "cpu_data_lines" TO "mpeg_data_lines" > 10; > TIMESPEC "TS_MPEG2FD" = FROM "mpeg_data_lines" TO "cpu_data_lines" > 10; > ***************************************************************************************************** > > Unfortunately the timing does not change wether I use the TIMESPEC > constraint or not; I just get a warning that "timing was not met" if I > use the constraint. Is there a constraint that will force the > implementation to meet timing? Signal to signal skew is more important > to me than propogation delay but these signals are asynchronous and I > could not find a constraint that meets that need - all the skew > constraints seem to involve a clock. The way I would implement this in > hardware would be to make all the signal traces the same length; is > there a similar constraint I can use in FPGA design? > > Thanks, > Derek > > I'm not a verilog person, but it looks like you're implementing a combinatorial mux on the data output. AFAIK, you cannot get closure using the timing constraints if the FPGA output is driven by combinatorial logic instead of registers. Using output registers after the mux allows the output registers to be located in the IOB (I/O Block) at the pin. With a low-skew clock driving the IOB FFs, the skew will be quite low - the sum of the global clock skew to the IOB FFs + the variation in tCKL of the IOB FFs. Without the register, the complete combinatorial delay for all 16 signals needs to be considered, which is more than the tool can do. The tool has to consider the min/max delays of all of the elements - CLBs and routing - in the path. UrbArticle: 130496
You are attempting to do asynchronous design in a synchronous design flow, By that, I mean, you may bus signals together, and you may register them by having them arrive at flip flops, clocked from the global clock resource. Then timing constraints will be applied, and all bussed signals will be routed such that they arrive in time to be registered in the flip flops at the rising lock edge. You do not have to worry about how the routing is done (the tools take care of that for you). Having signals leave a register, and arrive at another register (after passing through logic, or arithmetic operations) is the basis of synchronous design. Without registers and clocks, what you want to do is unsupported (asynchronous design in a part designed for synchronous implementation). http://en.wikipedia.org/wiki/Sequential_logic http://en.wikipedia.org/wiki/Synchronous_circuit as opposed to: http://en.wikipedia.org/wiki/Asynchronous_circuit (which is unsupported by FPGA design flows) AustinArticle: 130497
On Mar 25, 1:14=A0pm, Jon Elson <el...@wustl.edu> wrote: > Peter Alfke wrote: > > On Mar 24, 11:58 am, Jon Elson <el...@wustl.edu> wrote: > > >>sky46...@trline4.org wrote: > > >>>Jon Elson <el...@pico-systems.com> wrote: > > >>>>I got a batch of "Xilinx" Spartan XCS30 FPGAs from a Chinese > >>>>seller, and am having problems with random failures at first > >>>>power up. =A0Sometimes it is a stuck I/O pin, sometimes a failure > >>>>to configure. =A0I first thought maybe we had an ESD problem, but > >>>>I'm now thinking these may be counterfeit. =A0They have white ink > >>>>printed labels on the front, whereas other Xilinx chips have > >>>>laser-etched labels. =A0Also, these Spartan chips don't have the > >>>>Spartan logo just below the Xilinx logo, like my other Xilinx > >>>>chips. =A0Anyone have any comments on this? > > >>>Photo.. ? > > >>OK, where should I put the photos? > > >>Jon > > > You can send it to me,and I will pass it on. > > OK, I will do that. =A0I'll have to see how "macro" my camera will go. > Do you have any comment on some date code 1999 > Spartans that are printed with white ink (not laser marked) and > have the Xilinx logo but no Spartan logo under it? =A0These are > XCS30-3TQ144C parts. =A0I just got them late last year and am having what > looks like a 50%+ failure rate. =A0In the past, when I got an occasional > ESD damage event, I usually observed the chip running EXTREMELY hot or > totally shorting out the power supply. =A0These chips all run cool, but > many have what seems to be a stuck output pin or they don't configure at > all, and the pins that should be doing certain things when the PROG/ > line is cycled don't do anything. =A0I've used several hundred of this > particular Xilinx part in previous boards and never ran into any > problems like this. =A0That combined with the different markings make me > think they could be counterfeit, maybe poor quality wafers that were > supposed to be recycled, or something like that. > > Jon Jon, I really have no comments. I do not work in the Spartan group or even division, let alone building. I just promised to send your picture and comments to the people in the know. I hope the parts are fake, for I cannot imagine such a sudden surge in failure rate from good devices. Peter Alfke, who works in the Advanced Products (Virtex) division.Article: 130498
"Peter Alfke" <peter@xilinx.com> wrote in message news:48ceae85-5695-477e-8ed4-ea446dca38fe@s13g2000prd.googlegroups.com... On Mar 25, 1:14 pm, Jon Elson <el...@wustl.edu> wrote: > Peter Alfke wrote: > > On Mar 24, 11:58 am, Jon Elson <el...@wustl.edu> wrote: > > >>sky46...@trline4.org wrote: > > >>>Jon Elson <el...@pico-systems.com> wrote: > > >>>>I got a batch of "Xilinx" Spartan XCS30 FPGAs from a Chinese > >>>>seller, and am having problems with random failures at first > >>>>power up. Sometimes it is a stuck I/O pin, sometimes a failure > >>>>to configure. I first thought maybe we had an ESD problem, but > >>>>I'm now thinking these may be counterfeit. They have white ink > >>>>printed labels on the front, whereas other Xilinx chips have > >>>>laser-etched labels. Also, these Spartan chips don't have the > >>>>Spartan logo just below the Xilinx logo, like my other Xilinx > >>>>chips. Anyone have any comments on this? > > >>>Photo.. ? > > >>OK, where should I put the photos? > > >>Jon > > > You can send it to me,and I will pass it on. > > OK, I will do that. I'll have to see how "macro" my camera will go. > Do you have any comment on some date code 1999 > Spartans that are printed with white ink (not laser marked) and > have the Xilinx logo but no Spartan logo under it? These are > XCS30-3TQ144C parts. I just got them late last year and am having what > looks like a 50%+ failure rate. In the past, when I got an occasional > ESD damage event, I usually observed the chip running EXTREMELY hot or > totally shorting out the power supply. These chips all run cool, but > many have what seems to be a stuck output pin or they don't configure at > all, and the pins that should be doing certain things when the PROG/ > line is cycled don't do anything. I've used several hundred of this > particular Xilinx part in previous boards and never ran into any > problems like this. That combined with the different markings make me > think they could be counterfeit, maybe poor quality wafers that were > supposed to be recycled, or something like that. > > Jon Jon, I really have no comments. I do not work in the Spartan group or even division, let alone building. I just promised to send your picture and comments to the people in the know. I hope the parts are fake, for I cannot imagine such a sudden surge in failure rate from good devices. Peter Alfke, who works in the Advanced Products (Virtex) division. Peter, Can you tell us if you've ever seen any counterfeit Xilinx parts? If yes, were they authentic die that had been repackaged or relabled, or were the die themselves fakes? Thanks, BobArticle: 130499
Hi, I would like to get a fanout report of all utilized LABs in a design in QuartusII. The fitter section of compilation report in QuartusII just only reports fanout of global signal and non-global signal with high-fanout. Could everyone please help me on this? Thank you Roto Le
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