Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
This is a weird problem. I have a MPMC2 based PPC system with Flash memory attached via opb_emc. The design works fine including the flash memory, which is used for loading FPGA itself amongst other things. However I can't read its content from gdb. All I see is zeros... I am using EDK8.2 for this project and I believe I used to be able to read the flash just fine. It is possible though that when I did it last time I had EDK8.1... Does anyone have an idea of what I can be doing wrong here? Thanks, /MikhailArticle: 130626
Un bel giorno Antti digiṭ: > I can not imagine that the server overload is such a real problem that > Xilinx hasnt been able to solve it during the many years of repeated > webserver problems. Yes, and now they are trying to fix it with some stupid Java applets (probably they are hosting the file somewhere else but don't want the user to see the direct link). I don't understand why the big companies don't distribute their software with BitTorrent. It would be so nice, fast and easy for everyone. It would especially make sense for Xilinx, that offers a 2 GB software for free, and poses as the friendly neighborhood multinational. ,-) -- emboliaschizoide.splinder.comArticle: 130627
mk wrote: > On Fri, 28 Mar 2008 11:14:23 -0700 (PDT), FPGA > <FPGA.unknown@gmail.com> wrote: > >> what does the following code do >> output <= input[x*(y)-1 -: y]; > > That's called an indexed part select. The first expression signifies > base and the second expression signifies width. It the sign is + it's > an ascending select if it's negative it's a descending select. Your > example is equivalent to input[x*(y)-1: x*(y)-y] ie you need to > subtract (y-1) from the base to get the lower index. I think your equivalent should be: input[x*(y)-1: x*(y)-y+1] If I remember correctly, the width has to be a constant. In this case that would mean y could be a parameter, but not an integer or register. -KevinArticle: 130628
On Mar 28, 10:20 am, moja...@mojaveg.IWVISP.com (Everett M. Greene) wrote: > David Brown <da...@westcontrol.removethisbit.com> writes: > > >> The key is, > > >> "Can you write code to do +,~, |,>>,conditional branch on > > >> z or carry" > > > > You need XOR for add/subtract so it can be one of the > > > operations at little extra cost. Some sort of CALL > > > and RETURN is needed for the processor to be useful. > > > AND is needed as well. > > > (a & b) == ~(~a | ~b) > > (a ^ b) == (a | b) & ~(a & b) > > > Thus you don't need AND or XOR. Similarly, you subtraction. > > But you haven't produced addition/subtraction yet. The first > term of adders/subtractors is a ^ b. If you gate that output > to rest of the world, you have XOR with no further fuss. > NOT is available via a ^ 1s. You can produce any arithmetical or logical operation out of just NAND gates (or just NOR gates as was actually done in some ECL supercomputer implementations), and the same can be done in software, if efficiency is of no importance. However one big difference is that arithmetic operations imply carry (or borrow) logic, and word-wide logic implies the lack of inter-bit interference (carry), which are both costly to synthesize from the other. So a MISC that operates on words should provide at least one logic operation and one arithmetic operation. Right shift and compare to constant (say zero) are also costly to synthesize, so could also be provided for efficiency and completeness. IMHO. YMMV. -- rhn A.T nicholson d.0.t C-o-MArticle: 130629
I'm trying to rebuild an old project I did on ISE8.2i. I reinstalled 8.2i on my PC. I also have 9.2i installed on the same PC. I don't know if they would conflict or not? My environment variable XILINX is point to ISE8.2. I'm using CoreGen to create quite a few ROMs, RAMs and FIFOs. CoreGen has a history of breaking things. So, I did a cleanup project files to begin with. Everything else is unchanged. When I rebuild the project it is 20% larger than the original project was. My project will no longer fit in the part. Where is all of the extra bloat coming from? Thanks for your help, DaleArticle: 130630
Dale wrote:
> I'm trying to rebuild an old project I did on ISE8.2i. I reinstalled
> 8.2i on my PC. I also have 9.2i installed on the same PC. I don't
> know if they would conflict or not? My environment variable XILINX is
> point to ISE8.2. I'm using CoreGen to create quite a few ROMs, RAMs
> and FIFOs. CoreGen has a history of breaking things.
>
> So, I did a cleanup project files to begin with. Everything else is
> unchanged. When I rebuild the project it is 20% larger than the
> original project was. My project will no longer fit in the part.
> Where is all of the extra bloat coming from?
Something is different.
Maybe the project file cleanup did it.
I would look on the synthesis report and see
if those ROMs, RAMs, and FIFOs are still in block ram.
-- Mike Treseler
Article: 130631
Dale <dale.prather@gmail.com> wrote:
>I'm trying to rebuild an old project I did on ISE8.2i. I reinstalled
>8.2i on my PC. I also have 9.2i installed on the same PC. I don't
>know if they would conflict or not? My environment variable XILINX is
>point to ISE8.2. I'm using CoreGen to create quite a few ROMs, RAMs
>and FIFOs. CoreGen has a history of breaking things.
>So, I did a cleanup project files to begin with. Everything else is
>unchanged. When I rebuild the project it is 20% larger than the
>original project was. My project will no longer fit in the part.
>Where is all of the extra bloat coming from?
Checked these enviroment variables?
set path = .. (executable path)
setenv LD_LIBRARY_PATH .. (library path)
setenv XILINX .. ("home" path)
Article: 130632
On Mar 27, 8:03 pm, John Williams <jwilli...@itee.uq.edu.au> wrote:
> Hi Bin,
>
> bin.art...@gmail.com wrote:
> > I have spent the past few months slowly trying to get a PCI design
> > with Linux 2.6 on the Virtex 4. I have been able to overcome some of
> > the hurdles; however, I am still unable to boot up a working system.
> > If anyone has tried to do this (or has already done this) I would
> > apprecaite any help or suggestions. I can go into more detail as to
> > what I have done and where I am stuck if there is anyone who would be
> > willing to guide me!
>
> Are you using MicroBlaze or PPC?
I am using PPC.
>
> Have you verified PCI functionality with low level test apps - ie do a
> standalone EDK application that executes a PCI scan, make sure you can
> see the configuration space, do some simple config setup and try to move
> some data around.
I first downloaded a "hello_pci" standalone application from Xilinx
website. I
test my PCI-PCI Bridge and South Bridge and read device ID and vendor
ID back.
Xilinx's application note #945 has inspired me a lot. I did not try
to move any data around
because I have no idea how to do that. :-)
>
> If that's all working, then in Linux the PPC kernel uses more or less
> mainline PPC PCI handling code - you just need to do have some
> Xilinx-specific setup to enable the bridge, and you also need to tweak
> the config_read and _write routines to only do word accesses.
After that, I implemented Xilinx's board support package including
xparameter head file, ml410 early boot files, pci support files,
Board initialization file, did board specific setup, and fixed some
bugs
in its call tree, which took me almost a month.
I have attached my booting message in this mail. As you can see, I am
stuck at
"[ 11.805382] Freeing unused kernel memory: 100k init" . Usually
it's the last step
before the kernel starts root file system. I am sure my ramdisk and
root file system
were both working OK. My naive thought is that the kernel could not
register serial
port successfully (see time stamp [ 5.965954]). As a result, ttyS0 was
not able to
run and display messages after starting ramdisk. I would appreciate
any help or
suggestions on this.
It's also interesting to see my ml410 board respond me with a "ml300"
id.
My booting message was saying:
pci_scan: bus 0, device 8, id 030010ee
"10ee" is the vendor id for xilinx while "300" is the device id which
I think
might represent ml300. Does Xilinx forget to refresh its rom?
>
> Post on the linuxppc-embedded list to tap into the right channel.
I am about to do that :-)
>
> Regards,
>
> John
Here is my environment and tools:
-- Xilinx ML410 Rev C
-- Xilinx EDK 9.2i
-- Secret lab Linux v2.6 originally configured as platform Xilinx
ML403
And my booting message:
---------------------------------------------------------------------------
Xilinx ML410 Board-Specific Initialization:
ppb_init: dev = 9, id = ac23104c
pci_scan: bus 0, device 1, id 545110b9
pci_scan: bus 0, device 2, id 153310b9
pci_scan: bus 0, device 3, id 545710b9
pci_scan: bus 0, device 8, id 030010ee
pci_scan: bus 0, device 9, id ac23104c
pci_scan: bus 0, device 12, id 710110b9
pci_scan: bus 0, device 15, id 523710b9
sio_init: Device ID = 53 15, Revision = f3.
sio_init: LPT1 base = 0x0378, irq = 5.
sio_init: COM1 base = 0x03f8, irq = 4.
sio_init: COM2 base = 0x02f8, irq = 3.
sio_init: KBC irq = 1, PS2 irq = 1.
sio_init: Super I/O initialization complete.
loaded at: 00400000 006C21B4
board data at: 006C0124 006C01A0
relocated to: 00405154 004051D0
zimage at: 00406215 004EFDAA
initrd at: 004F0000 006BFDB0
avail ram: 006C3000 08000000
Linux/PPC load: console=ttyS0,9600 ip=off root=/dev/ram
Uncompressing Linux...done.
Now booting the kernel
[ 0.000000] Linux version 2.6.23-rc2-g0d62d8a8-dirty (bhuang2@rsass-
homer.uncc.edu) (gcc version 4.2.1) #190 Thu Mar 28
[ 0.000000] Xilinx ML40x Reference System (Virtex-4 FX)
[ 0.000000] Port by MontaVista Software, Inc. (source@mvista.com)
[ 0.000000] Zone PFN ranges:
[ 0.000000] DMA 0 -> 32768
[ 0.000000] Normal 32768 -> 32768
[ 0.000000] Movable zone start PFN for each node
[ 0.000000] early_node_map[1] active PFN ranges
[ 0.000000] 0: 0 -> 32768
[ 0.000000] Built 1 zonelists in Zone order. Total pages: 32512
[ 0.000000] Kernel command line: console=ttyS0,9600 ip=off root=/
dev/ram
[ 0.000000] Xilinx INTC #0 at 0x41200000 mapped to 0xE7FED000
[ 0.000000] PID hash table entries: 512 (order: 9, 2048 bytes)
[ 0.000175] Console: colour dummy device 80x25
[ 0.000241] console [ttyS0] enabled
[ 1.382947] Dentry cache hash table entries: 16384 (order: 4, 65536
bytes)
[ 1.466045] Inode-cache hash table entries: 8192 (order: 3, 32768
bytes)
[ 1.572643] Memory: 125852k available (1480k kernel code, 496k
data, 100k init, 0k highmem)
[ 1.764350] Mount-cache hash table entries: 512
[ 1.827727] PCI: Probing PCI hardware
[ 1.906477] ppc405_map_irq: bus 0 idsel 1 pin 1, res = 31
[ 1.970528] ppc405_map_irq: bus 0 idsel 2 pin 1, res = 31
[ 2.035157] ppc405_map_irq: bus 0 idsel 3 pin 1, res = 31
[ 2.099646] ppc405_map_irq: bus 0 idsel 8 pin 1, res = 31
[ 2.164225] ppc405_map_irq: bus 0 idsel 9 pin 1, res = 31
[ 2.228787] ppc405_map_irq: bus 0 idsel 11 pin 1, res = 31
[ 2.294400] ppc405_map_irq: bus 0 idsel 12 pin 1, res = 31
[ 2.360031] ppc405_map_irq: bus 0 idsel 15 pin 1, res = 31
[ 2.441645] SCSI subsystem initialized
[ 2.487503] usbcore: registered new interface driver usbfs
[ 2.553907] usbcore: registered new interface driver hub
[ 2.617790] usbcore: registered new device driver usb
[ 2.687574] checking if image is initramfs...it isn't (no cpio
magic); looks like an initrd
[ 4.548936] Freeing initrd memory: 1855k freed
[ 4.606889] io scheduler noop registered
[ 4.653232] io scheduler anticipatory registered (default)
[ 4.718790] io scheduler deadline registered
[ 4.769907] io scheduler cfq registered
[ 4.815634] Activating ISA DMA hang workarounds.
[ 5.667502] 0000:00:0f.0 OHCI: BIOS handoff failed (BIOS bug ?)
ffffffff
[ 5.798505] Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports,
IRQ sharing disabled
[ 5.892194] serial8250: ttyS0 at MMIO 0x0 (irq = 12) is a 16550A
[ 5.965954] Couldn't register serial port 0000:00:03.0: -28
[ 6.044910] RAMDISK driver initialized: 16 RAM disks of 65536K size
1024 blocksize
[ 6.141529] loop: module loaded
[ 6.178422] Uniform Multi-Platform E-IDE driver Revision:
7.00alpha2
[ 6.254522] ide: Assuming 33MHz system bus speed for PIO modes;
override with idebus=xx
[ 6.351314] ALI15X3: IDE controller at PCI slot 0000:00:0b.0
[ 6.418510] ALI15X3: chipset revision 196
[ 6.466414] ALI15X3: 100% native mode on irq 31
[ 6.520489] ALI15X3: simplex device: DMA forced
[ 6.574602] ide0: BM-DMA at 0xdfd0-0xdfd7, BIOS settings:
hda:DMA, hdb:DMA
[ 6.660918] ALI15X3: simplex device: DMA forced
[ 6.715201] ide1: BM-DMA at 0xdfd8-0xdfdf, BIOS settings:
hdc:DMA, hdd:DMA
[ 9.054991] usbmon: debugfs is not available
[ 9.106161] mice: PS/2 mouse device common for all mice
[ 9.168819] ali15x3_smbus 0000:00:0c.0: ALI15X3_smb region
uninitialized - upgrade BIOS or use force_addr=0xaddr
[ 9.290327] ali15x3_smbus 0000:00:0c.0: ALI15X3 not detected,
module not inserted.
[ 9.383605] RAMDISK: Compressed image found at block 0
[ 11.704980] VFS: Mounted root (ext2 filesystem) readonly.
[ 11.805382] Freeing unused kernel memory: 100k init
................kernel stops here................
---------------------------------------------------------------------------
regards,
Bin
Article: 130633I don't see the environment variables you mentioned except for the XILINX one and it's set to 8.2. To answer a few questions. * No, I have not opened the project in 9.2. * Yes, I have an archived version of the entire project including the ISE file. My ultimate goal is to make a slight change to the project w/out having to upgrade the project to 9.2 or 10.1. If EDK/ microblaze wasn't involved, I would just upgrade to the newest ISE release. * Yes, the service packs are updated to what they were including the IP library. * My top level is in ISE. Thanks, DaleArticle: 130634
"Dale" <dale.prather@gmail.com> wrote in message news:305574b6-a0b8-4a16-8b1b-2838527eca2d@13g2000hsb.googlegroups.com... > I'm trying to rebuild an old project I did on ISE8.2i. I reinstalled > 8.2i on my PC. I also have 9.2i installed on the same PC. I don't > know if they would conflict or not? My environment variable XILINX is > point to ISE8.2. I'm using CoreGen to create quite a few ROMs, RAMs > and FIFOs. CoreGen has a history of breaking things. > Have you opened this project in 9.2? Do you have an archived version of the .ise file? Is the service pack level the same (including IP) as it was when you did this project originally? /MikhailArticle: 130635
"Dale" <dale.prather@gmail.com> wrote in message news:305574b6-a0b8-4a16-8b1b-2838527eca2d@13g2000hsb.googlegroups.com... > I also have 9.2i installed on the same PC. I don't > know if they would conflict or not? Rename your 9.2 directory temporarily and you will know if it affects anything... Since EDK is involved, where is your top level? In ISE or EDK? /MikhailArticle: 130636
Kevin Neilson wrote: > mk wrote: >> On Fri, 28 Mar 2008 11:14:23 -0700 (PDT), FPGA >> <FPGA.unknown@gmail.com> wrote: >> >>> what does the following code do >>> output <= input[x*(y)-1 -: y]; >> >> That's called an indexed part select. The first expression signifies >> base and the second expression signifies width. It the sign is + it's >> an ascending select if it's negative it's a descending select. Your >> example is equivalent to input[x*(y)-1: x*(y)-y] ie you need to >> subtract (y-1) from the base to get the lower index. > > I think your equivalent should be: input[x*(y)-1: x*(y)-y+1] > > If I remember correctly, the width has to be a constant. In this case > that would mean y could be a parameter, but not an integer or register. > -Kevin The y that follows the indexed part select operator is the width. The vector mk showed has a width of y bits which is accurate. The vector Kevin showed has a width of y-1 bits which is inaccurate. Use mk's suggestion. Oh, and invest in a Verilog-2001 reference. Also - I removed the cross-post to comp.lang.vhdl because this is VERILOG! The VHDL abbreviations doesn't mean "Verilog Hardware Description Language." You can go to comp.lang.verilog for Verilog issues. - John_HArticle: 130637
Hi all, I announced a Getting Started With Xilinx FPGAs Video Guide here a little while ago. Clive (Max) Maxfield has now done a blog on them at http://www.pldesignline.com/blogs/206905099 Cheers, AnthonyArticle: 130638
Hi guys, This is one just for FPGA newbies, and possibly also a place where you can point people when they ask you what an FPGA is... Video #2 here answers the question "What is an FPGA?" http://www.burched.com/freevideos.ag.php That video also answers these other newbie questions: And how is that different to a microcontroller? Who makes FPGAs? What can I use FPGAs for? Why would I want to use FPGAs? How can I learn FPGA design?... ...hope that is useful for FPGA newbies:) Cheers, AnthonyArticle: 130639
Tony Burch <tony@burched.com.au> wrote: >Hi guys, >This is one just for FPGA newbies, and possibly also a place where you can >point people when they ask you what an FPGA is... I find it hard to elegantly explain sometime what an fpga is for people used to program sequential machines in sequential languages. And for everyone else what's is good for. They easily get caught in the "how do I get my sequential programs on it". The common answer is that it's a matrix of logic gates that can act as any other kind of chip at will, be it cpu, hdd controller, translator interface, dsp, etc.. I just don't think that answer really has a punch line thoe.Article: 130640
Hi Colin first of all i have to comment on my first impressions on your post. IMHO you have to provide a more abstract view of what went (in your opinion) wrong and specific details on diffs etc. I understand you tried to make a point but it would be better if you gave your thoughts more conceptually, and go down to details only when specifically asked too. > You may have been wondering why I have not > been posting much to Usenet and SystemC.org > since September 2007. Well yes ^_^. It seems that we had met in past within such threads. I actually (referring to an Sept. 2006) written my gcc-3.4.3 DLX backend. It supports everything except longs and has a few additions to standardesque DLX, for example a partial predication instruction. > In January 2006 I became a Ph.D. student in > the largest University of Pisa but I quit > in September 2007 (details follow). I'm trying to read your CV or webpage or something. Do you have any summary of your work (and previous ones) in the net? > VHDL Issues in Pisa > I had applied to Pisa in September 2005 when I was living in Ireland, having just > returned from my Swedish internship in the Netherlands. What were (and currently are) you job prospects in the Netherlands? Where you happy during your internship? What was/is the orientation of the R&D group there? Kind regards Nikolaos KavvadiasArticle: 130641
Hi FPGA has 1) 50mhz system clock from ext oscillator 2) 4Mhz clk that is async to the 50mhz problem, the 4MHz clk input sees double clk pulse, error rate approximate 1 to 10.000.000 unfortunatly the 4mhz clock needs to be used inside without phase delay, so oversampling and filtering with 50mhz is not an option, unless using very clever no delay glitch surpression filter external small R/C circuit on 5mhz doesnt change the error rate much, ah currently the 4mhz is clocked 1 time with 50mhz, this seemed to give better results as using the 4mhz clock directly any ideas how to really clean the 4mhz clock? or any thumb guess what is the likeliness to see double clk edges when sampling 4mhz with async 50mhz? could the "error rate" of such sampling be that 1:10M what I am seeing? I assume the 4 mhz clock is rather good, it coming from an ASIC and has total wire lenght from asic to FPGA maybe 20 mm (but over PCB edge connector). I did kinda think its hard to belive that the clock edge is so slow or noisy that 50mhz sampling could ever see double/wrong edges but guess i am wrong it doesnt seem to be cross talk either, as there arent much IOs toggling at all hm it looks like in rare cases the error is also one clock pulse missing! :) any good suggestions are welcome, how to troubleshoot the issue unfortunatly the FPGA is actel so can use any on-chip logic analyzer core, and the chip is rather full also, some internal signal could be routed out to external logic analyzer though if badly needed, but so far i am trying to fix the issue by thinking, and error-retry... AnttiArticle: 130642
Symon wrote: > Dear Grky, > > Did you win your place at Nevada in a poker game? :-) I'm guessing you're a > linebacker. > > Great post! > > Cheers, Syms. You know, one of these days I'll send you the bill for a new keyboard. I don't know how many times I spilled $insert_arbitrary_beverage over the old one laughing at one our your "snotty" comments :) cu, Sean -- My email address is only valid until the end of the month. Try figuring out what the address is going to be after that...Article: 130643
"Antti" <Antti.Lukats@googlemail.com> wrote in message news:e6010199-ca1d-4540-8ae3-a69a3a23b106@b1g2000hsg.googlegroups.com... > Hi > > FPGA has > 1) 50mhz system clock from ext oscillator > 2) 4Mhz clk that is async to the 50mhz > > problem, the 4MHz clk input sees double clk pulse, error rate > approximate 1 to 10.000.000 > unfortunatly the 4mhz clock needs to be used inside without phase > delay, so oversampling and filtering with 50mhz is not an option, > unless using very clever no delay glitch surpression filter > > external small R/C circuit on 5mhz doesnt change the error rate much, > ah currently the 4mhz is clocked 1 time with 50mhz, this seemed to > give better results as using the 4mhz clock directly > > any ideas how to really clean the 4mhz clock? > or any thumb guess what is the likeliness to see double clk edges when > sampling 4mhz with async 50mhz? > could the "error rate" of such sampling be that 1:10M what I am > seeing? > > I assume the 4 mhz clock is rather good, it coming from an ASIC and > has total wire lenght from asic to FPGA maybe 20 mm (but over PCB edge > connector). I did kinda think its hard to belive that the clock edge > is so slow or noisy that 50mhz sampling could ever see double/wrong > edges but guess i am wrong > > it doesnt seem to be cross talk either, as there arent much IOs > toggling at all > > hm it looks like in rare cases the error is also one clock pulse > missing! > > :) any good suggestions are welcome, how to troubleshoot the issue > > unfortunatly the FPGA is actel so can use any on-chip logic analyzer > core, and the chip is rather full also, some internal signal could be > routed out to external logic analyzer though if badly needed, but so > far i am trying to fix the issue by thinking, and error-retry... > > > Antti > > If you are sure the $MHz tr and tf are within the device clock spec (as is the voltage) then try putting the 4MHz clock into an onboard PLL configured for zero delay and narrow bandwidth, then use the PLL output for internal clocking. (Being a low life Altera user, don't know if this is available in Xilinx parts)Article: 130644
Antti wrote: > Hi > > FPGA has > 1) 50mhz system clock from ext oscillator > 2) 4Mhz clk that is async to the 50mhz > > problem, the 4MHz clk input sees double clk pulse, error rate > approximate 1 to 10.000.000 > unfortunatly the 4mhz clock needs to be used inside without phase > delay, so oversampling and filtering with 50mhz is not an option, > unless using very clever no delay glitch surpression filter How much delay is allowed? I assume you have already latched the clock once with every 50Mhz edge, to avoid meta stability problems. To avoid double clock pulses, you could feed a shift register with this latched signal and compare for "0111" and "1000" to detect edges more clean, maybe with an additional holdoff after detection to avoid detecting spikes. -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 130645
On Fri, 28 Mar 2008 13:53:45 -0700 (PDT), Dale <dale.prather@gmail.com> wrote: >I'm trying to rebuild an old project I did on ISE8.2i. I reinstalled >8.2i on my PC. I also have 9.2i installed on the same PC. I don't >know if they would conflict or not? My environment variable XILINX is >point to ISE8.2. I'm using CoreGen to create quite a few ROMs, RAMs >and FIFOs. CoreGen has a history of breaking things. > >So, I did a cleanup project files to begin with. Everything else is >unchanged. When I rebuild the project it is 20% larger than the >original project was. My project will no longer fit in the part. >Where is all of the extra bloat coming from? Check reports (.syr, .mrp) against archived ones ... if e.g. register counts have increased, consider that synthesis options (e.g. "equivalent-register-removal = yes" may have been changed in the re-install... - BrianArticle: 130646
On Sat, 29 Mar 2008 02:41:42 -0700 (PDT), Antti <Antti.Lukats@googlemail.com> wrote: >Hi > >FPGA has >1) 50mhz system clock from ext oscillator >2) 4Mhz clk that is async to the 50mhz > >problem, the 4MHz clk input sees double clk pulse, error rate >approximate 1 to 10.000.000 >unfortunatly the 4mhz clock needs to be used inside without phase >delay, so oversampling and filtering with 50mhz is not an option, >unless using very clever no delay glitch surpression filter however that doesn't stop you building analyzers (clocked on 50MHz) to diagnose the problem >external small R/C circuit on 5mhz doesnt change the error rate much, series-term (22-50R) at source may be the best bet ... but with 20mm trace length, that's unlikely to be the problem. >ah currently the 4mhz is clocked 1 time with 50mhz, this seemed to >give better results as using the 4mhz clock directly Also establishes that some sort of resynch is acceptable. >any ideas how to really clean the 4mhz clock? >or any thumb guess what is the likeliness to see double clk edges when >sampling 4mhz with async 50mhz? Metastability : about once in recorded human history :-) Other causes : e.g. crosstalk during the linear window : much higher. >could the "error rate" of such sampling be that 1:10M what I am >seeing? >I assume the 4 mhz clock is rather good, it coming from an ASIC and >has total wire lenght from asic to FPGA maybe 20 mm (but over PCB edge >connector). I did kinda think its hard to belive that the clock edge >is so slow or noisy that 50mhz sampling could ever see double/wrong >edges but guess i am wrong > >it doesnt seem to be cross talk either, as there arent much IOs >toggling at all > >hm it looks like in rare cases the error is also one clock pulse >missing! Build a trivial analyzer clocked at 50MHz. count "high time" and "low time" in 50MHz cycles; log the max and min "high time" counts (update the log after each rising edge); ditto low time. Good results would be 6 cycles min, 7 cycles max (+/-1 from asynchronicity) Classic edge bounce will show min high (or low) time of 1 cycle; glitches away from edges (e.g. from major crosstalk) may show e.g. min high 1, min low 3 cycles. Missing pulses will show large "max" times. etc My guess would be min times of 1, i.e. double-clocking edges, from (small amplitude) crosstalk which coincides with a slow 4MHz edge. Oh . And does this occur on one board, or on several identical ones? - BrianArticle: 130647
Antti wrote:
> Hi
>
> FPGA has
> 1) 50mhz system clock from ext oscillator
> 2) 4Mhz clk that is async to the 50mhz
>
> problem, the 4MHz clk input sees double clk pulse, error rate
> approximate 1 to 10.000.000
> unfortunatly the 4mhz clock needs to be used inside without phase
> delay, so oversampling and filtering with 50mhz is not an option,
> unless using very clever no delay glitch surpression filter
>
Hi Antti,
I guess your problem is a slow edge rate on your 4MHz clock. Does this fix
it?
process(clk_50M)
begin
if rising_edge(clk_50M) then
four_meg_d <= four_meg_in;
four_meg_dd <= four_meg_d;
end if;
end process;
process(four_meg_in, four_meg_dd)
begin
if four_meg_in = '1' and four_meg_dd = '0' then
four_meg_out <= '1';
elsif four_meg_in = '0' and four_meg_dd = '1' then
four_meg_out <= '0';
end if;
end process;
HTH., Syms.
Article: 130648On Mar 29, 10:41 am, Antti <Antti.Luk...@googlemail.com> wrote: > Hi > > FPGA has > 1) 50mhz system clock from ext oscillator > 2) 4Mhz clk that is async to the 50mhz > > problem, the 4MHz clk input sees double clk pulse, error rate > approximate 1 to 10.000.000 > unfortunatly the 4mhz clock needs to be used inside without phase > delay, so oversampling and filtering with 50mhz is not an option, > unless using very clever no delay glitch surpression filter > > external small R/C circuit on 5mhz doesnt change the error rate much, > ah currently the 4mhz is clocked 1 time with 50mhz, this seemed to > give better results as using the 4mhz clock directly > > any ideas how to really clean the 4mhz clock? > or any thumb guess what is the likeliness to see double clk edges when > sampling 4mhz with async 50mhz? > could the "error rate" of such sampling be that 1:10M what I am > seeing? > > I assume the 4 mhz clock is rather good, it coming from an ASIC and > has total wire lenght from asic to FPGA maybe 20 mm (but over PCB edge > connector). I did kinda think its hard to belive that the clock edge > is so slow or noisy that 50mhz sampling could ever see double/wrong > edges but guess i am wrong > > it doesnt seem to be cross talk either, as there arent much IOs > toggling at all > > hm it looks like in rare cases the error is also one clock pulse > missing! > > :) any good suggestions are welcome, how to troubleshoot the issue > > unfortunatly the FPGA is actel so can use any on-chip logic analyzer > core, and the chip is rather full also, some internal signal could be > routed out to external logic analyzer though if badly needed, but so > far i am trying to fix the issue by thinking, and error-retry... > > Antti I am almost sure your 4Mhz frequency is clean on your board. But verify! If your 4MHZ is stable then the trouble is coming inside your FPGA. Before all, verify you are using a Global buffer for the 50Mhz. Then you have to register all inputs with your 50MHz and to register the 4Mhz input with 50MHz too (f4mhz_reg). Then verify after Place & Route, your are using IOB registers (registers in the PADs)! The use of IOB registers is very important. When this is done and verified, return to your code and add a new Flip- Flop (50Mhz) to the registered 4Mhz input (f4mhz_reg2), and detect the rising edge of the 4Mhz by f4mhz_rise_pulse <= '1' WHEN (f4mhz_reg = '1') AND (f4mhz_reg2 = '0') ELSE '0'; Finally, all your flip-flops inside the FPGA core should use 50Mhz clk and the f4mhz_rise_pulse as clock enable. I am almost sure this will resolve your design issue. This is a very common issue for all VHDL / FPGA students . Hoping this resolve the problem. But resolving the trouble is not enough. We have to understand what was really the trouble and what happen when we do not synchronize all inputs in 2 clock domain ? Let me know if you want to understand what really was the trouble. - Laurent http://www.amontec.com ---- Introducing new USB Instrument Platform (Hi-Speed USB2.0 + Xilinx FPGA ) in a very small format. Small as a Amontec JTAGkey ! New fast JTAG interface is coming with!Article: 130649
I've got a fairly large design that I've been working with in ISE 9.2.04 for a while - it takes about 90% of a V2P100 and runs to completion in about 3.5 to 4 hours on my Linux x86_64 system (Athlon dual core 3800 w/ 4GB) using home-made make scripts. I decided to take 10.1 out for a spin to see if it really helps speed things up. Here's what I've seen on the first few runs: - XST seems to run about as fast as it used to. - NGDBUILD seems faster and seems to find errors in timing exceptions more quickly. - MAP works about the same. - PAR takes a lot longer to run. I'm seeing 8 hour runs that used to take 2 - 2.5 hours in 9.2.04 with the same constraints. It appears to be coming up with bad placements (Phase 12.27 seems to take _forever_) that are impossible to route successfully. I'm in the process of adding more timing exceptions and this seems to help, but I still haven't had a successful PAR run. Let me re-iterate: 9.2.04 didn't have any trouble with this design using the exact same source and constraints. Summary: 10.1 isn't working as well as 9.2.04. I'll probably be shelving it and waiting for the service pack. Comments / Criticism / Suggestions welcome. Eric
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z