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Mike Treseler <mike_treseler@comcast.net> wrote:
> If I worked for Xilinx I would write an
> ap note in vhdl and verilog for a useful
> application example that infers block ram from code,
> and then reference that example in all related documents.
it's all (public) available:
- XAPP463 ("Using BRAMs in Spartan-3 FPGA") applies also for
virtex-2 and with some additions/modifications for the newer virtex
parts.
- In the xilinx "synthesis and simulation guide" chapter 4,
page 152 pp, there are some (usefull) generic HDL code examples: How
to implement a "generic BRAM" in VHDL and/or verilog.
WD
--
Article: 130126On Mar 15, 9:11 am, ertw <gil...@hotmail.com> wrote: > Hi, > > I have a simple question about memory organization. I would like to > write a memory controller for IS61LV25616AL SRAM (256K x 16) but I am > having trouble understanding how the memory organization works. > > Datasheet says the memory is organized as 262,144 words by 16 bits > which is 256K x 16 but what does that mean in terms of rows and > columns ? > > Is there a memory tutorial that someone can point me to ? or maybe a > memory controller that someone has written for an SRAM ? > > Thanks, That's an SRAM, not an SDRAM. There are exactly as many address lines as required to address 256k locations. It also doesn't appear to be pipelined, so you just need to make sure that your controller meets the setup & hold requirements of the part, and registers the read data at the appropriate time.Article: 130127
On Mar 15, 7:24=A0am, Antti <Antti.Luk...@googlemail.com> wrote: > On 15 Mrz., 15:07, Mike Treseler <mike_trese...@comcast.net> wrote: > > > > > Antti wrote: > > > yes, Xilinx has purchased many things for slow death. > > > in 2004 just before the byout by Xilinx Triscend was about to come to > > > the market with the FPGA devices with > > > ARM+ethernet+ADC+something i dont remember > > > The key phrase is *about to* > > Most failed startups are responsible for their own deaths > > because the marketing geniuses overestimate demand > > for the gizmo, then react by changing its > > specifications until the money is gone. > > A last-minute acquisition at least saves the > > jobs of a few engineers. The "almost finished" > > product is often a mess. > > > =A0 =A0 =A0-- Mike Treseler > > sure! it could be they would have died anyway. > but now we never know. > > Antti If a group of people is lost in the desert, about to die of thirst, and somebody rescues them, gives them shelter, adopts them and gives them productive work, is that bad ? Yes, we will never know whether they might have finally found an oasis... But if you ask those people now, the are happy to be in the X tent. Beats being a white skeleton in the desert. Peter AlfkeArticle: 130128
On 15 Mrz., 20:33, Peter Alfke <al...@sbcglobal.net> wrote: > On Mar 15, 7:24 am, Antti <Antti.Luk...@googlemail.com> wrote: > > > > > On 15 Mrz., 15:07, Mike Treseler <mike_trese...@comcast.net> wrote: > > > > Antti wrote: > > > > yes, Xilinx has purchased many things for slow death. > > > > in 2004 just before the byout by Xilinx Triscend was about to come to > > > > the market with the FPGA devices with > > > > ARM+ethernet+ADC+something i dont remember > > > > The key phrase is *about to* > > > Most failed startups are responsible for their own deaths > > > because the marketing geniuses overestimate demand > > > for the gizmo, then react by changing its > > > specifications until the money is gone. > > > A last-minute acquisition at least saves the > > > jobs of a few engineers. The "almost finished" > > > product is often a mess. > > > > -- Mike Treseler > > > sure! it could be they would have died anyway. > > but now we never know. > > > Antti > > If a group of people is lost in the desert, about to die of thirst, > and somebody rescues them, gives them shelter, adopts them and gives > them productive work, is that bad ? Yes, we will never know whether > they might have finally found an oasis... > But if you ask those people now, the are happy to be in the X tent. > Beats being a white skeleton in the desert. > Peter Alfke Peter, I was almost to write to you and personally to appology of being to hardneckig on some issues, because I think I may have lived some of my personal frustration out. The last employer not only fired me while i was thinking that I was on vaccation, they did not last paycheck before I had to sue them, and then they lied to the unemployment agency that "I did not come to work REPEATEDLY". This was of course reason to cancel 3 months un- employment aid payments. I will not name the company. But bizzarre is that that company uses illegal nonlicensed development software (Xilinx, Mentor, Synplicity...) on more than 6 work places, and does military contracts where it uses unlicended Xilinx IP cores (with fake license!). And they dare to lie to the employment agency just for revenge (because I sued to get last paycheck)! Well some lessons are pretty hard. I think we watch "Joe vs Volcano" today, looks like one of those days. Antti stands up and goes and brings his wallet. opens it, and translates text from paper under the inside transparent pocket: "Loan Notice I, Antti Lukats, did borrow 10 (ten) EUR from the money directly donated for the food for my children" /A. Lukats/ 13. April 2005, Munich, Germany" I was working at that company at that time. I cant pay back those 10 EUR ever, I need to wait for my children to grow up to understand and "clear the loan". Til that time that loan is not paid back. Eh, maybe that all is still not enough excuse of my harsh words regarding the death of Triscend. And sure the folks are happy at X, I believe that, its just pitty that some products die because of marketing decisions. cheers everyone, AnttiArticle: 130129
"Thorsten Kiefer" <webmaster@nillakaes.de> wrote in message news:47da43e3$0$581$6e1ede2f@read.cnntp.org... >> Also, don't forget to change the configuration mode back to master >> serial after you have programmed the platform flash. Oh, you have to >> either cycle power or press the 'FGPA program' switch (if this is one on >> the board) before the FPGA will be loaded from the platform flash. > > I got it working now. I can leave the jumpers in "master serial" while > I program the flash. The fpga boots automatically from the flash. > > Thanks for your help! > > -Thorsten Yes, the way I always do it is to just leave the jumpers set for master-serial mode and then just program the XCF04 prom every time. And if you check the "Load FPGA" checkbox when downloading, the FPGA will automatically load from the prom at the end of the programming. Cheers, Anthony Burch Getting Started With Xilinx FPGAs Video Guide http://www.BurchED.comArticle: 130130
On 14 Mrz., 10:23, Thorsten Kiefer <webmas...@nillakaes.de> wrote: > > Also, don't forget to change the configuration mode back to master > > serial after you have programmed the platform flash. Oh, you have to > > either cycle power or press the 'FGPA program' switch (if this is one on > > the board) before the FPGA will be loaded from the platform flash. > > I got it working now. I can leave the jumpers in "master serial" while > I program the flash. The fpga boots automatically from the flash. > > Thanks for your help! > > -Thorsten Yes, the jumper setting is PARTIAL solution, the JTAG is always enabled and it always OVERRIDES the other configuration modes, but... Xilinx has never managed to the JTAG configuration with Impact work correctly and the result is that depending the configuration and impact version and cable version the jtag configuration may fail if the master serial configuration is enabled and the configuration memory containts a bitstream. If the config eeprom is erased then leaving the jumpers in master mode would not do any harm and you can use jtag config. so you just trapped into a XILINXBUG AnttiArticle: 130131
ERROR:HDLParsers - Cannot reanme dependency database for library "work", file is "xst/work/hdpdeps.ref". Temporary database file "C:\ \prj\fpga\s3ask\uart_bypass\xst\work\xil_284_5" will remain. System error message is: No such file or directory any idea or solution? hopefully the solution isnt ISE 10.1 AnttiArticle: 130132
On 16 Mrz., 17:18, Antti <Antti.Luk...@googlemail.com> wrote: > ERROR:HDLParsers - Cannot reanme dependency database for library > "work", file is "xst/work/hdpdeps.ref". Temporary database file "C:\ > \prj\fpga\s3ask\uart_bypass\xst\work\xil_284_5" will remain. System > error message is: No such file or directory > > any idea or solution? > hopefully the solution isnt ISE 10.1 > > Antti Problem issue tracked down. ISE 9.2SP4 is recognized AS VIRUS, so disabling antti-virus software will let the HDL parser to pass without errors. Why and how has xilinx managed to create software that triggers virus on alert on task "HDL parse" ??? AnttiArticle: 130133
Good morning,my name is Emad i leave in egypt ,i taken BSC in communication & electronics engineering with GPA "A" an now i preper my master in SDR technology.but i don't have any idea to How can i start.i have a strong knowldge in FPGA and VHDL and digital electronics.please advise me how can i start.Article: 130134
On 16 Mrz., 17:29, "Eng.Emad Samuel" <eng.emadsam...@gmail.com> wrote: > Good morning,my name is Emad i leave in egypt ,i taken BSC in > communication & electronics engineering with GPA "A" an now i preper > my master in SDR technology.but i don't have any idea to How can i > start.i have a strong knowldge in FPGA and VHDL and digital > electronics.please advise me how can i start. If you leave egypt where do you go? to DDR? The only place that belongs to DDR is small island near cuba that was given as gift to DDR and was forgotten to merge into BRD when the wall falled. A good idea to start is to start. Just start understanding the topic. Your "master" is probably defined a bit more precise than "SDR technology" ? Antti who never mastered the master, it was too boring.Article: 130135
ISE 9.2SP4 blues again.. HDL synthesis passes only after anti-virus disable, ok learned that ISE is now in VIRUS category. but how to program with Impact? until SP4 it was somewhat understandable, you select the device, right click with the mouse, select program, and it programs. but since SP4 that is no longer possible! right click only allows to assign new file! ok, i learned that too, you must go "processes window" then double click, then wait the dialog, and click. but why is the "program" removed from right click menu??? every single SP brings new surprises. Is that all? to surprise the customers with new features? things to know? workarounds to get things to use to work to work again? Antti is not only who would like to see Xilinx to improve the SW quality. And maybe maybe it would be time for Xilinx to arrange some beta-testers who would do their job?Article: 130136
Eng.Emad Samuel wrote: > Good morning,my name is Emad i leave in egypt ,i taken BSC in > communication & electronics engineering with GPA "A" an now i preper > my master in SDR technology.but i don't have any idea to How can i > start.i have a strong knowldge in FPGA and VHDL and digital > electronics.please advise me how can i start. One generally starts their masters thesis journey by researching topics such as "Software Defined Radio." If you know nothing about SDR, find out about it. Check out other universities that have research into SDR and find if there are any resources available to outside researchers. FPGAs and VHDL are often used in SDR but you need to know what you want to do to implement an SDR approach. THere may be a couple people here who have done work with SDR but you really need to get a basic understanding of the current state of research and development to approach masters-level work on this subject. Enjoy the journey, - John_HArticle: 130137
"John Adair" wrote >
> If you have a similar tristate function on more than one register it
> may be your synthesiser being clever and removing a "duplicate"
> register. If reduced like that then when you get to the back end a
> single tristate register can't be mapped into the I/O and be shared
> and hence ends up in the fabric. Have a look at the remove duplicate
> register synthesis options and turn that off and see if that solves
> your issue.
Thanks John (Symon and John_H too).
I do use the FPGA editor to visualize the placement of the logic.
Is there a faster method through a report? And I don't see any
incompatibility between the tristate clock and the data_out clock.
And I have the remove duplicate register synthesis option off.
I even tried to introduce bogus independent data into the tristate
output so the synthesiser would not be able to see duplicate
registers. These didn't work.
What did work is that I moved the registration of the tristate and
the data_out to the top module. This was fairly easy to do by cutting
the if clk'event and clk='1' line, changing the sensitivity from
clk to a list of combinatorial signals, and using a clocked process
in the top module to assign the submodules tristate and data_out.
I have the IOB primitives in a separate submodule as I have seen
Xilinx often do on their memory models. So one has this heirarchy:
top
/ \
IOBs work
This is probably a Xilinx ISE9.2 bug.
The data_out signals were properly placed with or without the
registration in the top module. The tristate signals were not.
Brad Smallridge
AiVision
Article: 130138the headers of the latticemico32 verilog source files don't imply changed code may be redistributed: // This confidential and proprietary software may be used only as authorised // by a licensing agreement from Lattice Semiconductor Corporation. // The entire notice above must be reproduced on all authorized copies and // copies may only be made to the extent permitted by a licensing agreement // from Lattice Semiconductor Corporation. Neither does the Lattice Web site http://www.latticesemi.com/products/intellectualproperty/ipcores/\ mico32/mico32opensourcelicensing.cfm talk about code redistribution, also it tells: > Allows the entire user community to identify areas of enhancements and to > help develop higher quality solutions and make modifications So the only legal way to make a modification available to others is to send the differences to Lattice and hope for inclusion in some next release. Not an option to trust in, when Mico32 on other then Lattice FPGA is one's target! The software deployment doesn't deploy the license. You can however download it seperate, by trying to download again and mark the license agreement box and save it to a local file. Apendix C, Top 2 however talks about the possibility to redistribute changed code free, in the sense of open source. What counts? Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 130139
Brad wrote: > > I have the IOB primitives in a separate submodule as I have seen > Xilinx often do on their memory models. > I've previously had problems with XST + hierarchy + registered tristates, with a 'fix' being placing the IO tristate stuff all at the top level. It sounds like you found a workaround already, but here's an old post on getting this to work for S3 with XST 6.x and 7.x, see the tristate comments in the code snippets and archive: http://groups.google.com/group/comp.arch.fpga/msg/afce49b66c1989aa BrianArticle: 130140
"Mike Treseler" <mike_treseler@comcast.net> wrote in message news:64246kF29nuntU1@mid.individual.net... > Xilinx User wrote: > >> I hope Xilinx introduces Systemverilog synthesis with ISE 10.1 > > Systemverilog is mainly a simulation upgrade. True enough, but then again, both Verilog and VHDL started out as 'simulation' (or documentation) languages ... now look where they are!Article: 130141
On Mar 14, 8:24=A0am, austin <aus...@xilinx.com> wrote: > Morten, > > We chose different paths: =A0Altera used hardened logic to get their > speed, where we chose to stay general, and use any pins/any fabric/any > standard. > > We have DDR3 designs that are also working at 533 MHz. > > Best to sit down and talk with your FAE on the subject. > > There are many other factors to consider (not he least of which is we > are in full production on Virtex 5 LX, LXT, SXT, and they are just now > in ES on on few parts, with S3 GX canceled completely). > > Even though Altera has some really mean, cool, and neat power point > presentations, we basically have no competition whatsoever at 65nm at > the high end (as you can't ship power point in your systems). > > Austin While Virtex 5 has indeed been shipping longer and is a very strong product, Stratix III FPGAs are shipping and doing well. Altera ships production qualified Stratix III FPGAs this week and has rolled out multiple devices. Our customers have highlighted they like the sizable density advantages of the biggest FPGA, the 3SL340 device (>15% higher LE count, 35% more flip-flops, 60% more memory, 3X DSP resources). Other customers like the clear performance advantages (2x speed grade edge). Others like the compile time advantage (1/3 the compile time to get far higher utilization). Still others like the power benefits (30% lower power validated on silicon). And others like the working 533 MHz DDR3 solution that also supports DIMMs. Stratix II GX continues to be the optimal solution for customers requiring transceiver performance >3.75 Gbps, though Virtex 5 LXT is indeed a very strong product for slower speed designs. Please contact your Altera rep for further details on any of the products above. We also have some very nice PowerPoint presentations. Dave Greenfield Altera Product MarketingArticle: 130142
On 17 Mrz., 01:21, Uwe Bonnes <b...@hertz.ikp.physik.tu-darmstadt.de> wrote: > the headers of the latticemico32 verilog source files don't imply changed > code may be redistributed: > // This confidential and proprietary software may be used only as authorised > // by a licensing agreement from Lattice Semiconductor Corporation. > // The entire notice above must be reproduced on all authorized copies and > // copies may only be made to the extent permitted by a licensing agreement > // from Lattice Semiconductor Corporation. > > Neither does the Lattice Web sitehttp://www.latticesemi.com/products/intellectualproperty/ipcores/\ > mico32/mico32opensourcelicensing.cfm > talk about code redistribution, also it tells: > > > Allows the entire user community to identify areas of enhancements and to > > help develop higher quality solutions and make modifications > > So the only legal way to make a modification available to others is to > send the differences to Lattice and hope for inclusion in some next > release. Not an option to trust in, when Mico32 on other then Lattice FPGA > is one's target! > > The software deployment doesn't deploy the license. You can however download > it seperate, by trying to download again and mark the license agreement box > and save it to a local file. Apendix C, Top 2 however talks about the > possibility to redistribute changed code free, in the sense of open source. > > What counts? > > Bye > -- > Uwe Bonnes b...@elektron.ikp.physik.tu-darmstadt.de > > Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ---------- Uwe, please read Lattice main License, Appendix C it clearly says ALL FILES GENERATED by Mico32 tools are subject to the open-source licensing, so it over-rides whatever is prefixed into the hdl source code. you can distribute those files under open-source license, also if modfied and you can distribute you own addons under any license you want and there is no vendor locking to Lattice, the stuff under lattice opensource license can be implemented for ANY FPGA or ASIC this is how i read it, Antti PS there is DDR2 IP Core mico32 so you can use it on Spartan3A starter board :)Article: 130143
On 17 Mrz., 07:00, Dave Greenfield <dav...@altera.com> wrote: > On Mar 14, 8:24 am, austin <aus...@xilinx.com> wrote: > > > > > Morten, > > > We chose different paths: Altera used hardened logic to get their > > speed, where we chose to stay general, and use any pins/any fabric/any > > standard. > > > We have DDR3 designs that are also working at 533 MHz. > > > Best to sit down and talk with your FAE on the subject. > > > There are many other factors to consider (not he least of which is we > > are in full production on Virtex 5 LX, LXT, SXT, and they are just now > > in ES on on few parts, with S3 GX canceled completely). > > > Even though Altera has some really mean, cool, and neat power point > > presentations, we basically have no competition whatsoever at 65nm at > > the high end (as you can't ship power point in your systems). > > > Austin > > While Virtex 5 has indeed been shipping longer and is a very strong > product, Stratix III FPGAs are shipping and doing well. Altera ships > production qualified Stratix III FPGAs this week and has rolled out > multiple devices. > > Our customers have highlighted they like the sizable density > advantages of the biggest FPGA, the 3SL340 device (>15% higher LE > count, 35% more flip-flops, 60% more memory, 3X DSP resources). > Other customers like the clear performance advantages (2x speed grade > edge). > Others like the compile time advantage (1/3 the compile time to get > far higher utilization). > Still others like the power benefits (30% lower power validated on > silicon). > And others like the working 533 MHz DDR3 solution that also supports > DIMMs. > > Stratix II GX continues to be the optimal solution for customers > requiring transceiver performance >3.75 Gbps, though Virtex 5 LXT is > indeed a very strong product for slower speed designs. > > Please contact your Altera rep for further details on any of the > products above. We also have some very nice PowerPoint presentations. > > Dave Greenfield > Altera Product Marketing hiphip hurraa..! V5 is nice product for lower speed designs ;) eh, but seriously there are companies who make BIG promises and decrease the real numbers, so has MGT performance gradually decreased while technology advanced V2ProX -> V4 -> V5, Lattice as example hasnt ever promised MGT speeds higher then they are able to deliver, they say that they can do up to 3.6G, hmmm... quote "SIIGX continues"... it does actually confirm the statement from Xilinx that SIII-GX is cancelled. So maybe Altera has also problems above 3.6G with SIII-GX, so it isnt even offered, forcing the MGT user to use one family older silicon ? Ok, whatever Altera has at the moment (compared to Xilinx) a) better package options for low cost families b) better offers and package options for CPLD (MAX2/Z) This is something Xilinx CAN NOT DENY. Maybe the think flexible small form factor package options are not important for consumer market. Maybe. And maybe Xilinx is trying to get out from CPLD business. Maybe. If not then its pretty much time to offer low cost small factor FPGAs and something new for CPLD-like desings for Xilinx. Or maybe increase MGT speed to >6G for Virtex-6 ? Eh even V5FXT isnt officially released. Maybe Xilinx is so busy doing the RAD-hardening for V5, its still hard task and they only got 23M$ contract todo this. Eh hope the rad-hardening of V5 doesnt add any other delay into the release of normal V5 AnttiArticle: 130144
hi, i am going to use easics tool for generating crc32 verilog code (8bit input) (www.easics.com/webtools/crctool) . i was able to implement correctly.but i need more info to how use this crc to generate FCS of a ethernet packt. i heard about there must be some bit reversal before applying to crc generator. but i am not clear about it .can any one guide me to what have to data stream before applying to crc and when checksum created if further processing had to be done on checksum thanks dilanArticle: 130145
Hi. It's probably not very good place for asking such, but there're should be at least those who knows starting points. We need to design our own CPU which can be very slow. It can execute each instruction, let's say, up to 50 cycles. We don't care about speed, and we are also don't care about memory size for microcode, but we're really care about CPU unit size. Where to read about CPU designing techniques, which are about shifting all possible to microcode from CPU unit? Extreme case will be probably Turing machine, but it's not practical. CPU registers and instructions in our case should be looks like ARM9 processor, maybe.Article: 130146
Dilan <dilan2005@gmail.com> wrote:
>hi,
> i am going to use easics tool for generating crc32 verilog code
>(8bit input) (www.easics.com/webtools/crctool) . i was able to
>implement correctly.but i need more info to how use this crc to
>generate FCS of a ethernet packt.
>i heard about there must be some bit reversal before applying to crc
>generator. but i am not clear about it .can any one guide me to what
>have to data stream before applying to crc and when checksum created
>if further processing had to be done on checksum
The crc you need to apply is the CRC32 AUTODIN II. This is to be applied to
all bits after the frame start. In 10/100M ethernet each 4-bits is in
reverse order (low nibble - high nibble). So you may need to swap these
before feeding the bits to the crc32 generator.
A C example of this crc is at:
http://darwinsource.opendarwin.org/10.3/text_cmds-30/cksum/crc32.c
You can use it for verification this way:
cat pktdata | cksum -o 3 | perl -ne 'if( /^(\d+)/ ){ printf("%08X\n",$1); }'
A tip is to capture some packets and use them as reference to verify your
crc is correct. Watch out for the order of bits coming out of the crc
generator aswell, sometimes these may need swapping aswell.
A quick way to find accidential bit swaps is to display the number in
binrary like this: perl -e 'printf("%032b\n",2);'
Hope this helps you a bit.
Article: 130147Austin, Thanks for your reply. I know this is kinda flamebait for you and your competitor, and I will review all postings with care. I have put my xilinx dealer to the work of finding real solution (not powerpoints, or postings on this site ;)) working at high speed. I don't really think we will get to 533Mhz, but want to compare REAL performance. For our upcoming design DDR speed and IO count is the main criterias for selection. A 32bit design is of no help for me. Altera claims to have 12 dedicated DQS pins on every side, where 2 sides can run at 533Mhz on their fastest device (wich is theoretically 216 pins when using 9bit ECC mem) . They claim to have 72bit real hw proving this, and Im waiting to see how this is done. For Xilinx, I have no idea how wide bus they can do. I've only seen 64bit designs at much lower rate for now. I am hoping they(you?) can show me something better. I know there is a lot of the "marketing numbers" out there and my colleagues have wide experience on trying to achive "marketing" numbers (and even got the supplier convinced that their numbers didn't work). Because of this, I need to see a working design before aiming at any number. Best regards, Morten "austin" <austin@xilinx.com> wrote in message news:fre5b8$71c1@cnn.xsj.xilinx.com... > Morten, > > We chose different paths: Altera used hardened logic to get their > speed, where we chose to stay general, and use any pins/any fabric/any > standard. > > We have DDR3 designs that are also working at 533 MHz. > > Best to sit down and talk with your FAE on the subject. > > There are many other factors to consider (not he least of which is we > are in full production on Virtex 5 LX, LXT, SXT, and they are just now > in ES on on few parts, with S3 GX canceled completely). > > Even though Altera has some really mean, cool, and neat power point > presentations, we basically have no competition whatsoever at 65nm at > the high end (as you can't ship power point in your systems). > > AustinArticle: 130148
climber.tim@gmail.com wrote: >Hi. >It's probably not very good place for asking such, but there're should >be at least those who knows starting points. >We need to design our own CPU which can be very slow. It can execute >each instruction, let's say, up to 50 cycles. We don't care about >speed, and we are also don't care about memory size for microcode, but >we're really care about CPU unit size. >Where to read about CPU designing techniques, which are about shifting >all possible to microcode from CPU unit? Extreme case will be probably >Turing machine, but it's not practical. CPU registers and instructions >in our case should be looks like ARM9 processor, maybe. A simple technique is to just implement the very basic instructions a cpu needs and then implement the rest as software functions. Instructions that you ought to have: Jump: Load instruction pointer from memory JumpSub: Push current instruction pointer on stack (stack++) Return: Load instruction pointer from stack (stack--) Move memory -> register Move register -> memory Compare register <=> register and jump if equal Increase/Decrease register Shift left/right Add register + register -> register This should give basic functionality for a performance penalty.Article: 130149
On Mon, 17 Mar 2008 01:37:43 -0700 (PDT), climber.tim@gmail.com wrote: >Hi. >It's probably not very good place for asking such, but there're should >be at least those who knows starting points. >We need to design our own CPU which can be very slow. It can execute >each instruction, let's say, up to 50 cycles. We don't care about >speed, and we are also don't care about memory size for microcode, but >we're really care about CPU unit size. >Where to read about CPU designing techniques, which are about shifting >all possible to microcode from CPU unit? Extreme case will be probably >Turing machine, but it's not practical. CPU registers and instructions >in our case should be looks like ARM9 processor, maybe. Have you looked at the obvious published options such as Picoblaze? It's tiny. Anything that looks like an ARM9 will NEVER be tiny. Do you *need* 32-bit? What are you proposing to do with this slow CPU? -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.
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