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PFC wrote: (snip) > An Ethernet MAC does not know about IP addresses, only Ethernet MAC > addresses. Ethernet sees IP packets as just data with a label that says > "protocol=IP", it does not use the IP address in any way. Ethernet > routing is based on the MAC address. That is , a type of X'0800' > Now your PC which is on Ethernet uses the ARP protocol to query the > network for "which is the MAC address of the machine with IP > xx.xx.xx.xx ?", it is a broadcast packet that all machines receive and > the one which feels concerned responds. Yes, but when you construct a UDP packet with IP header you still have to get the IP address into the packet. It should be possible to do all that with FPGA logic (and a medium sized state machine). -- glenArticle: 133026
ALuPin@web.de wrote: > I have described a state machine running with an external pixel clock. > As I could see > on the oscilloscope the ScanDetect signal becomes high indicating that > the pixel clock > is stable. BUT the clock is not stable for some while after Scdt > becomes high. The clock > seems to tune after some us. (stable clock should have around 100MHz) > The clock is changing its frequency, high and low phases are > symmetrical. You should be sure that if the FSM gets into an undefined state that it will be able to get out of that state in a reasonable number of clock cycles. Usually that is enough. -- glenArticle: 133027
Philip Freidin wrote: <snip> > > What you describe is something quite different. Two separate > synchronization paths, one clocked on the rising edge of the 40 MHz > clock and one clocked by the falling edge. This gives two paths > 12.5 ns out of phase, as you describe. But then you (typically) > have to combine these signals into 1 signal, in (one would assume) > the 40 MHz, at which point you are back to 25 ns resolution. > To retain the 12.5 ns resolution (of questionable value given the > asynchronous nature of the signal), you have to duplicate the down > stream logic, or pass it around with a tag to indicate which > synchronizer reported the signal first. Hardly something that is > typically needed. What 'is typically needed', depends on the application :) There are a number of event/edge capture schemes, where extra time resolution is a good thing. Still, I am sure we have expanded the OP's horizons, by showing he can resolve to 12.5ns relatively easily. (should this, or another app require it). -jgArticle: 133028
PFC --- > Welcome ;) Thank you! > It contains all you need including the free simulator which Great > Try Verilog and VHDL and choose according to your taste. I've seen some examples of VHDL on www.jrok.com (ZX Spectrum with AT keyb) and I'm amazed how simple the source is! > Always test your pin allocations BEFORE manufacturing the PCB ! > The synthesis tool will tell you if you want to use an impossible pin mapping. Why? Aren't all pins I/O? Jim Granville ------------- > What do you program the GALs with now ? - many pgmrs also > pgm CPLDs (so you just need an adaptor) > Or, you can use the JTAG ISP I've made my own programmer based on Manfred Winterhoff's design. I'll use the JTAG, surely. > There are also Atmel ATF150xASL series, in PLCC, but lower > power than XC95xx. I'm used to buying from Schukat, and from the list of CPLDs they have, XC95xx is the best choice. Schukat only sells Lattice and Xilinx. (I've never tried with Farnell, don't like the site's organization) > Note that PLCC is now somewhat trailing-edge, and newest > families are TQFP only. PLCCs are the starting point, considering I make my PCBs at home. > WinCUPL is a small 21MB (even smaller as command line model only), If I don't get the Webpack... Thanks to everyone for the help!Article: 133029
aleksa wrote: PFC >> Always test your pin allocations BEFORE manufacturing the PCB ! >> The synthesis tool will tell you if you want to use an impossible pin mapping. > > > Why? Aren't all pins I/O? Not all pins are created equal. Global CLocks, Global OE, Global CLRs are typical, so those have obvious natural allocations. Then, if a design gets full, you can find some CPLD resource limits free placement of all I/O - so it is always a good idea to both fit First, and also read the Fitter .RPT files, to see the Logic usage, and how much head-room you have. Also feel free to trial intermediate nodes : sometimes having' them gives a smaller desigm, sometimes allowing the fitter to collapse them, can give a smaller design. (but still readable at the source level) -jgArticle: 133030
Hi- I'm trying to locate the data sheet for an old 1M x 1 Mitsubishi dram part: MSM41000BJ (70nS) An internet search is coming up empty. If you can help out it would be appreciated. Thanks JimArticle: 133031
On Jun 13, 5:46=A0pm, Eric Smith <e...@brouhaha.com> wrote: > Charles Xavier wrote: > > If anyone has attempted to download anything in the 8GB range, you'll > > find that well.. if you're missing enough parts of the file, the par2 > > recovery can be a painful, painful process taking up to three hours in > > some cases. > > The XBOX 360 doesn't play x.264 and all the good movies are in x.264. > > Converting from x.264 to h.264 could be done offboard on an FPGA > > I have a hard time believing that those are the "two most annoying problem= s > on usenet". =A0I've been using Usenet since 1984, and I've never personall= y > encountered either problem. > > I've never tried to download an 8GB file from Usenet, and don't have any > clue why anyone would want to do such a thing. =A0There are much better > ways to distributed 8GB files. =A0But if I *did* want to download an 8GB > file from Usenet, I can't imagine that waiting three hours for a > reconstruction of missing pieces would really bother me that much. > There's never been a single thing that I've needed from Usenet so > urgently that it couldn't have waited three more hours. > > I watch a fair number of movies, but I've never had any problem with > x.264. =A0It sounds like you just need better player software. =A0That has= > nothing to do with Usenet. > > Since it doesn't appear that there is any real problem here, it also > doesn't appear that there is any need for an FPGA-based "solution". Thank you for sharing. Let your next post be in contribution to the project. If it doesn't apply to you and you don't see the need, why even reply?Article: 133032
>> Try Verilog and VHDL and choose according to your taste. > > I've seen some examples of VHDL on www.jrok.com (ZX Spectrum with AT > keyb) > and I'm amazed how simple the source is! Then your brain is wired for hardware ;) good for you ! > >> Always test your pin allocations BEFORE manufacturing the PCB ! >> The synthesis tool will tell you if you want to use an impossible >> pin mapping. > > Why? Aren't all pins I/O? Not necessarily, also, some have special functions that you might want to use. Also, voltage and banks come into play. > PLCCs are the starting point, considering I make my PCBs at home. If you're in Euroland, could try Olimex, they are very cheap and I heard recommendations for them : http://olimex.com/pcb/index.htmlArticle: 133033
On Sat, 14 Jun 2008 08:32:31 -0400, Jim Flanagan wrote: >I'm trying to locate the data sheet for >an old 1M x 1 Mitsubishi dram part: > MSM41000BJ (70nS) If you can find a data sheet for ANY 1Mx1 DRAM of approximately the same generation, it should tell you all you need. Pinouts and timing diagrams were standardised by JEDEC. The only problem might be if you're trying to work out exactly what package or performance grade you would get for any given Mitsubishi part number. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 133034
Pat, I am learning Verilog as well, my guess is that you may not handle correcly NLP/FLP stuff, that's the reason the interface seems down. Take a look here: http://www.fpga4fun.com/10BASE-T0.html "Keeping the link alive Even if no packets are sent on a 10BASE-T cable, a pulse has to be sent periodically (called the "Normal Link Pulse" or "NLP"). It is used to keep the connection "alive". A pulse needs to be sent every 16ms or so. The NLP can also be replaced by a "Fast Link Pulse" (FLP) burst, during a process called "auto-negotiation". The FLP carries information about the capabilities of the sender, so that the hardware at both end of a cable can negotiate the link parameters, like the speed and the half/full duplex status." Giuseppe Marullo giuseppe.marullo.nospam@iname.comArticle: 133035
On Fri, 13 Jun 2008 15:39:06 -0700 (PDT), aleksa wrote: > > >I'm currently using GALs (16V8-18V8-22V10), >but my current board requires 4 GALs and >I would like to replace them with one CPLD >which would also replace 4 other general ICs. > >I've never had the guts to try CPLD because I thought >they were complicated to learn, hard to solder and >most of all, impossible to programm without some $$$. > >Now I think different, but am unsure... > If you have $50 to experiment the Digilent kit includes a simple JTag cable and a nice board with two CLPD devices. An XC9500XL and a Coolrunner II. It operates on two AA Batteries or an optional wall-wart. (Or your own bench supply) The ISE CD is includes as well as a reference VHDL design with a simple counter and button de-bounce ckt. You can download the design and other info about the board at the link below. >I've choosen xilinx's XC95-36-72-108 to work with. > >I've read some examples of VHDL and I think it suits me. >Non-SMD PLCC socket will make it easy to solder. If you like I believe you can do your design in schematic form and in the case of a small design this may be all you need. The built-in ISE tools have core builders for many functions with a wizard-like menu to build more complex logic blocks. If you are just starting you may want to consider Verilog over VHDL. (seems to be more common in the market today) The nice thing is you get the instant gratification seeing your design work (not waiting for a asic build or board design) and you can make mods and improvements quickly. (Just re-program the chip) > >Now, programming.. > >Is it true that all I need is a FREE Webpack software >and a simple JTAG cable??? > >Will the Webpack only produce the fusemap or does >it also contain the software to actually burn the chip? >If the burn software is not contained in the Webpack- >where do I get it from? Or that is where the $$$ comes in? The ISE package includes the "impact" software to load/erase/re-load the device. This can also be run from the command line (and they support Linux) You can download the lab-pack that just has the impact part of the toolset if you need just that piece (ie in the lab where you don't want to install the full design system). This is all free for the CPLD's and the smaller FPGA's > >Current version of Webpack is huge for my modem (2.25Gb) >but maybe I'll get the version 7.1i - what do you guys >think of that version with XC95-36-72-108 in mind? > 7.1 should be fine for the CPLD family. Make sure you update with the latest service pack. >The last question (for now, sure) is: >how are CPLDs programmed, with JTAG or something else? > >Everybody says that it uses JTAG, but I've found a PDF >that says different: google for >"XILINX PROGRAMMER QUALIFICATION SPECIFICATION" > >That PDF is using address bus(A0-A13), data bus(D0-D3), >and several signals (TSTEN, PGMEN, VFYEN, TS0-TS3, AD_STB) >to burn the XC9500 family. JTAG seems the easiest with the toolset. With JTAG you can target any one device in the chain (ie if you have multiple CPLD's or a mix of JTAG compatible parts on your board) through one connection. Some of the newer devices can also be programmed with a SPI (serial interface.) (ie Spartan-AN that now has non-volitial flash load) I think I saw the option on some of the Coolrunner parts but I cannot recall. I have also done bit banging on the FPGA parts (Done,CLK,D0in,PROG,and one more I can't recall INIT maybe) through the load pins. I have not tried the procedure you showed above on a CPLD. CPLD Design/Development kit from Digilent: (They build many kits for Xilinx parts) http://www.digilentinc.com/Products/Detail.cfm?Prod=XC2XL&Nav1=Produc Have fun, BartArticle: 133036
Charles Xavier wrote: > On Jun 13, 5:46 pm, Eric Smith <e...@brouhaha.com> wrote: >> Charles Xavier wrote: >>> If anyone has attempted to download anything in the 8GB range, >>> you'll find that well.. if you're missing enough parts of the file, >>> the par2 recovery can be a painful, painful process taking up to >>> three hours in some cases. >>> The XBOX 360 doesn't play x.264 and all the good movies are in >>> x.264. Converting from x.264 to h.264 could be done offboard on an >>> FPGA >> >> I have a hard time believing that those are the "two most annoying >> problems on usenet". I've been using Usenet since 1984, and I've >> never personally encountered either problem. >> >> >> Since it doesn't appear that there is any real problem here, it also >> doesn't appear that there is any need for an FPGA-based "solution". > > Thank you for sharing. Let your next post be in contribution to the > project. > > If it doesn't apply to you and you don't see the need, why even reply? Hi Charles, Maybe to share the benefit of his experience to help you avoid wasting your time on a solution without a problem? Good luck, Syms.Article: 133037
Hi. I've spent hours trying to find a simple example/turorial of a microblaze imorted into system generater for simulation. All i find is HW co-sim examples. Is there a tutorial out there that does the following: Microblaze --> Shared mem --> Scope in simulink. I would be very happy if anyone could supply even a link. The lack of replies in numerous other forums is making me worried if this can even be done... Did anyone succeed on this?Article: 133038
Hello, I am fairly new to FPGA design and have a Xilinx Spartan 3 board, that has a 50 pin IO bank. When I load up a design, and route signals to different parts of this IO region, some of the signals are weakly coupled together. In specific, although they are not the same signal, they only have 50 ohms of resistance between them and are coupling somehow. How do I fix this?Article: 133039
On Jun 14, 7:44=A0pm, WyndyPickle <WyndyPic...@gmail.com> wrote: > Hello, > > I am fairly new to FPGA design and have a Xilinx Spartan 3 board, that > has a 50 pin IO bank. When I load up a design, and route signals to > different parts of this IO region, some of the signals are weakly > coupled together. In specific, although they are not the same signal, > they only have 50 ohms of resistance between them and are coupling > somehow. How do I fix this? Is this an output affecting another output, or affecting an input? How strong is the effect (what is the voltage ratio between the driving signal and the affected signal)? Have you observed the common Vcco and common ground. Are there decoupling problems? How did you measure the 50 Ohms? Lots of questions... Peter Alfke, Xilinx ApplicationsArticle: 133040
WyndyPickle wrote: > Hello, > > I am fairly new to FPGA design and have a Xilinx Spartan 3 board, that > has a 50 pin IO bank. When I load up a design, and route signals to > different parts of this IO region, some of the signals are weakly > coupled together. In specific, although they are not the same signal, > they only have 50 ohms of resistance between them and are coupling > somehow. How do I fix this? I would not call 50 Ohms is 'weakly coupled'. That is of the order of a termination resistance, so check there are none on the PCB, and none enabled inside the FPGA. If you remove power, does it still measure 50 ohms. -jgArticle: 133041
Hi, I want to use Xilinx DA FIR logic core (Ver 9.0) to generate many FIR blocks. The wordwidth of Dout is defined as the following: DOUT[R-1:0]: FILTER OUTPUT SAMPLE R-bit-wide output sample bus for the FIR, half-band and interpolated filters. R depends on the filter parameters (data precision, coefficient precision, number of taps and coefficient optimization selection) and is always supplied as a full-precision output port to avoid any potential for overflow. The width of DOUT(R) is out of my control for the many different FIR coefficient sets. In my project, I would like to have the same output wordwidth of the many DA FIR blocks. Does anyone have some good idea to reach that goal? Thanks a lot.Article: 133042
I've seen messages from regular posters saying that they run Modelsim/XE Starter Edition in Linux. This evidently works for the node-locked 'disk-id' based licenses. But if you have a full license, on a USB-dongle or other physical key, will Modelsim/XE still work under WINE?Article: 133043
On Jun 14, 12:39=A0pm, "Symon" <symon_bre...@hotmail.com> wrote: > Charles Xavier wrote: > > On Jun 13, 5:46 pm, Eric Smith <e...@brouhaha.com> wrote: > >> Charles Xavier wrote: > >>> If anyone has attempted to download anything in the 8GB range, > >>> you'll find that well.. if you're missing enough parts of the file, > >>> the par2 recovery can be a painful, painful process taking up to > >>> three hours in some cases. > >>> The XBOX 360 doesn't play x.264 and all the good movies are in > >>> x.264. Converting from x.264 to h.264 could be done offboard on an > >>> FPGA > > >> I have a hard time believing that those are the "two most annoying > >> problems on usenet". I've been using Usenet since 1984, and I've > >> never personally encountered either problem. > > >> Since it doesn't appear that there is any real problem here, it also > >> doesn't appear that there is any need for an FPGA-based "solution". > > > Thank you for sharing. Let your next post be in contribution to the > > project. > > > If it doesn't apply to you and you don't see the need, why even reply? > > Hi Charles, > Maybe to share the benefit of his experience to help you avoid wasting you= r > time on a solution without a problem? > Good luck, Syms. Engineers can often be of a single track mind, so let me restate. This is a problem that I am having. I could certainly get a faster computer, or try to finesse the algorithms for the decoding, but I want to learn about this specific algorithm implementation on an FPGA, so I'm using the FPGA to solve this problem (that is a problem for me). To me, this is a practical solution and an excellent gateway for myself and others who want to get into FPGA-based hardware acceleration of software algorithms. You give me a better way that solves a practical problem for _me_ and I'll take it. This reminds of the idiots at In-N-Out Burger who created the drive- through fast food restaurant (they claim). It doesn't affect the geriatric who only wants to eat inside because they can't imagine driving while eating. But apparently it turned out to be a good idea. Responding to this type of feedback is the real waste of time.Article: 133044
On 2008-06-11, Charles Xavier <skelotar@gmail.com> wrote: > The XBOX 360 doesn't play x.264 and all the good movies are in x.264. > Converting from x.264 to h.264 could be done offboard on an FPGA > because it takes for-ever to complete on my system (8 hours). This > should have the same premise as the previous issue, minus using a x. > 264 decoding core and possibly directly converting it to h.264 or > doing a decompression-recompression.. I'm not sure what the problem with x.264 is, but lets just say that it is far from trivial to write a H.264 decoder/encoder. The decoder is especially tricky as you need to be able to parse all parts of the standard whereas you can select only the parts you care about for the encoder. If you are an expert on video codecs and a newcomer to FPGAs, this would probably be a quite ambitiouis project to start with. If you are not an expert on video codecs, you will have to spend a lot of time to understand H.264 before you can even get started on the FPGA parts. This is written from personal experience by the way, I have written a grayscale H.264 decoder in C to get an understanding of how the standard works. Lets just say that it took way more time than I wanted to... In summary: I don't recommend a H.264 codec as a first FPGA project. The Reed-Solomon application seems like a much more reasonable project. You will still have a lot of things to figure out like how you are going to communicate with your FPGA board, but the problem itself is much more limited. /AndreasArticle: 133045
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Content-Type: text/html;
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<HTML><HEAD>
<META http-equiv=3DContent-Type content=3D"text/html; =
charset=3Diso-8859-1">
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<STYLE></STYLE>
</HEAD>
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Article: 133046Hai, I am facing problem while synthesis of Fixed point data type.I cannot change the synthesis tool.Is there any method which can convert fixed point to integer before hand and perform computation and convert back to fixed point without affecting the precision.? In my FIR filter design i will sample the input and perform computation,produce result with control signal and then i will sample the next data..ultimately i will waiting for the o/p control signal before sampling the data..now my question is how this logic will be implemented as hardware..do i need to store my input samples in ROM or i should depend on the software to do this? pls clarify. regards, faza On Jun 14, 7:46=A0am, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: > faza wrote: > > Can anyone explain how FIR filter implemented in real time > > I would vote for systolic array. > > > application....Wat is the role of software supporting the hardware??? > > Initialize the coefficients, and start everything going. > > -- glenArticle: 133047
On Jun 13, 7:48 pm, Jim Granville <no.s...@designtools.maps.co.nz> wrote: > Uwe Bonnes wrote: > > Jim Granville <no.s...@designtools.maps.co.nz> wrote: > > >>aleksa wrote: > >>>I've choosen xilinx's XC95-36-72-108 to work with. > > >>There are also Atmel ATF150xASL series, in PLCC, but lower > >>power than XC95xx. > > >>Note that PLCC is now somewhat trailing-edge, and newest > >>families are TQFP only. > > > Note also that XC95xx has smaller logic operation capabilities against > > XC95xxXL or XC95xxXV and has higher prices. > > The XC95xxXV (2.5V device) states this : > > Xilinx Data Sheet: > [Note: This product is being discontinued. You cannot > order parts after May 14, 2008. Xilinx recommends replacing > XC9536XV devices with equivalent XC9536XL devices > in all designs as soon as possible. Recommended replacements > are pin compatible, however require a VCC change to > 3.3V, and a recompile of the design file. In addition, there is > no 1.8V I/O support.] > > - seems 2.5V never hit critcal mass, and thus is EOL.... > > As Uwe mentions, the XC95xxXL is MUCH cheaper than the XC95xx, BUT > the XL is a 3.3V VccIO device. > > The ATF1502ASL is 5V Vcc capable - that may matter, when > replacing SPLDs. > > Some of the new Lattice devices mention 5V tolerant IO (when > VccIO=3.3V), but they are not in PLCC packages, and still need > multiple Supplies. > > -jg The XC95xxXL CPLDs do indeed use 3.3v VCC, but their I/Os are 5v tolerant. However, an output's HI is 3.3v, not 5v. If you are using 5v TTL (i.e. 74LSxx) or 5v CMOS with TTL input thresholds (i.e. 74ACTxx), then you can use a XC95xxXL CPLD. Otherwise you'll need a 5v device (XC95xx). I've used both 5v devices (XC9536 & XC95108) and 3.3v devices (XC9572XL), with both 74LS and 74ACT chips. HTH -Dave PollumArticle: 133048
On Wed, 11 Jun 2008 06:50:52 -0700 (PDT), Charles Xavier <skelotar@gmail.com> wrote: >As you all know, downloading files from usenet leaves you with two >sets of files.. The rar files from what you're downloading and the >par2 files for incomplete file repair. > >If anyone has attempted to download anything in the 8GB range, you'll >find that well.. if you're missing enough parts of the file, the par2 >recovery can be a painful, painful process taking up to three hours in >some cases. > >I'm sick of it. > >So, here's the idea. Use a FPGA to do the reed-solomon decoding to >accelerate the PAR2 repair/recovery process. The system should utilize >a USB connection to pipe data directly from the disk to the FPGA that >will do the offboard processing of the data. The data transfer should >be controlled by an application on the computer. > >Second Problem.. > >The XBOX 360 doesn't play x.264 and all the good movies are in x.264. >Converting from x.264 to h.264 could be done offboard on an FPGA >because it takes for-ever to complete on my system (8 hours). This >should have the same premise as the previous issue, minus using a x. >264 decoding core and possibly directly converting it to h.264 or >doing a decompression-recompression.. > >SPECS: The development system i'm using is the XILINX ML-505 board >with the Virtex 5 chip. This is a open-source project being done for >fun and learning btw. > >Suggestions / Comments / Complaints? Just program one of these: http://www.eetimes.com/news/latest/showArticle.jhtml;jsessionid=YBF0E0YIMESH2QSNDLSCKHA?articleID=208404063 240 cores, teraflop. JohnArticle: 133049
"faza" <fazulu.vlsi@gmail.com> wrote in message news:53fad5d8-9989-4089-82be-cf57588c9b34@u36g2000prf.googlegroups.com... Hai, I am facing problem while synthesis of Fixed point data type.I cannot change the synthesis tool.Is there any method which can convert fixed point to integer before hand and perform computation and convert back to fixed point without affecting the precision.? In my FIR filter design i will sample the input and perform computation,produce result with control signal and then i will sample the next data..ultimately i will waiting for the o/p control signal before sampling the data..now my question is how this logic will be implemented as hardware..do i need to store my input samples in ROM or i should depend on the software to do this? pls clarify. regards, faz Dude .. give us some background .. Are you a student? What year? Is this a project or an assignment? Mike
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