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Dear All I working on a custom based board where the system is running with xilinx 8.2i and Spartan 3E FPGA. Now we are in process of migrating from version 8.2i to 9.2i. Weare facing problem in debugging the system with 9.2i version. There is a abnormal behaviour while debugging. I would like to know the reason for this abnormal behaviour?? Experts please help me in solving this problem.. thanks a lot in advance. regds karthickArticle: 133301
"techG" <giuliopulina@gmail.com> wrote in message news:b947faa4-1d75-455a-9062-f6f8bc299625@a70g2000hsh.googlegroups.com... > Hi all, > I have a camera and a Virtex-5 FPGA, and i would like to store frames > in FPGA Block Ram. > In my design (that worked with Spartan-3E) i need to double camera > clock frequency, in order to get all data, because camera send data on > both clock edges. > > Giulio Hi Giulio, Does the camera generate the clock or does the FPGA make a clock to drive the camera? Thanks, Syms.Article: 133302
"karthick" <karthick.kr@gmail.com> wrote in message news:5d38b9f2-4fd7-44d2-9a87-5a9c6a6a2cd7@c19g2000prf.googlegroups.com... > Dear All > > I working on a custom based board where the system is running with > xilinx 8.2i and Spartan 3E FPGA. > > Now we are in process of migrating from version 8.2i to 9.2i. > > Weare facing problem in debugging the system with 9.2i version. There > is a abnormal behaviour while debugging. > > I would like to know the reason for this abnormal behaviour?? > > Experts please help me in solving this problem.. > > thanks a lot in advance. > > regds > karthick Dear kar thick, There is no problem faced by Weare. Clearly, the abnormal behaviour was in 8.2i. The behaviour you're seeing now with 9.2i is normal. You should be delighted. HTH., Syms.Article: 133303
Cross postingArticle: 133304
How do we decide which simulation should we go with for a project? I understand in general VCS is cycle-based simulator and Modelsim is Event-based simulator. But even in VCS when we compile VHDL design there is an option to choose the simulation type "Cycle-based" or "Event-based". Best regards, MuthuArticle: 133305
> The output is actually 4 differential signals (one for each column) > meaning I will need four ADCs (all four video outputs signals come out= > simultaneously). The resolution that I want is 16 bits. Sure, you want 16 bits, but what is the signal to noise ratio that the = = sensor actually delivers ? If your sensor only has say, 10 bits of = precision, then your expensive 16 bits ADCs are wasted. > Now, that means I have four parallel channels of 16 bits coming into > the FPGA every 25 ns that I need to store somewhere. The total data > per frame is: > (320 x 256) x 16 bits =3D 1310720 bits/frame OR 163840 Bytes/frame or > 160 KBytes / frame. > > Do you think I can store that much within a xilinx FPGA. I am trying > to do 30 frames per seccond which means I have roughly 33 ms per frame= > but using 40 MHz clock each frame can be read out in 512 microseconds > with a whole lot of dead time after each frame (unless I can run the > sensor at a slower pixel clock). Well your pixel clock is going to depend on the bandwidth and settling = = time of the analog path. Your settling time requirements depend on the = number of bits you actually want. If you want more precision it always = takes longer to settle. Don't forget this in the design of your analog = path. > The idea is to transfer data over the pci bus to the computer and I > cant go over 133 Meg transfers per second. Since I am reading 4 actually it's 133 megabytes/s, but 33 megatransfers/s since one transfe= r = is one 32 bit word ie 4 bytes > channels @ 40 MHz that works out to be 160 Mbits per second so not > possible to transfer the data on fly over the bus (unless I am > misunderstanding something). Is there a way to transfer data on the > fly over the pci bus other than slowing the pixel clock ? you can either use a fast pixel clock and a large FIFO, or a slower pix= el = clock and no FIFO. But if you only want 30 fps, which is quite small, and a small resoluti= on = of 320x240, this is only 2.3 million pixels per second. So you can use a= = pixel clock of (say) 1 MHz, with outputs 4 pixels every microsecond as y= ou = said, and then a 4-input muxed ADC, instead of 4 ADCs (much cheaper) = taking 4 million samples/s. In this case you are twice as fast as = necessary which will allow you to use up to half the frame time as = exposure time on your sensor. If you need longer exposures you will need= a = faster pixel clock to allow more time for exposure and less time for dat= a = handling. Now if you want to make high-speed recording (like 300 fps) to take = videos of bullets exploding tomatoes you'll need to use the fastest pixe= l = clock you can get and also very powerful lights. But if you only need a = = slow 30 fps you don't need to use expensive analog parts and ADCs. > Or how can I effeciently transfer the data data over the bus (even if > I have to store and then use a slower clock to transfer the data out).= To be efficient you need burst transfers so you will always need some = form of FIFO somewhere, and DMA. Note that since your throughput is quite small you could use USB instea= d = of PCI which would allow more freedom in locating the camera further fro= m = the computer itself. What do you want to do with this camera ?Article: 133306
> be used, slowing down the throughput. Target is a database searching of > 262144 elements with 16 bit each in maximum 220 ms. If you are searching 16 bit datums then your search space is limited to 65536 different datums. Why would you want to store more than this ? A hashtable comes to mind, for instance. What is your searching algorithm ? Why is it that complex ? Can you post a description ? Taking well-designed software as example, your 220 ms time budget is enough for Postgresql to perform about 3000-5000 simple SQL queries returning 1 row with btree index lookup on a table with millions of rows including network overhead (as long as it doesn't need to hit the disk), in 220 ms Xapian can make multiple full text phrase searches with ranking on a multi gigabyte text dataset. These are per core of course. So, I suggest reviewing your search algorithm ;)Article: 133307
> my real concern is the pc side... will setting the ethertype field to > tcp/ip work or is it necessary to use lwIP? lwip will do all the work for you but of course it will be slower than custom code. Consequences of that depend on your bandwidth. Anyway, if you don't want a full IP stack, you can use UDP (which is pretty easy). You need to build a packet with corect Ethernet, IP, and UDP headers, and then your data. You can reuse the header for the next packets. Ethernet header needs (of course) to have the correct fields including addresses, protocol type, etc. IP checksum (which only applies to the header) needs to be correct. You can compute the UDP checksum or simply set it to 0, in which case the PC will ignore the checksum field. If the checksum is not 0 and it is wrong, the PC will drop the packet. If you are on a LAN, Ethernet CRC will take care of error checking anyway so the UDP checksum is not needed. Just set it to 0. Computing this checksum is the most time consuming operation in UDP so being able to ignore it is nice when you have a slow CPU like uBlaze. Check Wikipedta for a description of the headers. It's really simple. You can also use a packet sniffer like ethereal to grok the headers and debug your code.Article: 133308
If I understand correctly , You are observing the abnormal behaviour with 8.2i. Even though we are using 9.2i we are using the older version of Microblaze (4.0) and other pheripherals. Will this cause any problems?? regds karthickArticle: 133309
On Jun 24, 6:19 am, muthu...@gmail.com wrote: > How do we decide which simulation should we go with for a project? Money Features that you feel are important.Article: 133310
Camera generate its own clock I'm successfully using IDDR flip-flops, but their simulation behavior is a bit different from what described in Virtex-5 user guide (or I'm making some mistakes).. however, i prefer this solution to the "clock adjustment" solution, because I found it simpler (and I'm not a very expert designer :D ). Thank you all again! On Jun 24, 10:35 am, "Symon" <symon_bre...@hotmail.com> wrote: > "techG" <giuliopul...@gmail.com> wrote in message > > news:b947faa4-1d75-455a-9062-f6f8bc299625@a70g2000hsh.googlegroups.com... > > > Hi all, > > I have a camera and a Virtex-5 FPGA, and i would like to store frames > > in FPGA Block Ram. > > In my design (that worked with Spartan-3E) i need to double camera > > clock frequency, in order to get all data, because camera send data on > > both clock edges. > > > Giulio > > Hi Giulio, > Does the camera generate the clock or does the FPGA make a clock to drive > the camera? > Thanks, Syms.Article: 133311
On Jun 23, 1:46 pm, "vikashrun...@gmail.com" <vikashrun...@gmail.com> wrote: > Hi, > > There is a new FPGA Linked in Group. > > Joining will allow you to find and contact other FPGA, CPLD members on > LinkedIn. The goal of this group is to help members: > > -> Reach other members of FPGA & CPLD community > -> Accelerate careers/business through referrals from FPGA Group > members > -> Know more than a name =96 view rich professional profiles from fellow > FPGA Group members > Here=92s the link to join: > > http://www.linkedin.com/e/gis/54049/5B3F2217B20B > > Hope to see you in the group, > > =97 Vikram How is your group different from comp.arch.fpga ? -Dave PollumArticle: 133312
karthick wrote: > Dear All > > I working on a custom based board where the system is running with > xilinx 8.2i and Spartan 3E FPGA. > > Now we are in process of migrating from version 8.2i to 9.2i. > > Weare facing problem in debugging the system with 9.2i version. There > is a abnormal behaviour while debugging. > > I would like to know the reason for this abnormal behaviour?? It is difficult to get anyone to help when the only description of the problem is 'abnormal'. Please tell us what result you are expecting, what result you are getting, why this result is wrong and what steps you have already taken to fix the problem. At that point, people can decide if they have anything to contribute. --- Joe Samson Pixel VelocityArticle: 133313
On Jun 24, 4:21=A0am, karthick <karthick...@gmail.com> wrote: > Dear All > > Weare facing problem in debugging the system with 9.2i version. There > is a abnormal behaviour while debugging. > > I would like to know the reason for this abnormal behaviour?? > > Experts please help me in solving this problem.. > You have a design error. KJArticle: 133314
karthick wrote: > If I understand correctly... You don't. Symon was making a joke. Your description is too vague for anyone to help you. -JeffArticle: 133315
On Tue, 24 Jun 2008 01:21:21 -0700, karthick wrote: > Dear All > > I working on a custom based board where the system is running with > xilinx 8.2i and Spartan 3E FPGA. > > Now we are in process of migrating from version 8.2i to 9.2i. > > Weare facing problem in debugging the system with 9.2i version. There is > a abnormal behaviour while debugging. > > I would like to know the reason for this abnormal behaviour?? > > Experts please help me in solving this problem.. > > thanks a lot in advance. > > regds > karthick Dr. Frederick Frankenstein: Igor, would you mind telling me whose brain I did put in? Igor: And you won't be angry? Dr. Frederick Frankenstein: I will NOT be angry. Igor: Abby someone. Dr. Frederick Frankenstein: Abby someone. Abby who? Igor: Abby Normal. Dr. Frederick Frankenstein: Abby Normal? Igor: I'm almost sure that was the name. Dr. Frederick Frankenstein: Are you saying that I put an abnormal brain into a seven and a half foot long, fifty-four inch wide GORILLA? [shakes and grabs him] Dr. Frederick Frankenstein: IS THAT WHAT YOU'RE TELLING ME?Article: 133316
Hi! I have the following problem on a Virtex5 system: I use an interrupt controller, that is connected to the PPC interrupt port. The interrupt controller and the PPC interrupt handler are initialized but working ONLY for the very first interrupt. After the first interrupt occured the processor hangs at address 0x60, which is in the interrupt vector table: 00000060 <IVOR6>: 60: 7c 70 43 a6 mtsprg 0,r3 64: 38 60 00 06 li r3,6 68: 7c 60 43 a6 mtspr 256,r3 6c: 48 00 00 94 b 100 <non_critical_irq> Did I miss something about the initialization? I used the source code provided with the examples of the xps_intc. MatthiasArticle: 133317
Dave, LinkedIn is an interesting community of sorts: each person may place their profile there, ostensibly so they can "network" with others and either get a better job, or get work (if they consult). It is also an insurance policy of sorts if you find yourself in a RIF... I have been "invited" to join in for one of my daughters, and others I know (in all sorts of different fields, completely unrelated to my field). Since I have no need to advertise myself (just google "Austin Lesea"), I find it something next to useless (for me). Being of a totally different generation (the last of the baby boomers), I am not all that excited about any on-line community (I prefer real community, with a good Cabernet, or Pinot Noir). None the less, this is a sort of 'FaceBook' for people with a professional job (or looking for one). Just like any other on-line experience, we will see if it is successful or not. My guess? With the price of gas, meeting on-line gets very attractive. Working from home once a week is now something the government is thinking of legislating...(more laws=bad government, I'm afraid. Let the market decide is my view). Although, I would easily drive 40 miles if a glass of good wine is involved. More if the people are my friends, too. On a completely different topic, this weekend will be the 44th year of the "Chews Ridge Gang" for ARRL Field Day...wish us luck -- we will need it as most of Northern California is on fire, and still burning (so we may not have access to Chews). http://www.pdarrl.org/scvsec/wikka.php?wakka=FDSites And, upon reflection, my "on the air" community is a lot more fun than the Internet. AustinArticle: 133318
Dear everybody, we have experienced a problem with our boards. We are using an Altera Cyclone device with NIOS II processor interfaced with a static RAM and a FLASH memory. The R/W access time for RAM has been set up to 60ns (the RAM datasheet reports 55ns) and the R/W access time for FLASH has been set up to 80ns (the FLASH datasheet reports 70ns). Up to 45=B0C the system works well. Over this temperature the processor crashes. Enlarging the R/W access times the system works well up to 85=B0C. Can you explain me how the signal timing change in function of temperature ? Is it possible to make something like a compensation to prevent this issue ? Can you give me a link where get information about this issue ? Best Regards /AlessandroArticle: 133319
Hello Austin,
Thanks for responding.
This is for a Virtex 5 LX110t device on a Avnet PCIE board AES-XLX-
V5LXT-PCIE110-G. I am trying a near-end PMA serial-loopback just
because the xaui core came with this default setting. For now I have
been following the instructions provided in UG196 about loopback modes
(chapter 9 in UG 196). Mainly, my task here is to control the
loopback externally (through the device driver). The verilog code that
controls the loopback as it came with xaui v7.2 is as follows.
assign loopback_int = mgt_loopback ? 3'b010 : 3'b000;
mgt_loopback is an output from the xaui core (the 'blackbox'). The
near-end PMA loopback("010") is enabled if mgt_loopback is high. The
mgt_loopback can be set high through the DRP or the MDIO interface as
suggested in the user-guides (UG196 and UG150). My issue specifically
is to know how these DRP ports can be configured in order to setup an
internal loopback and control it through my device driver.
I would be happy to know your suggestions on this.
Thanks,
Chethan
On Jun 23, 6:08 pm, austin <aus...@xilinx.com> wrote:
> Chetan,
>
> What device family? V2P, V4, or V5?
>
> Also, there is a serial loopback, and a parallel loopback. And, if that
> is not enough, are we talking near end, or far end which is looping back?
>
> Generally, a parallel or digital loopback checks the function and the
> logic (step one of any testing). Then a near end serial loopback will
> check the analog side. Often the serial loopback must have a good
> transmit termination, as reflections may cause errors. In this sense,
> looping back with nothing connected may fail due to reflections (get out
> the scope). Following that, looping back the far end on its parallel
> side will successfully check the analog and digital of the near end, and
> the analog looped back at the far end. Then the only thing not checked
> is synchronization (far end clock vs near end clock). For testing the
> clocking, you need a mode at the far end to use either the local clock,
> or to re-use the received clock. If you use the far end local clock,
> then you also need a loopback at the far end after the receive FIFO,
> before the transmit FIFO so that all of the design is tested.]
>
> Loopback testing can be a major task:
>
> http://www.juniper.net/techpubs/software/junos/junos76/swconfig76-net...
>
> http://www.credence.com/technical-library/open-docs/test-trends_loopb...
>
> Austin
Article: 133320
Chetan,
Have you read:
http://www.xilinx.com/support/documentation/user_guides/ug191.pdf
chapter 6?
and
http://www.xilinx.com/support/documentation/user_guides/ug196.pdf
page 91...
Austin
explore wrote:
> Hello Austin,
> Thanks for responding.
>
> This is for a Virtex 5 LX110t device on a Avnet PCIE board AES-XLX-
> V5LXT-PCIE110-G. I am trying a near-end PMA serial-loopback just
> because the xaui core came with this default setting. For now I have
> been following the instructions provided in UG196 about loopback modes
> (chapter 9 in UG 196). Mainly, my task here is to control the
> loopback externally (through the device driver). The verilog code that
> controls the loopback as it came with xaui v7.2 is as follows.
>
> assign loopback_int = mgt_loopback ? 3'b010 : 3'b000;
>
> mgt_loopback is an output from the xaui core (the 'blackbox'). The
> near-end PMA loopback("010") is enabled if mgt_loopback is high. The
> mgt_loopback can be set high through the DRP or the MDIO interface as
> suggested in the user-guides (UG196 and UG150). My issue specifically
> is to know how these DRP ports can be configured in order to setup an
> internal loopback and control it through my device driver.
>
> I would be happy to know your suggestions on this.
>
> Thanks,
> Chethan
>
>
>
>
>
> On Jun 23, 6:08 pm, austin <aus...@xilinx.com> wrote:
>> Chetan,
>>
>> What device family? V2P, V4, or V5?
>>
>> Also, there is a serial loopback, and a parallel loopback. And, if that
>> is not enough, are we talking near end, or far end which is looping back?
>>
>> Generally, a parallel or digital loopback checks the function and the
>> logic (step one of any testing). Then a near end serial loopback will
>> check the analog side. Often the serial loopback must have a good
>> transmit termination, as reflections may cause errors. In this sense,
>> looping back with nothing connected may fail due to reflections (get out
>> the scope). Following that, looping back the far end on its parallel
>> side will successfully check the analog and digital of the near end, and
>> the analog looped back at the far end. Then the only thing not checked
>> is synchronization (far end clock vs near end clock). For testing the
>> clocking, you need a mode at the far end to use either the local clock,
>> or to re-use the received clock. If you use the far end local clock,
>> then you also need a loopback at the far end after the receive FIFO,
>> before the transmit FIFO so that all of the design is tested.]
>>
>> Loopback testing can be a major task:
>>
>> http://www.juniper.net/techpubs/software/junos/junos76/swconfig76-net...
>>
>> http://www.credence.com/technical-library/open-docs/test-trends_loopb...
>>
>> Austin
>
Article: 133321MikeWhy wrote: (snip on aliasing and imaging) >> http://www.nikonians.org/nikon/d200/nikon_d200_review_2.html#aa95cf09 > Sure, I've clicked the shutter a few times. I was even around when Sigma > splatted in the market with the Foveon sensor. All the same, Bayer > aliasing isn't related to Nyquist aliasing and sampling frequency. The > OP needn't concern himself with Nyquist considerations. Yes? Bayer aliasing and sampling (spatial) frequency are exactly related to Nyquist aliasing, however the OP was asking about the time domain signal coming out of a CCD array. That signal has already been sampled and Nyquist should not be a consideration. (Unless one is sampling the CCD output at a lower frequency.) The OP didn't explain the optical system at all, so I can't say if that is a concern or not. -- glenArticle: 133322
I am currently working on a project that takes the same high level behavioral model and ultimately targets both an Altera and a Xilinx chip. About 95% of the code can by synthesized for either Altera or Xilinx. Meaning the bulk of the code can be generic without specifying architecture specific primitives. However, the last 5% is presenting some configuration management issues. For instance, I have to instantiate a DCM for Xilinx and a PLL for Altera. Both primitives have similar high level functionality. Considering this I would like to be able to simply exchange a DCM for a PLL when synthesizing between the two architectures. However there are enough differences in port definitions that this idea is not as easy as it would first seem to be. My question to the community is, does anyone have best practices techniques that address the multiple FPGA target problem? Is there a good way to write your code to encourage multiple FPGA development? Also, is there a good way to construct your directory structure within a code repository?Article: 133323
-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 General Schvantzkopf wrote: | On Fri, 20 Jun 2008 10:16:22 -0700, Stephen Williams wrote: | | General Schvantzkopf wrote: | | I haven't been able to get Icarus to work, it's not complete enough to | | run any of our testbenches. We aren't doing anything fancy, in fact | all | of our code is strict Verilog 95 it's not even 2001. | | Current snapshots are much improved, and bug reports are welcomed. | | I used the version that was in the F9 repositories which is 0.9, are the | current snapshots significantly better than that one? There is no 0.9 release, but 0.9.0.xxxx is the numbering scheme for the snapshots that are leading up to 0.9. Even at that, it depends on the actual version, as recently Icarus Verilog has been improving rapidly. Bug reports will help us pin down what your actual problems are and get them fixed up. There shouldn't be much left of the 1995 LRM that isn't supported by now. - -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep." -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.4-svn0 (GNU/Linux) Comment: Using GnuPG with SUSE - http://enigmail.mozdev.org iD8DBQFIYVm4rPt1Sc2b3ikRAlLcAKDcFVE0+WNh4v5a7r+aKkEatIEQ2ACeJ99c BK91SsjnmrS0bChcMJpXfhc= =pdGZ -----END PGP SIGNATURE-----Article: 133324
Try to make an architecturally independent wrapper that has internal implementations for each target device. As far as directory structure, I like the method commonly used for embedded OSes of making a clear division between device independent and device dependent code. The rest of the structure depends heavily on the complexity and structure of the project but I tend to create a folder for each high-level function. ---Matthew Hicks > I am currently working on a project that takes the same high level > behavioral model and ultimately targets both an Altera and a Xilinx > chip. About 95% of the code can by synthesized for either Altera or > Xilinx. Meaning the bulk of the code can be generic without > specifying architecture specific primitives. However, the last 5% is > presenting some configuration management issues. For instance, I have > to instantiate a DCM for Xilinx and a PLL for Altera. Both > primitives have similar high level functionality. Considering this I > would like to be able to simply exchange a DCM for a PLL when > synthesizing between the two architectures. However there are enough > differences in port definitions that this idea is not as easy as it > would first seem to be. My question to the community is, does anyone > have best practices techniques that address the multiple FPGA target > problem? Is there a good way to write your code to encourage multiple > FPGA development? Also, is there a good way to construct your > directory structure within a code repository? >
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