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"Norman Bollmann" <wirdnichtgelesen@gmx.net> wrote: >Hello, > > > >I've been searching the internet for days now and still I'm not sure about >what I am trying to do. Okay now, I've got a software implementation in >ANSI-C for a complex database searching. The database is a proprietary >format where I am saving data, which has to be given as a result, depending >on the input data. Problem is, the software implementation is far to slow. > > > >Now I am looking for alternative ways for a faster implementation and came >across the idea to implement the whole database searching as electronic >circuit in an FPGA. The database is of course far too big to save it inside >an FPGA, e.g. the BlockRAMs of a Spartan3. Therefore external memory has to >be used, slowing down the throughput. Target is a database searching of >262144 elements with 16 bit each in maximum 220 ms. I suggest you optimize your software algorithm. 262144 elements fits in the cache of any modern PC CPU. You'll have a hard time creating an FPGA design that will perform better. -- Programmeren in Almere? E-mail naar nico@nctdevpuntnl (punt=.)Article: 133351
On Jun 25, 7:04 am, muthu...@gmail.com wrote: > Friends, > > I have been using the Xilinx tools ISE, EDK in Windows environment. > But now planning to use Linux PC for running ISE and EDK. I am > curious, which platform (Windows or Linux) is good for Xilinx tools? > I am planning to use the ISE and EDK in GUI mode, not command line > mode. > > Linux version would be Red hat Enterprise WS version 4.0 (64-bit). > > Thank you. > > Best regards, > Muthu I definitely prefer the Linux version. See the thread "Is Vista Workable" for a huge list of reasons why. Just make sure that the Linux version you pick is supported by Xilinx. me.Article: 133352
"Mike Treseler" <mike_treseler@comcast.net> wrote in message news:6cfb87F3f44j2U1@mid.individual.net... > Symon wrote: > >> Do you have any examples of any 'proper' CAM devices that I can research? >> I >> know that Altera's ESBs can be used as small CAMs, and that Xilinx have >> an >> app. note design that can do single cycle reads and multi-cycle writes >> using >> a BlockRAM. It would appear that Micron have dumped their 2Mb 'Harmony' >> device long ago. I found various dead links to products, but nothign >> active. > > Useful CAM structures don't fit well in FPGAs > and the vendors have quit trying. > Some sort of hash table may be a better fit. > http://en.wikipedia.org/wiki/Hash_table > > -- Mike Treseler Hi Mike, Right, but are there any custom CAM devices out there? Thanks, Syms.Article: 133353
Symon wrote: > Right, but are there any custom CAM devices out there? > Thanks, Syms. Most have dropped out. Check idt and netlogic.Article: 133354
"Mike Treseler" <mike_treseler@comcast.net> wrote in message news:6cfgdeF3g3m7sU1@mid.individual.net... > Symon wrote: > >> Right, but are there any custom CAM devices out there? >> Thanks, Syms. > > Most have dropped out. > Check idt and netlogic. > > Looks like they're called "network search engines" these days. Thanks mate! http://idt.com/?genID=75K52134 http://www.netlogicmicro.com/2-products/nse70k.htmArticle: 133355
On Jun 23, 6:46 am, "SynopsysFPGAexpress" <fp...@sss.com> wrote: > Starting withISE10.1, has begun migrating some hard-IP simulation models > from Smartmodel to "SecureIP." For now, the SecureIP blocks can only > be simulated in 1simulator: Modelsim 6.3c (or later) > > " AR #30975 - 10.1 SecureIP libraries - Does NCSIM and VCS support Secure IP > flow?"http://www.xilinx.com/support/answers/30975.htm > Answer: SecureIP in NCSIM and VCS will be supported starting inISE11.1 > > Ok, so I guess the question is, when isISE11.1 planned for release? > Also, will the Aldec simulators (Active-HDL, Riviera) be supported, too? Hi 11.1 is planned to be released a year after 10.1. That means plan for March 2009. Xilinx is considering working with some customers on a beta program to get feedback for the NCSim and Synopsys support. If interested in this, please contact your Xilinx FAE. Aldec simulators are not supported by Xilinx and that is why you will probably need to talk to Aldec to get their roadmaps. Thanks DuthArticle: 133356
Hi! I'm designing a Spartan 3 FPGA with ISE 9.2 and just hit the point where the FPGA couldn't be routed anymore since it was too full. Now I have to optimize or reduce some modules to win some area, but I can only guess which ones use a lot of area so optimizing them would win me significant = space. Is there a tool (or am I overlooking something in ISE) which tells me whi= ch part of the design uses how much space? I'm aware that optimizing across hierarchy may make this information inaccurate, but still I guess it woul= d show me the right way... - Philip --=20 Frauenparkpl=E4tze sind eine gute Sache - fr=FCher ist man als Triebt=E4ter stundenlang ziellos durch's Parkhaus geirrt. (Andreas Leidig)Article: 133357
On Jun 23, 2:35 pm, "HT-Lab" <han...@ht-lab.com> wrote: > "SynopsysFPGAexpress" <fp...@sss.com> wrote in message > > news:JON7k.9710$jI5.7637@flpi148.ffdc.sbc.com... > > > Starting withISE10.1, has begun migrating some hard-IP simulation models > > from Smartmodel to "SecureIP." For now, the SecureIP blocks can only > > be simulated in 1simulator: Modelsim 6.3c (or later) > > > " AR #30975 - 10.1 SecureIP libraries - Does NCSIM and VCS support Secure > > IP flow?" > >http://www.xilinx.com/support/answers/30975.htm > > Answer: SecureIP in NCSIM and VCS will be supported starting inISE11.1 > > > Ok, so I guess the question is, when isISE11.1 planned for release? > > Also, will the Aldec simulators (Active-HDL, Riviera) be supported, too? > > I also seems to require a Verilog License(?): > > http://www.xilinx.com/support/answers/30481.htm > > But then this answer seems to indicate you can use VHDL (look at the > solution) or at least after 10.1 SP2 > > http://www.xilinx.com/support/answers/31125.htm > > If Verilog is required than I hope that Xilinx is kind enough to support > both Smartmodels and SecureIP until VHDL 4.0/2008 is supported (support > encryption in the same way as Verilog), > > Hanswww.ht-lab.com Hi, The problem is not just that VHDL does not have an encryption technology. The main issue is that the IP for these blocks are delivered in verilog only and that is why you will need to have a mixed-language license in order to simulate your VHDL design.This was always the case right from the beginning you do get a VHDL wrapper although it will call an underlying verilog model. For the reasons I provided in the last post. As far as Smartmodel support, it really is a dying product for Xilinx as smartmodels are not supported on windows and that will put our offering at risk. This is why we needed to move away from this method. Similarly the new encryption methods do not leverage any SWIFT interface and so you should see significant performance improvements. In summary you can continue to design in VHDL although when simulating be aware you will need a mixed language license as stated in the Synthesis and Simulation Design Guide. If cost is an issue please bring this up with the simulator vendor that you use, also note that you can simulate these models for free using the Xilinx ISim product as well. Thanks DuthArticle: 133358
On Jun 25, 3:01 pm, Philip Herzog <p...@arcor.de> wrote: > Hi! > > I'm designing a Spartan 3 FPGA with ISE 9.2 and just hit the point where > the FPGA couldn't be routed anymore since it was too full. Now I have to > optimize or reduce some modules to win some area, but I can only guess > which ones use a lot of area so optimizing them would win me significant = space. > > Is there a tool (or am I overlooking something in ISE) which tells me whi= ch > part of the design uses how much space? I'm aware that optimizing across > hierarchy may make this information inaccurate, but still I guess it woul= d > show me the right way... > > - Philip > -- > Frauenparkpl=E4tze sind eine gute Sache - fr=FCher ist > man als Triebt=E4ter stundenlang ziellos durch's > Parkhaus geirrt. (Andreas Leidig) I never found one. I have built each module seperately to get an idea of how big they are. I just drop the module into the largest package device of the family, and check carefully that it doesn't all get optimized away. G.Article: 133359
In comp.arch.fpga PFC <lists@peufeu.com> wrote: > Taking well-designed software as example, your 220 ms time budget is > enough for Postgresql to perform about 3000-5000 simple SQL queries > returning 1 row with btree index lookup on a table with millions of rows > including network overhead (as long as it doesn't need to hit the disk), > in 220 ms Xapian can make multiple full text phrase searches with ranking > on a multi gigabyte text dataset. And Google can search the entire freaking Internet :-) > So, I suggest reviewing your search algorithm ;) What he said. Describe problem more please. G.Article: 133360
Philip Herzog wrote: > I'm designing a Spartan 3 FPGA with ISE 9.2 and just hit the point where > the FPGA couldn't be routed anymore since it was too full. Now I have to > optimize or reduce some modules to win some area, but I can only guess > which ones use a lot of area so optimizing them would win me significant space. Many tools flatten the netlist before P&R so they don't know by then which module anything came from. You can try routing individual modules to see how big they are (even though it won't run that way). It should be a rough approximation to the size, but won't be exact. It will work better if you specify a smaller device so that P&R has some work to do. It should report LUTs used, use that for area. -- glenArticle: 133361
Mike Treseler wrote: > Useful CAM structures don't fit well in FPGAs > and the vendors have quit trying. > Some sort of hash table may be a better fit. > http://en.wikipedia.org/wiki/Hash_table Or systolic array if you are doing many such searches at the same time. http://en.wikipedia.org/wiki/Systolic_array -- glenArticle: 133362
On Jun 25, 3:01 pm, Philip Herzog <p...@arcor.de> wrote: > Hi! > > I'm designing a Spartan 3 FPGA with ISE 9.2 and just hit the point where > the FPGA couldn't be routed anymore since it was too full. Now I have to > optimize or reduce some modules to win some area, but I can only guess > which ones use a lot of area so optimizing them would win me significant = space. > > Is there a tool (or am I overlooking something in ISE) which tells me whi= ch > part of the design uses how much space? I'm aware that optimizing across > hierarchy may make this information inaccurate, but still I guess it woul= d > show me the right way... > > - Philip > -- > Frauenparkpl=E4tze sind eine gute Sache - fr=FCher ist > man als Triebt=E4ter stundenlang ziellos durch's > Parkhaus geirrt. (Andreas Leidig) I believe ISE 10.1 has a hierarchical report of each module consumption. It is quite detailed and lists the resource types and for a number of levels of hierarchy. Maybe try updgrade ISE to 10.1?Article: 133363
I found that catching interrupts when debugging is very hard to do. I had the same problem of missing interrupts when trying to write the stack frame save code for a RTOS that I wrote. I was using the PPC405 though. ---Matthew Hicks > Just a small update again. I managed to get the design working a bit > better... I modified my linker script, such that the .vectors section > is now stored in the BRAM memory instead of the DDR2 memory. As a > result the processor keeps working after an interrupt. So maybe the > problem was some kind of timeout error because of the slow DDR-RAM? > > But I now have the problem that the processer seems to see interrupts > all the time. Actually there are no interrupts from the interrupt > controller. So the processor just stays in the interrupt routines for > an external interrupt all the time and the normal program is never > continued after there was one or more real interrupts. But it is now > possible to have more than just a single interrupt. > > The odd thing again is that the processor goes to the normal program > when I use step by step in XMD. > > Matthias > > Matthias Alles schrieb: > >> The thing is really odd. I wanted to figure out when the program >> jumps >> to the address 0x60. I used XMD, set a breakpoint to the interrupt >> and >> went through the whole interrupt stuff step by step (i.e. instruction >> by >> instruction). I could see, that the program is continued correctly >> after >> the interrupt (it sends data through UART). So everything worked as >> expected! >> However, when I then use "con" to continue the program (after the >> interrupt was successful and the normal program already continued), >> the >> program freezes again and the program counter is set to 0x60 (which >> seems to be a program exception or something like that). >> How can that be? >> >> Matthias >> >>> I have the following problem on a Virtex5 system: >>> I use an interrupt controller, that is connected to the PPC >>> interrupt >>> port. The interrupt controller and the PPC interrupt handler are >>> initialized but working ONLY for the very first interrupt. After the >>> first interrupt occured the processor hangs at address 0x60, which >>> is in >>> the interrupt vector table: >>> 00000060 <IVOR6>: >>> 60: 7c 70 43 a6 mtsprg 0,r3 >>> 64: 38 60 00 06 li r3,6 >>> 68: 7c 60 43 a6 mtspr 256,r3 >>> 6c: 48 00 00 94 b 100 <non_critical_irq> >>> Did I miss something about the initialization? I used the source >>> code provided with the examples of the xps_intc. >>> >>> Matthias >>>Article: 133364
> I also wrote a Pearl script to elaborate and/or synthesise the entire > code tree (using wildcards etc) so at any point I can quickly see what > I may have "broken" with my last set of changes... > > Regards, > I forgot to mention that I like to make use of Verilog's pre-processor, when I can, and as Mark mentioned, a script/program that generates code with specific parameters based on a template also works in certain situations. ---Matthew HicksArticle: 133365
>I forgot to mention that I like to make use of Verilog's pre-processor, when >I can, and as Mark mentioned, a script/program that generates code with specific >parameters based on a template also works in certain situations. You can also use cpp as a preprocessor. It helps to be good with makefiles and/or may not fit your style if you like the big green button on the GUI. -- These are my opinions, not necessarily my employer's. I hate spam.Article: 133366
On 2008-06-25, Philip Herzog <phu@arcor.de> wrote: > Hi! > > I'm designing a Spartan 3 FPGA with ISE 9.2 and just hit the point where > the FPGA couldn't be routed anymore since it was too full. Now I have to > optimize or reduce some modules to win some area, but I can only guess > which ones use a lot of area so optimizing them would win me significant space. > > Is there a tool (or am I overlooking something in ISE) which tells me which > part of the design uses how much space? I'm aware that optimizing across > hierarchy may make this information inaccurate, but still I guess it would > show me the right way... I have a small Perl script to do this at http://www.da.isy.liu.se/~ehliar/stuff/ You can see an example output of the script if you search for xdlanalyze on the webpage. /AndreasArticle: 133367
Philip Herzog schrieb: > Hi! > > I'm designing a Spartan 3 FPGA with ISE 9.2 and just hit the point where > the FPGA couldn't be routed anymore since it was too full. Now I have to > optimize or reduce some modules to win some area, but I can only guess > which ones use a lot of area so optimizing them would win me significant space. > > Is there a tool (or am I overlooking something in ISE) which tells me which > part of the design uses how much space? I'm aware that optimizing across > hierarchy may make this information inaccurate, but still I guess it would > show me the right way... > > - Philip Hi Philip, if you just want to get an idea about the area of each module, you can use the floorplanner tool. Make sure that "keep hierarchy" is enabled in your synthesis properties, so each module will be shown in a different colour. If the PAR doesn't finish the routing, disable it. Placement only is all you need to see the area in floorplaner. have a nice synthesis EilertArticle: 133368
On Jun 25, 10:07=A0pm, Heinrich <Heinr...@myweb.com> wrote: > Else if I should have missed something I would be thankful for letting > me know How about timing / synchronization of the data? Is a clock being forwarded from one FPGA to the other, to which the data is sychronized? If not, how do you expect the receiving FPGA to know when each data bit is valid? If you want to treat the interface as asynchronous, you need an additional strobe from the tx which changes when a bit is valid, and some logic at the receiver side to sync to the receiver's internal clock to mitigate metastability issues. -TomArticle: 133369
Hi all, Im working on trimode Ethernet Mac core on Virtex 4. There is a tool in thie core called ":Xilinx Hardware Demonstration Platform" which acually displays the peckects being send and you can also set some parameter for the packet like destination address, length etc. Now the problem is with the destination address. Im entering a destination MAC address in its parameters but in the "frames read from FIFO" the value of the DA doesnt change. it reamins FF:FF:FF:FF:FF:FF; . So plz help me in this regard as how to change DA. plz reply ASAP. ThanksArticle: 133370
Heinrich schrieb:
> Hello
>
> Very easy question, but I just wanna make sure that I have done it the
> correct way so that I dont have to look in this simple stuff for errors :)
>
> Basically I have two FPGAs (Control & Target FPGAs) and I wanna foward
> data between them for receiving and sending single bits. My VHDL code
> for the Control FPGA looks as follows:
>
> library IEEE;
> use IEEE.std_logic_1164.all;
> use IEEE.std_logic_arith.all;
>
> entity ForwardBits is
> port(
> a_control : in std_logic;
> b_control : out std_logic;
> a_target : out std_logic;
> b_target : in std_logic
> );
> end ForwardBits;
>
> architecture Behavior of ForwardBits is
>
> begin
>
> a_target <= a_control;
> b_control<= b_target;
>
> end architecture Behavior;
>
> And the other thing I have to do is mapping the signals to PINs of the
> Control FPGA which looks as follows:
>
> NET "b_control" LOC = "M25";
> NET "a_control" LOC = "M26";
> NET "a_target" LOC = "U2";
> NET "b_target" LOC = "V5";
>
> Basically, the only erros could be done with the Pin mapping but that
> should be fine.
>
> Else if I should have missed something I would be thankful for letting
> me know
>
> Cheers
>
Hi Heinrich.
Everything looks fine, so far. But I'm still wondering what you are
about to do with that code?
First thing: You have two FPGAs.
So, how many IOs (regarding the above example) are in use on each FPGA?
Two or four?
If it is four, and you are connecting the signals as shown in your
example architecture inside one of your FPGAs you are creating a
two-wire loop. This makes barely any sense, unless you just want to
sense the presence or status of the other FPGA.
Or do you intend to have two signals on each fpga like this:
fpga1 fpga2
-------- ------------
| |
a_out|----------------->| a_in
| |
b_in |<-----------------| b_out
| |
-------- ------------
In this case you need two UCF files. One for each FPGA.
And there's no special code needed to access the ports.
example_fpga1:
control_something:process(b_in)
begin
...
end process;
a_out <= some_control_signal_for_target;
example_fpga1:
target_something:process(a_in)
begin
...
end process;
b_out <= some_target_signal_for_control;
_________________
So which one is the idea you have in mind?
Have a nice synthesis
Eilert
Article: 133371> I have constructed these blocks and the memory portion is working > however i cannot get the 2 peripherals to communicate with each other > is there anything i'm overlooking? > > Has anyone done anything similar to this? If you want your peripherals to communicate you will need to connect them together. In order to do this they must have some ports. The specification of those ports is up to you but they must appear in the VHDL/Verilog code (obviously) and also in the MPD file for your peripheral. The ports will then appear in XPS, in the "Ports" display mode. You can make the ports external (as you would usually do) but you can also connect ports internally simply by connecting them to the same net, just assign unique net names and you're set. If your port uses a standard xilinx bus spec (like MCH/XCL initiator and target) it will appear in the main window (provided the MPD file is correct) and you can connect it by clicking on the little wires and triangles XPS displays, just like you would connect a peripheral to the bus. For instance I created a peripheral that must access data from RAM at high throughput. I gave it a MCH initiator interface and connected this to the mch_sdram controller using the GUI. I had to hack the files a bit to get the correct syntax but it's easy. You have already done this if one of your peripherals has an interrupt that you connected to opb_intc, it's the same. The interface sucks, though, you might want to edit the MHS file directly and do some happy copypasting.Article: 133372
I found the solution for this problem. The thing is that the flag for a decrementer interrupt (DEC) was set in the timer status register (TSR) after powerup. Since I don't use this DEC interrupts the flag of course is never cleared. Now when I enable my external interrupts (EE flag in MSR) the DEC interrupt is enabled as well. Since I don't have an interrupt handler for this case the interrupt occurs all the time and the normal program is never executed anymore. So a single line in the startup code does the trick: XTime_TSRClearStatusBits(XREG_TSR_CLEAR_ALL); The difference between stp and con in XMD seems to show that stp just doesn't care about interrupts at all. MatthiasArticle: 133373
On Jun 26, 5:48 am, backhus <n...@nirgends.xyz> wrote: > Philip Herzog schrieb:> Hi! > > > I'm designing a Spartan 3 FPGA with ISE 9.2 and just hit the point where > > the FPGA couldn't be routed anymore since it was too full. Now I have to > > optimize or reduce some modules to win some area, but I can only guess > > which ones use a lot of area so optimizing them would win me significant space. > > > Is there a tool (or am I overlooking something in ISE) which tells me which > > part of the design uses how much space? I'm aware that optimizing across > > hierarchy may make this information inaccurate, but still I guess it would > > show me the right way... > > > - Philip > > Hi Philip, > if you just want to get an idea about the area of each module, you can > use the floorplanner tool. Make sure that "keep hierarchy" is enabled in > your synthesis properties, so each module will be shown in a different > colour. If the PAR doesn't finish the routing, disable it. Placement > only is all you need to see the area in floorplaner. > > have a nice synthesis > Eilert You can also have a look at the modules in floorplanner just after translate (again, the "keep hierarchy" is essential). This is the size of the modules after synthesis, but the map stage may increase or decrease the size of the design by optimising or duplicating logic. RobArticle: 133374
Hi, I have a problem with getting the correct startup values for an array of bytes on a Xilinx V5 When the array is declared it is initialised using a function (which of course has only constant inputs). In simulation the array appears to be correctly initialised, but when the bitfile is downloaded it looks as though all the registers are initialised to zero. Is it me or XST!? Rob
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Compare FPGA features and resources
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