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On Jun 30, 11:00=A0am, timinganalyzer <timinganaly...@gmail.com> wrote:
> On Jun 30, 1:21 pm, mahesh <mahesh...@gmail.com> wrote:
>
>
>
>
>
> > On Jun 30, 5:50 am, timinganalyzer <timinganaly...@gmail.com> wrote:
>
> > > On Jun 29, 11:36 pm, mahesh <mahesh...@gmail.com> wrote:
>
> > > > On Jun 29, 5:54 pm, timinganalyzer <timinganaly...@gmail.com> wrote=
:
>
> > > > > Hello All,
>
> > > > > A new version beta 0.85 is now available. =A0The following change=
s and
> > > > > additions have occurred.
>
> > > > > 1 Quickly add previously used Delays and Constraints from pop-up =
menu
> > > > > 2 The current state is inverted automatically when adding new pul=
se if
> > > > > the newstate in the
> > > > > =A0 =A0toolbar is the same as the current state in the signal.
> > > > > 3 Keystroke shortcuts for all the signal state buttons in toolbar=
.
> > > > > Hover over button to see keystrokes.
> > > > > 4 Signals can now use text values for next state. =A0This is usef=
ul when
> > > > > labels are needed in digital signals.
> > > > > 5 Moving text and edges by mouse drags now use undo and redo
> > > > > 6 Should work with JRE1.5 or newer
>
> > > > > You can download the Free Edition now and read all about the
> > > > > TimingAnalyzer at:
>
> > > > >www.timing-diagrams.com
>
> > > > Hi,
> > > > =A0 =A0 =A0I tried to install it on Vista Basic.But facing difficul=
ty in
> > > > installing.I did install the JRE.when I run the timinganalyzer.jar =
exe
> > > > file It pops me a message saying main class not found exiting !!
> > > > =A0 =A0 =A0Could u pls help me in fixing the problem ...ur help wil=
l be
> > > > appreciated
>
> > > > Thanks in advance,
> > > > hesh
>
> > > Can you tell what version of Java you are using? =A0I have used beta
> > > 0.85
> > > with JRE1.5.
>
> > > If you bring up a dos window, =A0enter
>
> > > java -jar TimingAnalyzer.jar
>
> > > This will report the OS, =A0Java version, =A0....
>
> > > Thanks, =A0Dan
>
> > Hi ,
>
> > =A0 =A0 =A0 =A0I installed java version 1.6.0_06.but unable to run the
> > analyzer...pls do gimme ur inputs...
>
> > Thanks in advance,
> > hesh
>
> Hello Hesh,
>
> Maybe somehow the the zip file you downloaded was corrupted? =A0The file
> size is 5,170KB.
> When you extract the zip file, =A0you should see the directory structure
> shown below
>
> =A0c:\Apps\TimingAnalyzer_bxx dir
> =A0 =A0 =A0 =A0 =A0 TimingAnalyzer.jar =A0 =A0 -- =A0 The executable prog=
ram
> =A0 =A0 =A0 =A0 =A0 docs dir =A0 =A0 =A0 =A0 =A0 =A0 =A0 -- =A0 html help=
files required by
> program
> =A0 =A0 =A0 =A0 =A0 images dir =A0 =A0 =A0 =A0 =A0 =A0 -- =A0 images requ=
ired by program
> =A0 =A0 =A0 =A0 =A0 scripts dir =A0 =A0 =A0 =A0 =A0 =A0-- =A0 user script=
s
> =A0 =A0 =A0 =A0 =A0 themes dir =A0 =A0 =A0 =A0 =A0 =A0 -- =A0 look and fe=
el themes
> =A0 =A0 =A0 =A0 =A0 pics dir =A0 =A0 =A0 =A0 =A0 =A0 =A0 -- =A0 saved ima=
ges of example files
> =A0 =A0 =A0 =A0 =A0 examples dir =A0 =A0 =A0 =A0 =A0 -- =A0 timing diagra=
m example files
> =A0 =A0 =A0 =A0 =A0 settings dir =A0 =A0 =A0 =A0 =A0 -- =A0 default and u=
ser
> settings
>
> If your extracted directory structure and the size the program looks
> correct, then do
> the following and let me know the results.
>
> Open dos window.
> cd to TimingAnalyzer_b85
> java -jar TimingAnalyzer.jar
>
> Copy the output shown in the dos window and send that to me.
> Let me know how you make out.
>
> Thanks,
> Dan- Hide quoted text -
>
> - Show quoted text -
Hi Dan,
I downloaded it again....got the issue fixed...
Thanks a lot for ur help,
hesh
Article: 133476
In article <mfW9k.30790$ZE5.14811@nlpi061.nbdc.sbc.com>,
hlao <hlao@nowhere.net> wrote:
>I created a simple Verilog-2001 test-module:
>When I ran this module through Xilinx Webpack 10.1, it synthesized
>as a "addsub" macro...
>But I tried the same top.v module in Altera Quartus-II.
>When I synthesize to (Cyclone-II 2C20), Quartus-II creates an adder unit,
>plus a bunch of separate muxes in front of port 'inb.' I've found that the
>LUT consumption is TWICE the amount (34 vs 17) as a straight adder-only.
Yes Altera LE-based FPGAs work like this. Pretty much the entire LUT is
used as a full adder, there is not enough left for an optional
ones-complement of the B input to generate selectable subtractor.
This is changed beginning with the Stratix-II ALM design.
But why do you care? How many selectable adder/subtractors are you going to
have in your design? Even if it was a lot, Cyclone-II FPGAs have plenty of
LUTs.
You would only really care if it made a timing difference. The only way to
know this is to run your entire design through each vendor's tools.
There's a good chance that Altera would win this due to a less obvious
feature of their 4-input LUTs: namely that the input to output delay depends
on which pins are used: some are slow and some are fast (unlike Xilinx which
are all even). The tool maps timing critical pins to the fast inputs.
If you want something more significant to compare between X and A, compare
Xilinx LUT-RAMs with Altera M4Ks available in Cyclone-II. The combinatorial
read port on the LUT-RAMs (and SRL16s) is sometimes very convenient.
--
/* jhallen@world.std.com AB1GO */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 133477Zhane wrote: > when i try to translate it, it tells me this > > ERROR:NgdBuild:753 - "top.ucf" Line 4: Could not find instance(s) > 'DCM_SP_INST' > in the design. To suppress this error specify the correct instance > name or > remove the constraint. > > <snip> > > my top.vhd, make use of a component from clockmanager.vhd ...inside > clockmanager.vhd has > > what's wrong huh? Perhaps you forgot to include the libraries? library unisim; use unisim.vcomponents.all; HTH -P@Article: 133478
On Jul 1, 1:20=A0pm, PatC <p...@REMOVETHISpatocarr.com> wrote: > Zhane wrote: > > when i try to translate it, it tells me this > > > ERROR:NgdBuild:753 - "top.ucf" Line 4: Could not find instance(s) > > 'DCM_SP_INST' > > =A0 =A0in the design. =A0To suppress this error specify the correct ins= tance > > name or > > =A0 =A0remove the constraint. > > > <snip> > > > my top.vhd, make use of a component from clockmanager.vhd ...inside > > clockmanager.vhd has > > > what's wrong huh? > > Perhaps you forgot to include the libraries? > > library unisim; > use unisim.vcomponents.all; > > HTH > -P@ even after including in my top.vhd also cannot. Im still getting the same error But when i remove... INST DCM_SP_INST CLK_FEEDBACK =3D 1X; INST DCM_SP_INST CLKDV_DIVIDE =3D 2.0; INST DCM_SP_INST CLKFX_DIVIDE =3D 1; INST DCM_SP_INST CLKFX_MULTIPLY =3D 2; INST DCM_SP_INST CLKIN_DIVIDE_BY_2 =3D FALSE; INST DCM_SP_INST CLKIN_PERIOD =3D 20.000; INST DCM_SP_INST CLKOUT_PHASE_SHIFT =3D NONE; INST DCM_SP_INST DESKEW_ADJUST =3D SYSTEM_SYNCHRONOUS; INST DCM_SP_INST DFS_FREQUENCY_MODE =3D LOW; INST DCM_SP_INST DLL_FREQUENCY_MODE =3D LOW; INST DCM_SP_INST DUTY_CYCLE_CORRECTION =3D TRUE; INST DCM_SP_INST FACTORY_JF =3D C080; INST DCM_SP_INST PHASE_SHIFT =3D 0; INST DCM_SP_INST STARTUP_WAIT =3D FALSE; from my constraints file...i can do it w/o any error. should I remove them?Article: 133479
Zhane wrote: > On Jul 1, 1:20 pm, PatC <p...@REMOVETHISpatocarr.com> wrote: >> Zhane wrote: >>> when i try to translate it, it tells me this >>> ERROR:NgdBuild:753 - "top.ucf" Line 4: Could not find instance(s) >>> 'DCM_SP_INST' >>> in the design. To suppress this error specify the correct instance >>> name or >>> remove the constraint. >>> <snip> >>> my top.vhd, make use of a component from clockmanager.vhd ...inside >>> clockmanager.vhd has >>> what's wrong huh? Since the instance is inside another module, you have to specify the complete path to the instance you want to constrain, e.g. INST clockmanager_inst/DCM_SP_INST CLK_FEEDBACK = 1X; ... and so on. clockmanager_inst is the instance name for the clockmanager-module you use in your top level. > even after including in my top.vhd also cannot. Im still getting the > same error > But when i remove... > > INST DCM_SP_INST CLK_FEEDBACK = 1X; > INST DCM_SP_INST CLKDV_DIVIDE = 2.0; > INST DCM_SP_INST CLKFX_DIVIDE = 1; > INST DCM_SP_INST CLKFX_MULTIPLY = 2; > INST DCM_SP_INST CLKIN_DIVIDE_BY_2 = FALSE; > INST DCM_SP_INST CLKIN_PERIOD = 20.000; > INST DCM_SP_INST CLKOUT_PHASE_SHIFT = NONE; > INST DCM_SP_INST DESKEW_ADJUST = SYSTEM_SYNCHRONOUS; > INST DCM_SP_INST DFS_FREQUENCY_MODE = LOW; > INST DCM_SP_INST DLL_FREQUENCY_MODE = LOW; > INST DCM_SP_INST DUTY_CYCLE_CORRECTION = TRUE; > INST DCM_SP_INST FACTORY_JF = C080; > INST DCM_SP_INST PHASE_SHIFT = 0; > INST DCM_SP_INST STARTUP_WAIT = FALSE; > > from my constraints file...i can do it w/o any error. > > should I remove them? You can use attributes in your VHDL-code instead of specifying constraints in the UCF, or you can specify GENERICs when instantiating. See http://tinyurl.com/4cwlf8 HTH, Sean -- My email address is only valid until the end of the month. Try figuring out what the address is going to be after that...Article: 133480
Hi there, I have the same problem, I find this document that say to start the server cs_server.sh before start the analyser http://www.xilinx.com/publications/xcellonline/xcell_55/xc_chipscope55.htm bye Oscar. On 13 Giu, 07:38, Alan Nishioka <a...@nishioka.com> wrote: > On Jun 12, 9:25 am, "Symon" <symon_bre...@hotmail.com> wrote: > > > Alan Nishioka wrote: > > > On Jun 12, 8:14 am, ni <nbg2...@gmail.com> wrote: > > >> I get the following error with chipscope analyzer whenever I do the > > >> intialize chain. > > >> ERROR: Socket Open Failed. localhost/127.0.0.1:50001 > > >> localhost > > >> java.net.ConnectException: Connection refused > > >> ERROR: Failed to detect cable. > > >> Try to open a specific cable from the 'JTAG Chain' menu > > > >> IMPACT is able to initialize the chain successfully. > > > > It looks like a network connection is failing. =A0Are you sure you are= > > > not being blocked by your firewall? > > > > Alan Nishioka > > > Hi Alan, > > > I don't think that's it.http://en.wikipedia.org/wiki/Localhost > > > Did the OP try turning his computer off and on again? ;-) > > > Cheers, Syms. > > Zone Alarm can block this sort of access and cause this sort of > problem. =A0It causes similar problems with the Xilinx simulator. > > Alan NishiokaArticle: 133481
On Sat, 28 Jun 2008 13:39:09 -0400, "KJ" <kkjennings@sbcglobal.net>
wrote:
> <snipped>
Thanks. And thanks to those who gave me an opinion without an
accompanying lecture on logic minimisation.
The 'why' is not very interesting - basically feature creep. I have a
verification tool which allows usage of multi-dimensional arrays. It
occurred to me that, with a couple of hours fiddling, I could modify
the array indexing so that you could convert an array initialiser into
a K-map:
// f is a 5D array, but the 'kmap' declaration handles the complexity
kmap f = 0 1 1 0 1 0 1 0 // uses reflected-binary addressing,
1 1 0 0 0 0 1 1 // not "C-style" addressing
1 0 1 0 0 1 1 1
1 0 1 1 1 1 1 0;
...
x = f[A,B,C,D,E]; // compute a function of 5 vars
Not Earth-shattering, but potentially useful to people who still do
combinatorial logic design, although there can't be many of them left.
Nothing to do with minimisation, but presumably those people will have
a preferred array layout which was originally derived from
minimisation principles. I didn't want to impose reflected-binary
addressing on them if another form was preferable.
-Evan
Article: 133482
On Sat, 28 Jun 2008 17:25:42 -0700 (PDT), ajjc <ajjc@optngn.com>
wrote:
>In John F. Wakerly's "Digital Design, Principles and Practices",
>4th Edition, pgs 235-236,564 (there is also a 5th edition)
>uses your second version (the historical one) of 5/6-variable map
>for logic minimization exercises and FSM synthesis.
>Of course, mathematically, either one works.
Yes, my copy of Lewin ("Logical Design of Switching Circuits") does
the same. I suspect that teaching material does this because it's
easier to visualise, where the more academic approach may be the
reflected-binary version.
Thanks
Evan
Article: 133483Here is an XAPP that should get you started. There is a TFTP server example using lwip which you can use to transfer data between the PC and Microblaze. www.xilinx.com/support/documentation/application_notes/xapp1026.pdf --parag On Jun 30, 4:20=A0am, chrisde...@gmail.com wrote: > Hi, > =A0 =A0I am new to using lwip. I am wondering if you can advice me on the > same. > =A0 =A0I need to transfer data from PC to Microblaze microprocessor on a > Xilinx FPGA board and vice versa as fast as possible. i dun need any > error correction or the overheads like full TCP/IP. I am currently > readin this article to understand about socket programming as an > initial start: > > http://cscene.unitycode.org/topics/unix/cs2-13.xml.html > > =A0 =A0Here are the questions that I have: > > 1) =A0 I am stuck at the part in the link above which says > =A0 =A0hp=3Dgethostbyname(servername);a > the code above is more for developing applications on PC. I am looking > for lwip drivers to run on the Microblaze (32bit CPU) on the FPGA. > > cos i cannot find a similar function in lwip. any idea how to resolve > this? i have tried looking for equiv functions like getnameinfo(), > getaddrinfo() but these functions will work. :( > > 2) any other useful links to read for regards to this topic? i have > tried looking athttp://www.xilinx.com/ise/embedded/edk91i_docs/lwip_v2_00_= a.pdf > > what do i need to purchase to let the sockets running on both PC and > FPGA communicate with each other? > > possible to advice me on some documents to point me in the right > direction? > > thanks > ChrisArticle: 133484
>From the expert: "To simplify and clarify: 1) S[11] = 0, S[10:0] = 0 | No error 2) S[11] = 1, S[10:0] = X | Single bit error, S[10:0] is the correction ptr. 3) S[11] = 0, S[10:0] != 0 | Double bit error, uncorrectable 1 & 3 are obviously very simple because there is no decoding to be done. 2 requires syndrome decoding, and there are a lot of exceptional cases - the documentation of which can be a bit confusing and lead to errors, as we see in the V5 config UG." True for both V4 and V5, AustinArticle: 133485
On Jul 1, 5:38=A0pm, Sean Durkin <news_ju...@durkin.de> wrote: > Zhane wrote: > > On Jul 1, 1:20 pm, PatC <p...@REMOVETHISpatocarr.com> wrote: > >> Zhane wrote: > >>> when i try to translate it, it tells me this > >>> ERROR:NgdBuild:753 - "top.ucf" Line 4: Could not find instance(s) > >>> 'DCM_SP_INST' > >>> =A0 =A0in the design. =A0To suppress this error specify the correct i= nstance > >>> name or > >>> =A0 =A0remove the constraint. > >>> <snip> > >>> my top.vhd, make use of a component from clockmanager.vhd ...inside > >>> clockmanager.vhd has > >>> what's wrong huh? > > Since the instance is inside another module, you have to specify the > complete path to the instance you want to constrain, e.g. > > INST clockmanager_inst/DCM_SP_INST CLK_FEEDBACK =3D 1X; > > ... and so on. clockmanager_inst is the instance name for the > clockmanager-module you use in your top level. > > > > > even after including in my top.vhd also cannot. Im still getting the > > same error > > But when i remove... > > > =A0 =A0 =A0 =A0 =A0 =A0INST DCM_SP_INST CLK_FEEDBACK =3D 1X; > > =A0 =A0 =A0 =A0 =A0 =A0INST DCM_SP_INST CLKDV_DIVIDE =3D 2.0; > > =A0 =A0 =A0 =A0 =A0 =A0INST DCM_SP_INST CLKFX_DIVIDE =3D 1; > > =A0 =A0 =A0 =A0 =A0 =A0INST DCM_SP_INST CLKFX_MULTIPLY =3D 2; > > =A0 =A0 =A0 =A0 =A0 =A0INST DCM_SP_INST CLKIN_DIVIDE_BY_2 =3D FALSE; > > =A0 =A0 =A0 =A0 =A0 =A0INST DCM_SP_INST CLKIN_PERIOD =3D 20.000; > > =A0 =A0 =A0 =A0 =A0 =A0INST DCM_SP_INST CLKOUT_PHASE_SHIFT =3D NONE; > > =A0 =A0 =A0 =A0 =A0 =A0INST DCM_SP_INST DESKEW_ADJUST =3D SYSTEM_SYNCHR= ONOUS; > > =A0 =A0 =A0 =A0 =A0 =A0INST DCM_SP_INST DFS_FREQUENCY_MODE =3D LOW; > > =A0 =A0 =A0 =A0 =A0 =A0INST DCM_SP_INST DLL_FREQUENCY_MODE =3D LOW; > > =A0 =A0 =A0 =A0 =A0 =A0INST DCM_SP_INST DUTY_CYCLE_CORRECTION =3D TRUE; > > =A0 =A0 =A0 =A0 =A0 =A0INST DCM_SP_INST FACTORY_JF =3D C080; > > =A0 =A0 =A0 =A0 =A0 =A0INST DCM_SP_INST PHASE_SHIFT =3D 0; > > =A0 =A0 =A0 =A0 =A0 =A0INST DCM_SP_INST STARTUP_WAIT =3D FALSE; > > > from my constraints file...i can do it w/o any error. > > > should I remove them? > > You can use attributes in your VHDL-code instead of specifying > constraints in the UCF, or you can specify GENERICs when instantiating. > Seehttp://tinyurl.com/4cwlf8 > > HTH, > Sean > > -- > My email address is only valid until the end of the month. > Try figuring out what the address is going to be after that... thanks.. it solved the problem. I've been trying out the following code with TEMPUART.VHD as my top module on my UART. I connected the Uart of my spartan to my PC using a null modem connection. It's weird cause I never seem to be able to get the data I output , FF and 0A, on my PC. I get 7F instead of FF... http://www.mediafire.com/?mjbgzgwxtwb << my source is located hereArticle: 133486
I just wanted to know whether type casting in verilog is sythesizable or not?Article: 133487
Adam, OK, I opened up FPGA Editor, so I now think I know what you are asking. Associated with each CLB, is an interconnect block. This block represents a convenient way to visualize the interconnection resources in the FPGA (the actual schematics, layout, and physical placement is entirely different). This "switch box" has inputs and outputs. There is a little block to the right, and to the top of the switch box, which has some logic 0, and logic 1 points. These are identified as TIEOFF_X??Y??.KEEP1 or .KEEP0 (tie to 1, or tie to 0). These are places where the synthesis may find a logic 1, or a logic 0, so as to tie a signal high, or low, as required (for example unused inputs to a function may be specifically directed to exist, not be trimmed no optimized, and thus need to go somewhere). These tie off points represent a functional view of what is going on which is also not necessarily present, nor implemented in the same way as in the hardware itself. Remember that FPGA Editor is a convenient way for the software people to reduce the complexity of the schematics to a functional view of the FPGA device: it is not a schematic, nor even a simplified schematic of the device. Like many other items in FPGA Editor, this is almost 25 years old (!) and is considered "so obvious" that no one ever even thought about documenting it, or even explaining it. I apologize, Austin chestnut wrote: > Hi, > > I ran into a problem which is related to TIEOFF_X0Y31. I opened > FPGA_Editor and see such sites around Xilinx Virtex5. i am wondering > what's this site for? I googled and could not get any infos. > > Thank you, > > AdamArticle: 133488
Verilog doesn't really have a strong notion of types, maybe you are thinking about VHDL or SystemVerilog. ---Matthew Hicks > I just wanted to know whether type casting in verilog is sythesizable > or not? >Article: 133489
Register internal to the CPU or hardware register. What device are you using? ---Matthew Hicks > Hi everybody, > > I am using PPC to configure number of LUTs using HWICAP, my question > is , Is it possible to generate an interrupt internally according to a > change in register value , as i want to do new configuration > depending on this value? > > thanks > FatmaArticle: 133490
I am working with a processor core that is written in VHDL and relies on a BUNCH of IP vendor provided libraries. I was able to build all the required libraries in ActiveHDL and compile the top-level unit. When I went to implement the design in ISE, ActiveHDL didn't transfer over the library files. Hence, both the GUI and command line synthesis runs failed. The libraries use a deepish folder structure, meaning a library is composed of several folders. So adding all the files in ActiveHDL's synthesis options panel isn't an option. Is there any way to get ActiveHDL to transfer over the compilation libraries to the synthesis program? Also, I tried to make an ISE project, but here to the mechanism for adding libraries doesn't seem to support the multi-folder library structure. Is there an easy way to add multi-folder libraries here in ISE? I'm not above editing text files, in fact that is preferred. The only way I get synthesis to work is to use xst from th command line with the elaborate command, but I would like to use the gui and/or ActiveHDL. In addition, is there an easy way to do the same in Synplify? Thanks for the insight, ---Matthew HicksArticle: 133491
I am looking for fpga-dsp-board with USB Interface for hardware-in- loop. I don't think I want to mess with USB. I just want to use some easy to use board which will allow me to transfer data (at high speed) to-fro the board using simple instructions. Any recommendations?Article: 133492
Matthew Hicks wrote:
> I am working with a processor core that is written in VHDL and relies on
> a BUNCH of IP vendor provided libraries. I was able to build all the
> required libraries in ActiveHDL and compile the top-level unit.
Might want to compile and run the vendor testbenches at this point.
> When I
> went to implement the design in ISE, ActiveHDL didn't transfer over the
> library files.
Enter the synthesis file list directly.
-- Mike Treseler
Article: 133493
"beeraka@gmail.com" wrote:
>
> Here is an XAPP that should get you started. There is a TFTP
> server example using lwip which you can use to transfer data
> between the PC and Microblaze. ... snip ...
This is rather pointless without a proper quotation of the original
enquiry, which you have lost by top-posting. Please do not
top-post. Your answer belongs after (or intermixed with) the
quoted material to which you reply, after snipping all irrelevant
material. See the following links:
<http://www.catb.org/~esr/faqs/smart-questions.html>
<http://www.caliburn.nl/topposting.html>
<http://www.netmeister.org/news/learn2quote.html>
<http://cfaj.freeshell.org/google/> (taming google)
--
[mail]: Chuck F (cbfalconer at maineline dot net)
[page]: <http://cbfalconer.home.att.net>
Try the download section.
Article: 133494Hi All, I'm starting to look at building something that will allow me to take screenshots and do video capture of both of the Nintendo DS screens. Amazingly there is actually nothing available that you can buy to do this (publically anyway), so why not build it! I knew I was onto something when I found this... http://home.comcast.net/~olimar/DS/jumbotron/ That was enough to prove to me that if the creator of that is able to grab a screenie so am I (in theory )! Unfortunaltly the creator is either not picking up mails from that address or is being hammered with similar questions and is not responding which leaves a noob like me a bit lost.... Anyway, undetered I'd like to capture a screenshot from one screen and squirt it through an RS232 connection where I can have a simple home made .NET app listening (I'm a .NET developer in the day ) to create a simple *.bmp or similar. I've been eyeing up the Diligent Spartan 3E Starter Board to help out with the project as it has a few handy bits already onboard (namely RS232, VGA (3 bit only I think?) for some simple downsampled ouput and some memory to buffer a frame should I need to). I've isolated the RGB (6 bit each) solder points and found the VSYNC and DCLK (data sampling clock?) solder points as well. According to the page I've found I can simply count the clocks (263 exactly) to find the HSYNC. For reference heres a link to the specs of an LCD that is appently very close to the Nintendo DS ones... http://www.sharpsma.com/Page.aspx/americas/en/part/LQ030B7DD01/ However, I am a total noob (both FPGA + General electronics) and I have some basic questions before proceeding if anybody can help (crosses fingers! ) 1. I'm guessing I just buy the 100 pin breadboard module for the Diligent Spartan 3E Starter Board and pop the RGB + DCLK + VSYNC straight into it? Do I need to check the voltage first or anything to make sure its safe? Will I need to put a ground pin in as theres a GRD solder point on the Nintendo DS PCB? 2. When 'counting clocks' for the HSYNC I'm assuming the author of the page already mentioned was talking about counting the clocks of the DCLK, agree? How would I go about that in Verilog? 3. To build up the frame of data do I just sample the RBG pins every clock cycle? The author of the page already mentioned points out that the bottom screen is read on the rising clock edge and the top on the falling, how do I go about sampling on each edge? If theres ANY other advice you have PLEASE do mention it. Good book etc are always welcome... PeteArticle: 133495
---Matthew Hicks > Matthew Hicks wrote: > >> I am working with a processor core that is written in VHDL and relies >> on a BUNCH of IP vendor provided libraries. I was able to build all >> the required libraries in ActiveHDL and compile the top-level unit. >> > Might want to compile and run the vendor testbenches at this point. > I need to get something running on the dev. board quick so I will take for granted that the IP functions as it should. >> When I >> went to implement the design in ISE, ActiveHDL didn't transfer over >> the >> library files. > Enter the synthesis file list directly. It's not as easy as selecting a bunch of files or folders. I would have to create go to every folder in a library and manually add the files in it. This takes too much time. I found that, for ISE, I can create a .npl file and use the SUBLIB and LIBFILE keywords to build a project files that already has the required libraries loaded. This I can write a script to do, which is good. The problem is, this technique uses an old format and Xilinx's new project file formats are less than human readable/editable. I also worry about possible namespace collisions since all sub folders are combined by ISE into on main library namespace. ---Matthew HicksArticle: 133496
On Jul 1, 5:19 pm, Matthew Hicks <mdhic...@uiuc.edu> wrote: > This takes too much time. I found that, for ISE, I can create a .npl file You've already wasted two and a half hours... get to typing/clicking already! AndyArticle: 133497
Pete, First, you need a common reference between the boards (a "ground") so that they both know what is expected of them. Next, you need to know what the logic voltage levels are: LVCMOS, HSTL, SSTL, What? Are they "rail to rail" (and if so, is that 0 to 3.3 volts? or 0 to 2.5 volts?). This assumes everything is single-ended. If differential, then forget it (too many signal integrity issues ... see below). Then, you need some way to get the signals from point A (the source) to point B (the sink). This is likely to be a ribbon cable, arranged as signal, ground, signal, ground, signal, ground...and so on (basically a whole bunch of 50 ohm transmission lines between source and sink). The Vcco for the Spartan IO bank that is the sink (receives these signals) has to be the same voltage as was used to send them (3.3V, 2.5V, 1.8V, or 1.5V). The IO standard used on the inputs must be one that will "hear" the signals coming down the cable. I would start with LVCMOS, only because for a single ended output, it is pretty basic, and usually works. Now that you have a chance of having the signals get from A to B, find a clock in A that you can use to sync everything at B, and send it over there. If attaching the cable breaks the source, then there are signal integrity issues (loading, and/or reflections), and the problem is harder as you will need a set of buffers right at A to isolate and drive the cable to B. Synchronous design is what you need, asynchronous design using FPGAs is just masochism (and will only result in tears). Just the hardware, AustinArticle: 133498
Trying to design an FPGA from scratch, but not sure how this fpga should be programmed. It is going to be a tile concept fpga with a LUT SRAM architecture. I have the resources to write VHDL/Verilog, netlist it and do the layout(incl. routing), but how do I program this fpga? I guess this is something I am not too clear about. Thanks folksArticle: 133499
Lol, yeah, you're right, but after manually adding the files in ActiveHDL (almost an hour wasted), I found out that I could make it generate a synthesis script (a tcl file) and then I could just modify and run the script. If only AHDL allowed me to load the script back into the synthesis options window. My main gripe with AHDL is that I have to add the libraries twice, once for compilation/simulation and once for implementation. ---Matthew Hicks > On Jul 1, 5:19 pm, Matthew Hicks <mdhic...@uiuc.edu> wrote: > >> This takes too much time. I found that, for ISE, I can create a .npl >> file >> > You've already wasted two and a half hours... get to typing/clicking > already! > > Andy >
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