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"Zhane" <me75@hotmail.com> wrote in message news:e92bb3c9-58a3-4941-938c-6e4587b99d8e@i18g2000prn.googlegroups.com... On Jul 3, 4:54 pm, "Stephan van Beek" <stephan.vanb...@mathworks.nl> wrote: > "Zhane" <m...@hotmail.com> wrote in message > > news:2086f732-c988-42fa-b94d-e56af2454b72@p39g2000prm.googlegroups.com... > > > > > Im trying to make use of the fifo in my Spartan3E starter kit > > > i've added the component declaration and instantiation template as > > instructed in the vho file. but im getting the following error when i > > try to implement the design > > > ERROR:NgdBuild:604 - logical block 'FIFO' with type > > 'fifo_generator_v3_3' could > > not be resolved. A pin name misspelling can cause this, a missing > > edif or ngc > > file, or the misspelling of a type name. Symbol > > 'fifo_generator_v3_3' is not > > supported in target 'spartan3e'. > > > Ive also added "Library XilinxCoreLib;" at my top module, which refers > > to the fifo component. > > > am I missing something? > > Hi, > > this error indicates that the design hierarchy is not complete > most likely there is also an ngc file generated which is the actual > content > of the core for ISE > is this file in the same folder as your ise project? > if not you could set the macro search path to include the folder in > searching for all required files > > Regards, > Stephan >how to set a macro search path? if you right click on implement design > properties > translate properties the macro search path is one of the available options to set, you can also set multiple paths seperated by ; Regards, StephanArticle: 133551
Has anybody used central_dma to copy data between peripherals and processors, or between two buffers in bram mermory. I have added it to the design and configure but, I receive a DMA BUS TIMEOUT. Best RegardsArticle: 133552
On Jul 3, 4:28 am, manuel-loz...@mixmail.com wrote: > Hi thanks for your response. > > Unfortunately this is a PCI card not a MiniPCI. > > Best regards, > Manuel > > On 3 jul, 02:39, Brian Drummond <brian_drumm...@btconnect.com> wrote: > > > On Wed, 2 Jul 2008 03:32:07 -0700 (PDT), manuel-loz...@mixmail.com > > wrote: > > > >Hi, > > > >I'm looking for a minipci card with an FPGA in order to work for some > > >project. The PCI interface should be programmed inside the FPGA apart > > >from other application specific functions. > > > >Unfortunately I have only found standard PCIs > > > >Do anybody know any breadboard mini pci (with or without FPGA) that I > > >can use as starting point. > > > like this perhaps? > > >http://enterpoint.co.uk/moelbryn/minican.html > > > - Brian You may have more luck finding a PC-Card (sometimes known as CardBus or PCMCIA card) form factor with FPGA. Is this for a notebook computer?Article: 133553
On Thu, 3 Jul 2008 01:28:45 -0700 (PDT), manuel-lozano@mixmail.com wrote: >Hi thanks for your response. > >Unfortunately this is a PCI card not a MiniPCI. > >Best regards, >Manuel Oh heck. Another standard variant on PCI, to add to CardBus, CompactPCI and PC104. (all of which DO have FPGA cards available). In which case you may have to either use a commercial board (as previously mentioned) with a PCI to miniPCI adapter, or use it as a starting point for your own PCB layout. Or contact the manufacturer for a modified version; they may be interested if this is a commercial project. At one stage the schematic and PCB layout for another FPGA board were available for download, which would have made a good starting point, but it now appears to be only available for sale. http://www.fpga4fun.com/PCI.html - BrianArticle: 133554
Hi, I need to ensure that two FFs are placed close to each other. Does anybody know if it's possible? Can I use any constraints in my UCF, or any attributes of signals? ThanksArticle: 133555
Hi I wanna use an external function generator to feed the FPGA with the clock signal. I have come across a function generator from TTi (TG330). http://www.tti-test.com/products-tti/text-pages/gen-tg300.htm So I am wondering if this device is suitable to generate a stable clock signal or if I will run into trouble. Maybe there are other, better devices out there that I could use for my purposes? I wanna run the implementation at a very low frequency of around 1 MHz. Thanks!Article: 133556
On Jul 3, 6:42 am, Tiago Noronha <tiago...@gmail.com> wrote: > Hi, > > I need to ensure that two FFs are placed close to each other. Does > anybody know if it's possible? Can I use any constraints in my UCF, or > any attributes of signals? > > Thanks Yes you can do that. You can use a relative location constraint, or and area group constraint to do that. For the details of how to do it, refer to the Xilinx constraint guide. It is included in the ISE distribution. It should be located at: $Xilinx\doc\usenglish\books\docs\cgd\cgd.pdf Regards, John McCaskill www.FasterTechnology.comArticle: 133557
On Jul 3, 7:43=A0pm, "Stephan van Beek" <stephan.vanb...@mathworks.nl> wrote: > "Zhane" <m...@hotmail.com> wrote in message > > news:e92bb3c9-58a3-4941-938c-6e4587b99d8e@i18g2000prn.googlegroups.com... > On Jul 3, 4:54 pm, "Stephan van Beek" <stephan.vanb...@mathworks.nl> > wrote: > > > > > "Zhane" <m...@hotmail.com> wrote in message > > >news:2086f732-c988-42fa-b94d-e56af2454b72@p39g2000prm.googlegroups.com..= . > > > > Im trying to make use of the fifo in my Spartan3E starter kit > > > > i've added the component declaration and instantiation template as > > > instructed in the vho file. but im getting the following error when i > > > try to implement the design > > > > ERROR:NgdBuild:604 - logical block 'FIFO' with type > > > 'fifo_generator_v3_3' could > > > not be resolved. A pin name misspelling can cause this, a missing > > > edif or ngc > > > file, or the misspelling of a type name. Symbol > > > 'fifo_generator_v3_3' is not > > > supported in target 'spartan3e'. > > > > Ive also added "Library XilinxCoreLib;" at my top module, which refer= s > > > to the fifo component. > > > > am I missing something? > > > Hi, > > > this error indicates that the design hierarchy is not complete > > most likely there is also an ngc file generated which is the actual > > content > > of the core for ISE > > is this file in the same folder as your ise project? > > if not you could set the macro search path to include the folder in > > searching for all required files > > > Regards, > > Stephan > >how to set a macro search path? > > if you right click on implement design > properties > translate propertie= s > the macro search path is one of the available options to set, you can als= o > set multiple paths seperated by ; > > Regards, > Stephan ooo it searches every sub directories?Article: 133558
Hi, I know that it is possible to put multiple microblaze in a virtexIIPro. I am trying to design one architecture with two microblaze and two bram. When I try to generate Addresses, xps returns error because it couldn't work with multiple processors. So I decide to map address manually, but xps still returns errors and linker script doesn't recognize the second bram. If linker script doesn't recognize this bram, how could I download the executable.elf to this bram. Could someone inform me about the best way to build this design? Best Regards PabloArticle: 133559
Rob Berger wrote:
> Hi
>
> I wanna use an external function generator to feed the FPGA with
> the clock signal. I have come across a function generator from TTi (TG330).
>
> http://www.tti-test.com/products-tti/text-pages/gen-tg300.htm
> ....
>
> Maybe there are other, better devices out there that I could use for my
> purposes? I wanna run the implementation at a very low frequency of
> around 1 MHz.
I use a TI eZ430-F2013 USB development kit as a clock generator in
my lab. This MSP430 processor has a programmable clock on-chip and
you can configure the chip very simply to emit the clock signal on
a digital output pin. You do need to code a little program, though
-- no nice front panel as on a function generator, but also much
cheaper. I got my device free from a TI promotional seminar...
HTH,
--
Niklas Holsti
Tidorum Ltd
niklas holsti tidorum fi
. @ .
Article: 133560On Jul 1, 2:00 pm, austin <aus...@xilinx.com> wrote: > Adam, > > OK, I opened up FPGA Editor, so I now think I know what you are asking. > > Associated with each CLB, is an interconnect block. This block > represents a convenient way to visualize the interconnection resources > in the FPGA (the actual schematics, layout, and physical placement is > entirely different). > > This "switch box" has inputs and outputs. There is a little block to > the right, and to the top of the switch box, which has some logic 0, and > logic 1 points. These are identified as TIEOFF_X??Y??.KEEP1 or .KEEP0 > (tie to 1, or tie to 0). > > These are places where the synthesis may find a logic 1, or a logic 0, > so as to tie a signal high, or low, as required (for example unused > inputs to a function may be specifically directed to exist, not be > trimmed no optimized, and thus need to go somewhere). > > These tie off points represent a functional view of what is going on > which is also not necessarily present, nor implemented in the same way > as in the hardware itself. > > Remember that FPGA Editor is a convenient way for the software people to > reduce the complexity of the schematics to a functional view of the FPGA > device: it is not a schematic, nor even a simplified schematic of the > device. > > Like many other items in FPGA Editor, this is almost 25 years old (!) > and is considered "so obvious" that no one ever even thought about > documenting it, or even explaining it. > > I apologize, > > Austin > > chestnut wrote: > > Hi, > > > I ran into a problem which is related to TIEOFF_X0Y31. I opened > > FPGA_Editor and see such sites around Xilinx Virtex5. i am wondering > > what's this site for? I googled and could not get any infos. > > > Thank you, > > >Adam Austin, thank you for your replies. it is crystal clear to me now. I always thought myself of a FPGA veteran until I went through your replies. there are still FPGA commonsense which are blind to me... thank you again and have a good holiday, AdamArticle: 133561
Hi Ausitn & Peter and whoever else from Xilinx is listening, I need your opinion on how number of reheating cycles with or without reballing, provided the rework is done professionally using proper equipment, will or will not affect long-time reliability. I am particularly interested in any related information with regards to the commercial grade of Virtex-4 FPGAs. Thanks, /MikhailArticle: 133562
On Jul 3, 7:39 am, Pablo <pbantu...@gmail.com> wrote: > Hello, > > I ask for people who has detected some problem in programs running > in External Memory (Micron DDR SDRAM). These problems are about > "printf" and "malloc" functions, and the results are unexpected. > > Best Regards for your answers. I know little about software so my suggestions are from hardware perspective. are you sure that your DDR memory controller is functioning properly? can you pass some memory tests ?Article: 133563
On Jul 3, 10:33=A0am, Niklas Holsti <niklas.hol...@tidorum.invalid> wrote: > Rob Berger wrote: > > Hi > > > I wanna use an external function generator to feed the FPGA with > > the clock signal. I have come across a function generator from TTi (TG3= 30). > > >http://www.tti-test.com/products-tti/text-pages/gen-tg300.htm > > .... > > > Maybe there are other, better devices out there that I could use for my > > purposes? I wanna run the implementation at a very low frequency of > > around 1 MHz. > > I use a TI eZ430-F2013 USB development kit as a clock generator in > my lab. This MSP430 processor has a programmable clock on-chip and > you can configure the chip very simply to emit the clock signal on > a digital output pin. You do need to code a little program, though > -- no nice front panel as on a function generator, but also much > cheaper. I got my device free from a TI promotional seminar... > > HTH, > > -- > Niklas Holsti > Tidorum Ltd > niklas holsti tidorum fi > =A0 =A0 =A0 =A0. =A0 =A0 =A0@ =A0 =A0 =A0 . You do not need anything fancy to clock the FPGA. You can use any crystal oscillator for about $1 and you can divide the frequency down with a few internal flip-flops. You can also build an oscillator with two external resistors plus a capacitor (see my 'six easy pieces"),which is remarkably stable. It all depends on your requirements... Peter AlfkeArticle: 133564
"chestnut" <adam0818@gmail.com> wrote in message news:be05ef05-6da1-4c93-8e3c-5f3b8103cbb4@m45g2000hsb.googlegroups.com... > On Jul 3, 7:39 am, Pablo <pbantu...@gmail.com> wrote: >> Hello, >> >> I ask for people who has detected some problem in programs running >> in External Memory (Micron DDR SDRAM). These problems are about >> "printf" and "malloc" functions, and the results are unexpected. >> >> Best Regards for your answers. > > I know little about software so my suggestions are from hardware > perspective. are you sure that your DDR memory > controller is functioning properly? can you pass some memory tests ? If it's a Microblaze, Xilinx documents say the libc or stdio stuff is not re-entrant. You'll have to add your own locks if you have multiple threads writing to stdout, for example.Article: 133565
On Thu, 03 Jul 2008 15:39:04 +0100, Rob Berger <Rob_Berger@yahoo.co.uk> wrote: >Hi > >I wanna use an external function generator to feed the FPGA with >the clock signal. I have come across a function generator from TTi (TG330). > >http://www.tti-test.com/products-tti/text-pages/gen-tg300.htm > >So I am wondering if this device is suitable to generate a stable >clock signal or if I will run into trouble. It's not suitable. The maximum output frequency is given as 3 MHz whereas a typical FPGA clock frequency would be in the 50-100MHz region. You can multiply clock rates internally with a DCM (Xilinx; Altera has a roughly equivalent PLL); but the Xilinx DCM typically works with input frequencies above 25 MHz. Even if you don't need any performance from the FPGA and a 3MHz clock is sufficient, I'd be worried about the very slow "< 100ns" edges this thing claims to generate. Slow ramps like that, in the presence of noise, can generate several clock edges where you only wanted one. If you MUST use it, feed it through an external buffer to the FPGA. Go with Peter's suggestion or Niklas's; or wire up the four corner pins on a DIP14 socket and you can plug in any crystal oscillator you want. - BrianArticle: 133566
Can anyone help me check my codes? I implemented it, but when I run on Modelsim, there doesnt seem to be any data coming out of my FIFO during the clock cycles... my source is at http://www.mediafire.com/?nxnttnn1nbqArticle: 133567
On Jul 4, 10:44=A0am, Zhane <m...@hotmail.com> wrote: > Can anyone help me check my codes? > > I implemented it, but when I run on Modelsim, there doesnt seem to be > any data coming out of my FIFO during the clock cycles... > > my source is athttp://www.mediafire.com/?nxnttnn1nbq im getting this error when I do my simulation with Modelsim # ** Warning: Design size of 11167 statements or 0 non-Xilinx leaf instances exceeds ModelSim XE-Starter recommended capacity. in my simulation it looks as if nothing has been written into the FIFO even when I enable wr_enArticle: 133568
"Zhane" <me75@hotmail.com> wrote in message news:39230673-45bb-4f5e-ac0f-57cc904713b3@i36g2000prf.googlegroups.com... > im getting this error when I do my simulation with Modelsim > # ** Warning: Design size of 11167 statements or 0 non-Xilinx leaf > instances exceeds ModelSim XE-Starter recommended capacity. Wich means that your ModelSim license doesn't allow for simulating design of such size. /MikhailArticle: 133569
On Jul 4, 11:43=A0am, "MM" <mb...@yahoo.com> wrote: > "Zhane" <m...@hotmail.com> wrote in message > > news:39230673-45bb-4f5e-ac0f-57cc904713b3@i36g2000prf.googlegroups.com... > > > im getting this error when I do my simulation with Modelsim > > # ** Warning: Design size of 11167 statements or 0 non-Xilinx leaf > > instances exceeds ModelSim XE-Starter recommended capacity. > > Wich means that your ModelSim license doesn't allow for simulating design= of > such size. > > /Mikhail hmm so is my codes right?Article: 133570
On Jul 4, 1:04=A0pm, Zhane <m...@hotmail.com> wrote: > On Jul 4, 11:43=A0am, "MM" <mb...@yahoo.com> wrote: > > > "Zhane" <m...@hotmail.com> wrote in message > > >news:39230673-45bb-4f5e-ac0f-57cc904713b3@i36g2000prf.googlegroups.com..= . > > > > im getting this error when I do my simulation with Modelsim > > > # ** Warning: Design size of 11167 statements or 0 non-Xilinx leaf > > > instances exceeds ModelSim XE-Starter recommended capacity. > > > Wich means that your ModelSim license doesn't allow for simulating desi= gn of > > such size. > > > /Mikhail > > hmm so is my codes right? or rather... how can I simulate the FIFO?Article: 133571
Dear Freinds I came across a website which conducts Free Webinars on PMP Certification (Project Management Institute, USA) Awareness and The Roadmap. It proved to be quite useful. This Training Institute also provides live online lectures on PMP Certification Preparation at very competitive rates and also have full website support as Contents / Downloads / Question Bank of Over 1200 questions / Online support for all your queries. If you are interested in becoming a PMP Certified Professional - do visit the following link http://www.pmsoftglobal.com/Free-serv-Webinars.html MakarandArticle: 133572
> >how to set a macro search path? > > if you right click on implement design > properties > translate properties > the macro search path is one of the available options to set, you can also > set multiple paths seperated by ; > > Regards, > Stephan ooo it searches every sub directories? ==== No I don't think so, but you can add multiple paths. StephanArticle: 133573
On Jul 1, 11:31=A0pm, phxag...@gmail.com wrote: > Thank you all for your inputs on this subject. You are right, I would > first want to evaluate what I am signing-up for and thats exactly what > I am doing in this group :) It would definitely not go all the way > into fabrication, but a proof of concept would be good enough. The > idea is to create a novel tile architecture that does not exist > today. > > Question for Mike. I thought Dagger was a web-based tool. Can I really > modify it? I just did a search, skimmed a poster and a user's manual, so I don't know very much about it. The thing is, if you're in academic research, you can ask the people who developed Dagger for their source code, and they'll probably be happy to share it with you. That's the way it usually works. But really, what sort of class inspires such a complicated project? Cheers, MikeArticle: 133574
On Jul 3, 2:32=A0pm, Pablo <pbantu...@gmail.com> wrote: > Has anybody used central_dma to copy data between peripherals and > processors, or between two buffers in bram mermory. I have added it to > the design and configure but, I receive a DMA BUS TIMEOUT. > > Best Regards Obviously one of the addresses you are trying to access does not exist. Check the address map. Otherwise the CENTRAL_DMA has low performance since the data needs to travel twice: source_peripheral -> DMA and DMA -> destination_peripheral Not to mention that is not capable of long bursts. Cheers, Guru
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Compare FPGA features and resources
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Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z