Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Hi everyone, My Spartan-3A DSP kit has grown an Analog/Digital converter (AD9218 dual 10bit 65MS/s) on its SystemAce port (the EXP connectors were a bit too much of a hassle to solder). And I'm running into all kinds of funny timing issues, so I'd like to once again ask for a little help. I run the on-board 125MHz clock through a DCM to get a 62.5MHz clock. This clock goes out of a pad towards the sampler, and the bits come back from the sampler. But, depending on rather unrelated changes in my VHDL, sometimes I get perfect samples showing the sine output from my signal generator, and sometimes there are all kinds of 'jaggies' indicating that I'm catching some bits either too late or too early. But I also get 'Xst:2169 HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources', and "Route:455 - CLK Net:adc_clk_OBUF may have excessive skew because 1 clk pins and 1 non_clk pins failed to route using a clk template' As an aside, pet peeve: why do the Xilinx error messages never tell you *which* clock is not getting a BUFG, or *which* clock ended up on a SideBufg - it's always "Some clock" How would one properly specify the timing constraints for something like this? The examples the constraint guide seem to assume that both clock and data arrive at the FPGA from an external source, instead of the FPGA clocking such a source. The Xilinx documentation is great at explaining which menu item to click or what syntax to use to specify timing constraints, but I'm looking for something that tells me what these things actually -mean-. Any pointers greatly appreciated. Regards, Paul Boven.Article: 135901
hello, I think you have a timing issue. are you using FPGA to generate a 62.5MHz clk to the AD9218 and then use the same clock to latch the sampler data inside FPGA? if so, you need properly constraint this clock in your design. can you send me your top file so that I can help you figure out how to constraint this clock? I agree with you. Xilinx user constraint guide is written like a law, not convincing people, sometimes, just confusing people.. adam On Oct 21, 8:53 am, Paul Boven <p.bo...@xs4all.nl> wrote: > Hi everyone, > > My Spartan-3A DSP kit has grown an Analog/Digital converter (AD9218 dual > 10bit 65MS/s) on its SystemAce port (the EXP connectors were a bit too > much of a hassle to solder). > > And I'm running into all kinds of funny timing issues, so I'd like to > once again ask for a little help. > > I run the on-board 125MHz clock through a DCM to get a 62.5MHz clock. > This clock goes out of a pad towards the sampler, and the bits come back > from the sampler. But, depending on rather unrelated changes in my VHDL, > sometimes I get perfect samples showing the sine output from my signal > generator, and sometimes there are all kinds of 'jaggies' indicating > that I'm catching some bits either too late or too early. > > But I also get 'Xst:2169 HDL ADVISOR - Some clock signals were not > automatically buffered by XST with BUFG/BUFR resources', and "Route:455 > - CLK Net:adc_clk_OBUF may have excessive skew because 1 clk pins and 1 > non_clk pins failed to route using a clk template' > > As an aside, pet peeve: why do the Xilinx error messages never tell you > *which* clock is not getting a BUFG, or *which* clock ended up on a > SideBufg - it's always "Some clock" > > How would one properly specify the timing constraints for something like > this? The examples the constraint guide seem to assume that both clock > and data arrive at the FPGA from an external source, instead of the FPGA > clocking such a source. > > The Xilinx documentation is great at explaining which menu item to click > or what syntax to use to specify timing constraints, but I'm looking for > something that tells me what these things actually -mean-. Any pointers > greatly appreciated. > > Regards, Paul Boven.Article: 135902
On Oct 21, 7:53 am, Paul Boven <p.bo...@xs4all.nl> wrote: > Hi everyone, > > My Spartan-3A DSP kit has grown an Analog/Digital converter (AD9218 dual > 10bit 65MS/s) on its SystemAce port (the EXP connectors were a bit too > much of a hassle to solder). > > And I'm running into all kinds of funny timing issues, so I'd like to > once again ask for a little help. > > I run the on-board 125MHz clock through a DCM to get a 62.5MHz clock. > This clock goes out of a pad towards the sampler, and the bits come back > from the sampler. But, depending on rather unrelated changes in my VHDL, > sometimes I get perfect samples showing the sine output from my signal > generator, and sometimes there are all kinds of 'jaggies' indicating > that I'm catching some bits either too late or too early. > > But I also get 'Xst:2169 HDL ADVISOR - Some clock signals were not > automatically buffered by XST with BUFG/BUFR resources', and "Route:455 > - CLK Net:adc_clk_OBUF may have excessive skew because 1 clk pins and 1 > non_clk pins failed to route using a clk template' > > As an aside, pet peeve: why do the Xilinx error messages never tell you > *which* clock is not getting a BUFG, or *which* clock ended up on a > SideBufg - it's always "Some clock" > > How would one properly specify the timing constraints for something like > this? The examples the constraint guide seem to assume that both clock > and data arrive at the FPGA from an external source, instead of the FPGA > clocking such a source. > > The Xilinx documentation is great at explaining which menu item to click > or what syntax to use to specify timing constraints, but I'm looking for > something that tells me what these things actually -mean-. Any pointers > greatly appreciated. > > Regards, Paul Boven. Until you provide timing constraints, you will continue to get erratic results. Use the clock-to-data-out time of your sampler to derive constraints for the data and clock relationships. Also make sure that you are using the IOB registers to capture the data; this will minimize timing problems due to design dependent routing. The Xilinx documentation provides enough examples to convey the meaning of the timing constraints. Are you using a UCF file to supply the constraints? Darol KlawetterArticle: 135903
On Oct 18, 5:44 am, cid <nihons...@gmail.com> wrote: > I was also thinking of working on my own fpga projects to have my resume/ > skillset stand out. Personal projects like that may or may not get any attention from a company, but they give you the confidence to talk about the technology as someone who really knows it on a practical level.Article: 135904
On Oct 20, 2:39=A0pm, Darol Klawetter <darol.klawet...@l-3com.com>
wrote:
> On Oct 20, 9:12 am, "sebastian.schuep...@gmail.com"
>
> <sebastian.schuep...@googlemail.com> wrote:
> > Hi,
>
> > I would like to connect an external clk source (i.e. signal generator)
> > to my virtex 2 pro board (xupv2p)
> > The thing is that I didn't really unterstand the concept of
> > differential clocks. Can I just connect one clk source to one input or
> > do i have to have an input for both EXTERNAL_CLOCK_P and
> > EXTERNAL_CLOCK_N. Whats the difference between those.
>
> > Thanks for your help.
> > Sebastian
>
> The differential clock input circuitry of the FPGA measures the
> voltage difference between the two inputs, not their absolute voltage
> level with respect to a common reference (e.g. ground). The advantage
> of differential clocks is greater noise immunity. If the differential
> pair is routed correctly, then a noise source will couple into both
> inputs, affecting the common mode voltage but not the voltage
> difference.
>
> Also, differential pairs cancel out self noise because each signal of
> the pair emits an EM field that is of opposite phase with respect to
> the other. There's plenty of info on the web if you want more detail.
>
> Darol Klawetter
I am regularly using the pin "EXTERNAL_CLOCK_P" for my purpose
and I am leaving the other node "EXTERNAL_CLOCK_N" unconnected.It
works.In this case in the ucf file you will have to use the standard
"LVCMOS25" or LVTTL instead of "LVDS".
-Pratap
Article: 135905On Oct 17, 6:59 am, Owen Duffy <n...@no.where> wrote: > > II assembler. This POF will have your whole design in it, including > > the new UFM contents. > > That is a problem, I do not want to ship the design part of the POF to > end users. I cannot see a way in Quartus II v8 to make a POF file that > does not include the CFM. Make a jam file and study it in a text editor. There are seperate 'routines' in the file for CFM and UFM, and you should be able to delete/disable the ones you don't want. In fact, you should be able to reverse the UFM data encoding blob (feed it known test cases) and come up with a script that does what you need.Article: 135906
On Oct 20, 8:49=A0pm, Peter Alfke <al...@sbcglobal.net> wrote: > On Oct 20, 3:30=A0pm, Pratap <pratap.i...@gmail.com> wrote: > > > > > On Oct 13, 6:59=A0am, General Schvantzkopf <schvantzk...@yahoo.com> > > wrote:> On Wed, 08 Oct 2008 07:35:44 -0700, Pratap wrote: > > > > Hi, > > > > I want to synthesize a delay of around 10 ns in Xilinx Virtex2 Pro.= So I > > > > put around 200 inverters in series and get the desired delay. So I = did > > > > port map the BASIC cell "INV" according to the XST settings. But wh= en i > > > > place and route I guess the optimizer removes all the intermediate > > > > buffers and I get very less delay when I do a post route simulation= . > > > > How can I get rid of this problem? > > > Hi, > > Can you please send me some good material on DCM? > > I actually require to generating delays around 0 ps by having a > > passive > > delay of around 1 period and then increasing and decreasing the input > > frequency slightly.Can DCM help me in that case? > > -pratap > > > > > Thanks in advance. > > > > -Pratap > > > > Do you need a delay or can you accomplish your task with a phase shif= ted > > > clock? If you can use a phase shifted clock from the DCM that's a muc= h > > > better way of doing it because it's stable over temperature and proce= ss > > > and because it won't change when the tools change. > > > > If you must build a delay line from buffers you will have to directly > > > place them because the routing delays are much more important then th= e LUT > > > delays. Also you should use an XOR instead of an inverter. Tie one si= de of > > > the XOR to a flop which presets to 1 on reset and then clocks a zero = into > > > the data input. This will be enough to fool XST and PAR into leaving = the > > > components alone. > > The important question is: Who decides when to start your delay. > If you can wait until an oscillator has a rising edge, then there are > many high-quality solutions, especially when you know the delay value > well beforehand. With the help of frequency synthesis and PLLs, you > can generate a delay with very fine resolution, even below a > picosecond. (Of course you lose that accuracy as you propagate through > more logic.) > If, however, you need to be the master of starting the delay, then you > are much more constrained, and your best bet is what Virtex-4 and > later did by cascading analog delay elements, and servo-controlling > their composite delay. And the inherent accuracy will be not perfect, > with an error of a nanosecond, unless you get really creative. > Peter Alfke, lurking from home... Hi, I read the manual of Virtex2P for the DCM.But I found it not useful for me. All I require is a fixed delay of around 10ns.The precision doesn't matter.But it has to be stable.Then if I feed a square wave of say 10ns period.I get the effective delay between the original and the delayed signal as 0 ps. If I increase the input period to 10.001ps, I get the delay to be 1ps and similarly for an input period of 9.999ns I get a delay of -1ps. So all I require here is a fixed constant delay like that of a passive element. When I synthesize a bunch of cascaded even number of inverters, I get the synthesized technology schematic as expected too.Even after the "translate" phase it i in tact. But after the "map" phase many signals disappear.I guess it does some optimization in this step and removes all the intermediate signals and delays.is there any way to tell the mapper not to optimize? Thanks, PratapArticle: 135907
I have setup the latest ISE with latest updates. I can't seem to find the ISIM tool. We normally run Aldec, but they have gotten a little behind and just became partners with Xilinx. I wanted to see if ISIM could be used. Looking on the Xilinx site, it seems like the full blown copy of ISE should have at least the lite version of ISIM and Planahead. I loaded ISE from the DVD but we don't buy the version with the simulator. I can't seem to find a seperate download for ISIM. Do I need to download the web version to evaluate ISIM? I tried to call Xilinx support and was told I can't talk to anyone in tech support and have to use the webcase. We currently have 5 seats so I guess we are no longer considered a big enough customer. I tied to use the webcase but need to open a new account which takes some 30 minutes to setup. So, if you can halp me figure out how to get ISIM running it would be great.Article: 135908
Pratap wrote: > > Hi, > I read the manual of Virtex2P for the DCM.But I found it not useful > for me. > All I require is a fixed delay of around 10ns.The precision doesn't > matter.But it has to be stable.Then if I feed a square wave of say > 10ns period.I get the effective delay between the original and the > delayed signal as 0 ps. If I increase the input period to 10.001ps, I > get the delay to be 1ps and similarly for an input period of 9.999ns I > get a delay of -1ps. So all I require here is a fixed constant delay > like that of a passive element. > When I synthesize a bunch of cascaded even number of inverters, I get > the synthesized technology schematic as expected too.Even after the > "translate" phase it i in tact. But after the "map" phase many signals > disappear.I guess it does some optimization in this step and removes > all the intermediate signals and delays.is there any way to tell the > mapper not to optimize? > Thanks, > Pratap You will not get a super-stable delay in an FPGA because these devices are not designed as timing elements but instead are intended to provide extreme functionality. If you implement a series of inverters with LUT primitives (which should not get optimized out) you still end up with differences due to global or local temperature changes on the die and due to local activity in the form of minute changes in the voltage rail or coupled energy from other nearby activity that are fine in the digital world. The analog world of transition thresholds are a different matter. If you need picosecond level consistency, develop a discrete analog or analog/digital hybrid solution to achieve your goals. You will need to pay special attention to power and to electromagnetic coupling and either need a very well behaved feedback loop to keep the delay solid to the picosecond level or you'll need to regulate the temperature of the circuit (such as with ovenized oscillators) and maintain a smooth power consumption. I've implemented delay elements in an FPGA but I've been allowed more slop and performed my own adjustments to the 100 ps (or smaller) level using carry chain elements directly feeding a series of registers. It's not a variable delay to another part of the circuit and it's certainly 2 orders of magnitude (base 10) from the picosecond level of control you're asking for. The delay maintenance is not a simple task, introduces jitter, and shows signs of "swaying" back and forth under normal operation. Go analog. Or figure out what you really need, not just what you dream up. - John_HArticle: 135909
cs_posting@hotmail.com wrote in news:728708cd-fc4a-49af-922c-a36ee9e83347 @l76g2000hse.googlegroups.com: > On Oct 17, 6:59 am, Owen Duffy <n...@no.where> wrote: > >> > II assembler. This POF will have your whole design in it, including >> > the new UFM contents. >> >> That is a problem, I do not want to ship the design part of the POF to >> end users. I cannot see a way in Quartus II v8 to make a POF file that >> does not include the CFM. > > Make a jam file and study it in a text editor. There are seperate > 'routines' in the file for CFM and UFM, and you should be able to > delete/disable the ones you don't want. In fact, you should be able > to reverse the UFM data encoding blob (feed it known test cases) and > come up with a script that does what you need. > > Thanks, I had examined the JAM file as a possible solution to the problem. It seems to me that the JAM file incorporates chip specific timing and architecture in its content, and I did see the opportunity to nobble it so that it would not install a CFM, delete the CFM content, and write a utility to re-encode the UFM and insert it in the file. I could do this for every chip in the MAX II family, and I might have a tailored solution that might work... but a maintenance nightmare. When Altera authored the document http://www.altera.ru/Disks/Altera% 20Documentation%20Library/literature/hb/max2/max2_mii51011.pdf , they understood what end users need, and they understood that the best person to write a Jam composer (the "UFM HEX to Jam Utility" in the article) to convert a hex file to a JAM file is the chip manufacturer. I was casting around here to see if I hadn't missed something. Thanks for taking the time to respond, appreciated. OwenArticle: 135910
In order to implement an advanced clocking scheme for 8 Aurora cores on a Virtex 5, do I need to use the DRPs of each one to set the clock source selection bits or is there another (simpler) way? TIA, Roger.Article: 135911
----- Original Message ----- From: "Paul Boven" <p.boven@xs4all.nl> Newsgroups: comp.arch.fpga Sent: Tuesday, October 21, 2008 1:53 PM Subject: Question on timing constraints > Hi everyone, > > My Spartan-3A DSP kit has grown an Analog/Digital converter (AD9218 dual > 10bit 65MS/s) on its SystemAce port (the EXP connectors were a bit too > much of a hassle to solder). > > And I'm running into all kinds of funny timing issues, so I'd like to once > again ask for a little help. > > I run the on-board 125MHz clock through a DCM to get a 62.5MHz clock. This > clock goes out of a pad towards the sampler, and the bits come back from > the sampler. But, depending on rather unrelated changes in my VHDL, > sometimes I get perfect samples showing the sine output from my signal > generator, and sometimes there are all kinds of 'jaggies' indicating that > I'm catching some bits either too late or too early. > Paul, OK, I guess your 62.5M clock is coming from a bufg, right? Make the clock that goes to your ADC by using the output IOB's DDR registers with the clock connected to the DDR's clock, D1 <= '1' and D2 <= '2'. Also, make sure that the data from the ADC is clocked into your design using the FFs in the IOBs where the data comes in. This way your clock out and clock in are quite tightly constrained and the P&R variability should disappear. There are also delay elements in the input IOBs that are there to provide the 'zero hold time' feature. You may or may not want to adjust whether these are used after thinking about your timing. Good luck, Syms.Article: 135912
On Tue, 21 Oct 2008 14:53:37 +0200, Paul Boven <p.boven@xs4all.nl> wrote: >Hi everyone, > >My Spartan-3A DSP kit has grown an Analog/Digital converter (AD9218 dual >10bit 65MS/s) on its SystemAce port (the EXP connectors were a bit too >much of a hassle to solder). > >And I'm running into all kinds of funny timing issues, so I'd like to >once again ask for a little help. Symon is right about making sure you use the FFs in the IOBs where appropriate. Just one further tip: the .mrp Mapper report file contains the information about which FFs/registers were pushed into the IOBs (in a section near the end). It isn't always what you expect, and it can take some fiddling to persuade the tools you want IOB registers. For example; some devices need a separate tri-state register per bit of output and an active low tristate signal. Also, you may need to attach "keep" attributes to signals, and/or "equivalent-register-removal" attributes set to "no" to specific signals to prevent the tools from helpfully removing redundant registers... - BrianArticle: 135913
On Tue, 21 Oct 2008 08:52:44 -0700 (PDT), "lecroy7200@chek.com" <lecroy7200@chek.com> wrote: >I have setup the latest ISE with latest updates. I can't seem to find >the ISIM tool. We normally run Aldec, but they have gotten a little >behind and just became partners with Xilinx. I wanted to see if ISIM >could be used. > >Looking on the Xilinx site, it seems like the full blown copy of ISE >should have at least the lite version of ISIM and Planahead. I >loaded ISE from the DVD but we don't buy the version with the >simulator. I can't seem to find a seperate download for ISIM. > >Do I need to download the web version to evaluate ISIM? > It's built in, (to both full ISE 10.1 and Webpack) but it took me most of a day to find too... In ISE, the "sources" window has a little drop down box at the top, labelled "Sources for:" - select "Behavioural Simulation" here and the simulator appears in the "Processes" window instead of the synth/PAR tools. I seem to remember I had to set an option somewhere to choose between ISIM and Modelsim, but can't remember where. ISIM is still a bit ropey compared with Modelsim, but when it doesn't crash it seems to give accurate simulation results. The "Lite" version handles moderately large designs but isn't up to post-route simulations or EDK projects (it slows down to about a nanosecond per second) - BrianArticle: 135914
On Oct 19, 3:19=A0am, Muzaffer Kal <k...@dspia.com> wrote: > On Sat, 18 Oct 2008 13:33:33 -0700 (PDT), Fred > > <fred__blo...@lycos.com> wrote: > >> Not really. There is 4b/5b encoding to go from 4 bits at 25 MHz (ie > >> 100mb/s) and then there is a scrambler at 125 MHz. This scrambler is a > >> self-synchronizing one and there is no CRC associated with it. At 4bit > >> stage if there is no packet data (ie if MAC is not sending anything) a > >> 5 bit IDLE code is inserted in the bitstream continuously. > > >I've come across 4b/5b encoding elsewhere and don't feel it's going to > >be an issue, the legal codes, the Start and End of Stream Delimiter > >should be easy to code. > > Yes, there is nothing interesting about the encoding in the > transmitter. > > >Not sure what you mean by self-synchronizing. =A0This is something I > >need to look into further. > > Sorry about the confusion, I meant that the descrambler at the > receiver is self-synchronizing. The scrambler at the transmitter is > just a standard scrambler. > > >I though the 5 bit idle code was all 1's but that these were also > >scrambled? > > Yes the idle code is 5 bits of 1 which is inserted in between actual > packet data encoded with 4b5b. Then the resulting 125 Mb/s bit stream > is scrambled and mlt-3 encoded before being driven to the wire. > Muzaffer Kal > > ASIC/FPGA Design Services > DSPIA INC.http://www.dspia.com I'm rapidly coming to the conclusion that the purchase of a PHY, given their cost, might be a smart move. Sad really because I would have liked to have coded the whole system in a FPGA. A VHDL test bench would have been ideal!!Article: 135915
"Symon" <symon_brewer@hotmail.com> wrote in message news:gdllcb$1su$1@aioe.org... > connected to the DDR's clock, D1 <= '1' and D2 <= '2'. Also, make sure > that D'oh, D2 <= '0' !Article: 135916
All-
In an existing XC3S-FG676 design, which has worked fine for a couple
of years, we have recently enabled some previously unused pins.
Whenever we build the updated logic, we get this message:
ERROR:Place:207 - Due to SelectIO banking constraints, the IOBs in
your design
cannot be automatically placed.
Each Group of a specific Standard is listed.
Standard LVCMOS33 (Vref=NR Vcco=3.30 Terminate=none) 336 IOs, 336
locked.
(59-Inputs, 170-Outputs, 107-Bidirectional)
Standard LVCMOS25 (Vref=NR Vcco=2.50 Terminate=none) 7 IOs, 0
locked.
(0-Inputs, 7-Outputs, 0-Bidirectional)
When we look at the Pad Report, we can't see any pins other than 3.3V
(with exception of pre-defined VCCINT, VCCO_X, and VCCAUX pins).
There are no LVCMOS25 pins listed. In the .ucf file, we did not
define any LVCMOS25 pins and included IOSTANDARD = LVCMOS33 for all
used pins.
What can cause this error? How do we know exactly which bank and/or
pins to which XST is referring? How can we debug this?
We're using ISE v7.1.04i. I can send post the full XST report if
needed.
-Jeff
Article: 135917
Jeff Brower <jbro...@signalogic.com> wrote:
>
> When we look at the Pad Report, we can't see any pins other than 3.3V
> (with exception of pre-defined VCCINT, VCCO_X, and VCCAUX pins).
> There are no LVCMOS25 pins listed. In the .ucf file, we did not
> define any LVCMOS25 pins and included IOSTANDARD = LVCMOS33 for all
> used pins.
>
> What can cause this error? How do we know exactly which bank and/or
> pins to which XST is referring? How can we debug this?
>
A few years back, I hit a feature in 7.1.04i where unused LOC'd inputs
would default back to LVCMOS25 (instead of using the IOSTANDARD that
had been applied to them) and trip a similar error.
One workaround is to OR any unused inputs together to generate a
dummy
output signal, preventing them from being optimized away. ( A "keep"
and/or "S" {save} attribute on the input signals might also work )
http://groups.google.com/group/comp.arch.fpga/msg/8955e7209e0c3929
Brian
Article: 135918On Oct 21, 4:54 pm, Jeff Brower <jbro...@signalogic.com> wrote: > All- > > In an existing XC3S-FG676 design, which has worked fine for a couple > of years, we have recently enabled some previously unused pins. > Whenever we build the updated logic, we get this message: > > ERROR:Place:207 - Due to SelectIO banking constraints, the IOBs in > your design > cannot be automatically placed. > > Each Group of a specific Standard is listed. > Standard LVCMOS33 (Vref=NR Vcco=3.30 Terminate=none) 336 IOs, 336 > locked. > (59-Inputs, 170-Outputs, 107-Bidirectional) > Standard LVCMOS25 (Vref=NR Vcco=2.50 Terminate=none) 7 IOs, 0 > locked. > (0-Inputs, 7-Outputs, 0-Bidirectional) > > When we look at the Pad Report, we can't see any pins other than 3.3V > (with exception of pre-defined VCCINT, VCCO_X, and VCCAUX pins). > There are no LVCMOS25 pins listed. In the .ucf file, we did not > define any LVCMOS25 pins and included IOSTANDARD = LVCMOS33 for all > used pins. > > What can cause this error? How do we know exactly which bank and/or > pins to which XST is referring? How can we debug this? > > We're using ISE v7.1.04i. I can send post the full XST report if > needed. > > -Jeff IIRC, the pad report contains only the properly placed pads. You'll need to go back to the UCF to figure it out. Have you tried the GUI to nail down all pins? Sometimes it prevents you from making "mistakes", and the error message from it mey be enlightening. Alex.Article: 135919
Much earlier, I wrote: > > My understanding of this is as follows: > > - if you use the IBISheader values by uncommenting the header > for a specific package, you get a generic uncoupled lumped model > with min/typ/max values representative of that package type > > - if you use the .pkg file, you get a coupled lumped model that > models each pin of the package distinctly > > In neither case should you use the Tlines with these newer IBIS > files, as that delay is now included in the lumped package model. > I recently stumbled across a related Answer Record, 21632, whilst seaching for Something Completely Different: http://www.xilinx.com/support/answers/21632.htm " AR #21632 - How do I integrate per pin parasitic package data " (in the .pkg file) provided in the IBIS archive into the IBIS file? BrianArticle: 135920
Hi, Im new to DSP stuff and have a very simple question. Since the multiplier in virtex 5 dsp is 2's complement ... does that mean when using the std_logic_unsigned library, the maximum number of bits A input can have is 24 instead of 25 and 17 instead of 18 for B input? Whereas I can use 25 bits for A and 18 for B by using the std_logic_signed library? thanks.Article: 135921
>
>> It's good to know someone else has managed to use global signals
>> with XST. Now we know it's worth the effort to making it work.
>
> I'll try to extract a working example from some old code
> in the next week or few if I have the time.( My from-scratch
> hack at it just now got me a bunch of XST "undriven signal"
> errors if I try reading the signal for synthesis outside
> the level of hierarchy it's assigned in. )
>
After looking at this again, XST's support of globals
doesn't seem robust enough to use for general in-circuit
probing; in order to read a global signal that's been
assigned, the read seems to need to be within the same
entity as the assignment.
( That said, this technique does work well for simulation,
and XST will happily process those probe assignments without
needing any translate on/off directives or other code edits)
I went back and looked at the code where I'd used this
before; it had a global record with a couple dozen signals
that were used by a processor verification testbench in
simulation. That same global record was then brought out
as a port at the top level of the processor in the
synthesized design; but, as it turns out, the only signals
I hooked up to I/O for in-circuit tracing had also been
assigned at that same level of the code.
I put together a quick example below; note that this code
hasn't been simulated, so there may be silly errors.
If you synthesize it with XST 9.2i or 10.1i, only the
"probe_a" signal is actually hooked up at the top level;
"probe_b", assigned lower down, is silently deleted.
Note that XTS's RTL viewer doesn't show either probe
port in the internal schematic, but the Technology view
and report files show "probe_a" connected to a pin.
Using a signal instead of a record signal causes XST errors.
If your hierarchy isn't too deep, passing probe records
up to the top using ports may be workable as an alternative
to global signals.
Brian
--
-- <probe_pkg.vhd>
--
-- probe package
--
library ieee;
use ieee.std_logic_1164.all;
package probe_pkg is
type probe_type is record
probe_a : std_logic;
probe_b : std_logic;
end record;
signal probes : probe_type;
end probe_pkg;
--
-- <up_count.vhd>
--
-- lower level counter module
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned."+";
library work;
use work.probe_pkg.all;
entity up_count is
port
(
clk : in std_logic;
count_out : out std_logic_vector(7 downto 0)
);
end up_count;
architecture arch1 of up_count is
signal count : std_logic_vector(7 downto 0) := ( others => '0');
begin
process(clk)
begin
if rising_edge(clk) then
count <= count + 1;
end if;
end process;
count_out <= count;
-- try driving global signal in probe record
probes.probe_b <= count(0);
end arch1;
--
-- <probe_top.vhd>
--
-- top level probe test
--
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.probe_pkg.all;
entity probe_top is
port
(
clk : in std_logic;
data_out : out std_logic_vector(7 downto 0);
probe_a_out : out std_logic;
probe_b_out : out std_logic
);
end probe_top;
architecture arch1 of probe_top is
signal data : std_logic_vector(7 downto 0);
begin
I_DATA : entity work.up_count
port map
(
clk => clk,
count_out => data
);
data_out <= data;
-- probe_a is assigned at the same level
probes.probe_a <= data(1);
--
-- assign probe signals to ports
--
-- probes.probe_a
-- assigned within this selfsame entity,
-- gets connected in the synthesized design
--
-- probes.probe_b
-- assigned lower down, in entity up_count,
-- is unconnected in the synthesized design
--
probe_a_out <= probes.probe_a;
probe_b_out <= probes.probe_b;
end;
Article: 135922The problem with quality is largely related to the analog front-end used to capture the digital signal. The algorithms used to refine the digital signal would be hard to surpass with a one man team. ---Matthew Hicks > On Oct 20, 10:44 am, Mike Treseler <mtrese...@gmail.com> wrote: > >>> as far as working on my own fpga projects I am interested in: >>> >>> cell phone technology >>> wireless technology >>> video/audio processing >>> sonar/radar >> Pick one and just do it. >> >> -- Mike Treseler >> > Thanks for the advice. > > I think the biggest problem when trying to learn on your own is > finding good resources. > > For example: In America TV stations will start broadcasting digital > signals to replace analog signals. Most digital TV receivers that have > been produce so far have average video/audio quality. > > I'm interested in creating my own digital receiver with high video/ > audio quality, however, don't know where to get information on the TV > signal's encoding type, data bit length, channel information...etc. > Also, I'm not sure whether or not working on this is legal without > permission. > > I haven't found any information about this online, but I'm assuming > that broadcasting stations have license agreements with digital TV > receiver manufacturers; and that is how they are able to decode the > signals. >Article: 135923
On Tue, 21 Oct 2008 16:23:00 -0700 (PDT), Fred <fred__bloggs@lycos.com> wrote: >> Yes the idle code is 5 bits of 1 which is inserted in between actual >> packet data encoded with 4b5b. Then the resulting 125 Mb/s bit stream >> is scrambled and mlt-3 encoded before being driven to the wire. >> Muzaffer Kal >> >> ASIC/FPGA Design Services >> DSPIA INC.http://www.dspia.com > >I'm rapidly coming to the conclusion that the purchase of a PHY, given >their cost, might be a smart move. Sad really because I would have >liked to have coded the whole system in a FPGA. A VHDL test bench >would have been ideal!! Believe me that's the right choice. Also if you have to receive in addition the transmitting, you have to deal with clock recovery and equalization (not to mention blw correction) at the receiver which are much more difficult problems than transmitting mlt3 signal. A 125 (or 250 depending on how you do things) ADC probably at 8 bits (if you have to do blw in digital) probably costs the same as a PHY so go with that and save yourself a world of trouble. Muzaffer Kal ASIC/FPGA Design Services DSPIA INC. http://www.dspia.comArticle: 135924
<hanumaan81@gmail.com> wrote in message news:a0cb5eb6-0638-40e4-8f04-f1684cbc161e@u40g2000pru.googlegroups.com... > Hi, Im new to DSP stuff and have a very simple question. > > Since the multiplier in virtex 5 dsp is 2's complement ... does that > mean when using the std_logic_unsigned library, the maximum number of > bits A input can have is 24 instead of 25 and 17 instead of 18 for B > input? > > Whereas I can use 25 bits for A and 18 for B by using the > std_logic_signed library? > > thanks. Dear 'new to DSP stuff', Although this doesn't answer your question, you should be using numeric.std http://www.synthworks.com/papers/vhdl_math_tricks_mapld_2003.pdf HTH., Syms.
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z