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Start by looking at your component instantiation. Then, post the rest of your code if problems remain. ---Matthew Hicks > Hello!Good day!:) ... I am new to vhdl and I really need your help. > Below is a portion of my code. it had the error: "Line 66. result of > operator = is not static."...please tell me what this means...thank > you! > > library ieee; > use ieee.std_logic_1164.all; > entity ALU is > port (A, B : in std_logic_vector(7 downto 0); > Cin : in std_logic; > sel : in std_logic_vector(3 downto 0); > Output : out std_logic_vector(7 downto 0)); > end ALU; > architecture behavioral of ALU is > component AndEightBit is > port(B, A : in std_logic_vector(7 downto 0); > S : out std_logic_vector(7 downto 0)); > end component;Article: 135676
Hello, I am a newbie and I would like your help. What is a DDR Flop? I found IFDDR and OFDDR primitives from Xilinx. However, I cannot find more information on this topic. Your comments are appreciated.Article: 135677
On Oct 12, 8:02=A0am, FP <FPGA.unkn...@gmail.com> wrote: > Hello, > > I am a newbie and I would like your help. What is a DDR Flop? I found > IFDDR and OFDDR primitives from Xilinx. However, I cannot find more > information on this topic. > > Your comments are appreciated. I would like to use this to genrate a 200MHz clock from a 100 MHz source.Article: 135678
Nial Stewart a écrit : > > That's the way I've been describing bus tri-states since I started > FPGA design 15 odd years ago. As far as I know it's a 'standard' > so the tools should be able to deal with it. So have I but I've sometimes seen it not to work NicolasArticle: 135679
I have a couple of different Xilinx evaluation boards for sale from some HAM radio projects that I've worked on. I have a Spartan board and a Virtex board. These come with the cables and power supplies. Thanks for looking. Mike mstricker@embarqmail.comArticle: 135680
"FP" <FPGA.unknown@gmail.com> wrote in message news:f04f02a9-8d27-420a-9ed0-5c7981608b32@p49g2000hsd.googlegroups.com... On Oct 12, 8:02 am, FP <FPGA.unkn...@gmail.com> wrote: > Hello, > > I am a newbie and I would like your help. What is a DDR Flop? I found > IFDDR and OFDDR primitives from Xilinx. However, I cannot find more > information on this topic. > > Your comments are appreciated. I would like to use this to genrate a 200MHz clock from a 100 MHz source. Unless you can guarantee a 50/50 mark space in your clock it would be far easier to use an internal PLL with zero delay enabled.Article: 135681
Hi ,
Can U please tell me the good refernces for STA....
Article: 135682"Leon" <leon355@btinternet.com> wrote in message news:8b26b4d6-8df3-46ee-bf45-bead03716e9e@y29g2000hsf.googlegroups.com... > On 11 Oct, 19:28, "Hamish Shufflebotham" <h.sh...@chufftypuffty.com> > wrote: >> "Leon" <leon...@btinternet.com> wrote in message >> >> news:a0543b74-9f3f-4ed8-a90a-4cfc3dc73341@u65g2000hsc.googlegroups.com... >> On 11 Oct, 18:57, "Hamish Shufflebotham" <h.sh...@chufftypuffty.com> >> wrote: >> >> >> >> > "Leon" <leon...@btinternet.com> wrote in message >> >> >news:e94e9fe1-8fe2-4b76-b8f5-c393a6511b7e@k13g2000hse.googlegroups.com... >> >> > > On 11 Oct, 18:44, "Hamish Shufflebotham" <h.sh...@chufftypuffty.com> >> > > wrote: >> > >> "Leon" <leon...@btinternet.com> wrote in message >> >> > >>news:3a7e63d4-23af-4199-8993-f4a8a4e2196b@m3g2000hsc.googlegroups.com... >> > >> On 11 Oct, 18:01, Simon <goo...@gornall.net> wrote: >> >> > >> I don't work for XMOS. I just like the devices, and believe people >> > >> should know about them. Those are all forums I use a lot, and >> > >> several >> > >> people there have thanked me for bringing them to their attention, >> > >> and >> > >> are getting involved. I don't see what is wrong with that. >> >> > >> A single XMOS device can often replace a DSP and an FPGA, which is >> > >> one >> > >> of the reasons I'm using it, and why I thought it might be of >> > >> interest >> > >> to the FPGA community. >> >> > >> I am using them in a couple of applications, I have a vested >> > >> interest >> > >> in XMOS succeeding. >> >> > >> Leon >> >> > >> mmmmm "1 bit software driven DAC" - that'll kick the shite out of my >> > >> 400MHz >> > >> 10 bit video DAC. >> >> > > That's just for outputting sound with minimum external hardware on a >> > > low-cost dev kit. I'll be using a DACat RF in one of my applications. >> >> > > Leon >> >> > Really? - and which RF DAC is that? >> >> The MAX19692. That's overkill, really, and something slower will do. >> >> Leon >> >> Your not kidding! - the maximum IO toggle rate of the XS-1 is only >> 100MHz! > > That was the first one I came to amongst my Maxim data sheets. I'll > probably use one of the 250 Msps chips. > > I want to develop a software-defined-radio, with an equally fast ADC > feeding one of the cores for the Rx function, the DAC on another for > the Tx function, and the other two cores doing all the DSP work. XMOS > is quite interested in the idea, and is giving me some chip samples to > play with by the end of the month. > > Leon Even outputting "RF" at Nyquist will only give you a 50MHz carrier - how are you going to modulate it? If it is an AM Tx then you might *just* get away with a 5MHz carrier - if you are phase modding or even going to use QAM you will have a sub 1MHz carrier - what use is that? Similarly on the Rx side, even sampling at 100MHz is going to give you a rubbish noise floor at carrier freqs above 500kHz or so. Now if you are doing IF processing I can perhaps understand a possible favourable outcome. HamishArticle: 135683
Radha wrote: good refernces for STA.... http://www.google.com/search?q=static+timing+analysis+tutorialArticle: 135684
I am implementing a Microblaze NoC on an FPGA. Four Microblaze Processors interconnected upon a Virtex2P and I was wondering if anyone could tell me of any tutorials available which might help my studying on the subject. -- Message posted using http://www.talkaboutelectronicequipment.com/group/comp.arch.fpga/ More information at http://www.talkaboutelectronicequipment.com/faq.htmlArticle: 135685
Hi All, Can somebody suggest me a technical report/paper/case study of implementation of Complex Event Processing in FPGA. Basically, I want to know how to implement CEP in FPGA. I am trying to build a high volume high speed data stream handling device[hint: think trading!] and I need that initial 'handle' to start developing/getting started in implementation of CEP in FPGA. Your suggestions, comments are most welcome SohamArticle: 135686
On Sun, 12 Oct 2008 12:52:06 -0700 (PDT), Equinox <sohamdas@gmail.com> wrote: >Basically, I want to know how to implement CEP in FPGA. I am trying to >build a high volume high speed data stream handling device[hint: think >trading!] Tell your idiot stock trader customers to go to blazes. Anything that makes their greedy silly systems respond even faster will make the financial markets even more unstable and chaotic than they already are, and we will all be worse off. Instead of feeding them with yet more technology that they're too stupid to use well, give them a few good books on control theory and hope that either they all die of boredom or perhaps they might learn something about making systems stable. Not that I'm bitter or anything, of course :-) -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 135687
On 12 Oct, 17:42, "Hamish Shufflebotham" <h.sh...@chufftypuffty.com> wrote: > "Leon" <leon...@btinternet.com> wrote in message > > news:8b26b4d6-8df3-46ee-bf45-bead03716e9e@y29g2000hsf.googlegroups.com... > > > > > On 11 Oct, 19:28, "Hamish Shufflebotham" <h.sh...@chufftypuffty.com> > > wrote: > >> "Leon" <leon...@btinternet.com> wrote in message > > >>news:a0543b74-9f3f-4ed8-a90a-4cfc3dc73341@u65g2000hsc.googlegroups.com... > >> On 11 Oct, 18:57, "Hamish Shufflebotham" <h.sh...@chufftypuffty.com> > >> wrote: > > >> > "Leon" <leon...@btinternet.com> wrote in message > > >> >news:e94e9fe1-8fe2-4b76-b8f5-c393a6511b7e@k13g2000hse.googlegroups.com... > > >> > > On 11 Oct, 18:44, "Hamish Shufflebotham" <h.sh...@chufftypuffty.com> > >> > > wrote: > >> > >> "Leon" <leon...@btinternet.com> wrote in message > > >> > >>news:3a7e63d4-23af-4199-8993-f4a8a4e2196b@m3g2000hsc.googlegroups.com... > >> > >> On 11 Oct, 18:01, Simon <goo...@gornall.net> wrote: > > >> > >> I don't work for XMOS. I just like the devices, and believe people > >> > >> should know about them. Those are all forums I use a lot, and > >> > >> several > >> > >> people there have thanked me for bringing them to their attention, > >> > >> and > >> > >> are getting involved. I don't see what is wrong with that. > > >> > >> A single XMOS device can often replace a DSP and an FPGA, which is > >> > >> one > >> > >> of the reasons I'm using it, and why I thought it might be of > >> > >> interest > >> > >> to the FPGA community. > > >> > >> I am using them in a couple of applications, I have a vested > >> > >> interest > >> > >> in XMOS succeeding. > > >> > >> Leon > > >> > >> mmmmm "1 bit software driven DAC" - that'll kick the shite out of my > >> > >> 400MHz > >> > >> 10 bit video DAC. > > >> > > That's just for outputting sound with minimum external hardware on a > >> > > low-cost dev kit. I'll be using a DACat RF in one of my applications. > > >> > > Leon > > >> > Really? - and which RF DAC is that? > > >> The MAX19692. That's overkill, really, and something slower will do. > > >> Leon > > >> Your not kidding! - the maximum IO toggle rate of the XS-1 is only > >> 100MHz! > > > That was the first one I came to amongst my Maxim data sheets. I'll > > probably use one of the 250 Msps chips. > > > I want to develop a software-defined-radio, with an equally fast ADC > > feeding one of the cores for the Rx function, the DAC on another for > > the Tx function, and the other two cores doing all the DSP work. XMOS > > is quite interested in the idea, and is giving me some chip samples to > > play with by the end of the month. > > > Leon > > Even outputting "RF" at Nyquist will only give you a 50MHz carrier - how are > you going to modulate it? > > If it is an AM Tx then you might *just* get away with a 5MHz carrier - if > you are phase modding or even going to use QAM you will have a sub 1MHz > carrier - what use is that? > > Similarly on the Rx side, even sampling at 100MHz is going to give you a > rubbish noise floor at carrier freqs above 500kHz or so. > > Now if you are doing IF processing I can perhaps understand a possible > favourable outcome. > > Hamish SSB on some of the amateur bands should be doable. I'll try a quadrature sampling detector in the receiver first, converting to I and Q baseband, with a codec. LeonArticle: 135688
On Sun, 12 Oct 2008 12:52:06 -0700 (PDT), Equinox <sohamdas@gmail.com> wrote: >Hi All, > >Can somebody suggest me a technical report/paper/case study of >implementation of Complex Event Processing in FPGA. > >Basically, I want to know how to implement CEP in FPGA. > >Your suggestions, comments are most welcome > Decompose your Complex Events into their Real and Imaginary components, and process these in parallel. Please note, it is an all too common mistake to take algorithms originally designed for real values, and apply them to imaginary values. Hope this helps, - BrianArticle: 135689
On Sun, 12 Oct 2008 21:37:21 +0100, Jonathan Bromley <jonathan.bromley@MYCOMPANY.com> wrote: >Not that I'm bitter or anything, of course :-) discovered a j in your pension fund? - BrianArticle: 135690
On Oct 11, 1:43=A0am, Leon <leon...@btinternet.com> wrote: > On 10 Oct, 17:42, ste...@coppice.org wrote: > > > > > On Oct 10, 9:01=A0pm, Leon <leon...@btinternet.com> wrote: > > > > I've just ordered my 1600 MIPS XMOS XC-1 design kit. > > > > The XMOS chips will replace DSPs and FPGAs in a lot of applications. > > > > I haven't been so excited about a new chip since the transputer came > > > out. David May designed them both, of course. > > > > Leon > > > leon...@btinternet.com > > > Is the comparison with the Transputer supposed to imply this is a half > > thought out design with brain dead execution? :-\ > > > Steve > > The transputer was ahead of its time, and really pushed the technology > that was available. I sold a lot of systems using it, mostly to > universities and research establishments, because there was nothing > else around with that sort of performance then. Inmos even had their > own fab! > > Leon The Transputer wasn't ahead of its time. It was brain dead. A chip only effective in substantial arrays selling for hundreds of pounds per device was a dead duck from the start. The only people who could seriously look at it for substantial arrays were military applications. However, when approached about military parts Transputer gave evasive answers. There was nothing innovative about the design of the Transputer. The device as it was supposed to be (i.e. separate comms and execution planes), rather than the crippled one they shipped, was similar to designs several people in the UK (and presumably elsewhere) were toying with at that time. The others did not proceed because the economics looked so wrong.Article: 135691
Hello everyone, I would like to create a scheme to hook up an external CPU model to a Verilog design. I have already established a basic communication protocol to link Verilog design to an external device. So, it should be easy to link a CPU model to a Verilog design. I'm looking for a 32-bit CPU model written in C or Java or Python or any high-level language that can be supported by gcc. So far, I can think of are SPARC V8 or DLX CPU, which was designed by Hennessy and Patterson. As I don't want to spend time to create development environment for this, I would like to find a CPU which is ready to plug-in. The goal of my experiment is to create a framework so that any external model (CPU, DSP, compression engine, and other IPs) can be easily plugged in to a Verilog design. Any comments, any suggestions will be greatly appreciated. Aki NiimuraArticle: 135692
FP wrote: > On Oct 12, 8:02 am, FP <FPGA.unkn...@gmail.com> wrote: >> Hello, >> >> I am a newbie and I would like your help. What is a DDR Flop? I found >> IFDDR and OFDDR primitives from Xilinx. However, I cannot find more >> information on this topic. >> >> Your comments are appreciated. > > I would like to use this to genrate a 200MHz clock from a 100 MHz > source. It doesn't work that way. A DDR (double date rate) register clocks data in/out on both the positive and negative edges of the clock. This can generate a replica of the clock, but can not double it. In comparison, a normal SDR (single data rate) register on clocks data in/out on one edge of the clock and can generate a maximum of a half/rate clock. Ed McGettigan -- Xilinx Inc.Article: 135693
FP wrote: > Hello, > > I am a newbie and I would like your help. What is a DDR Flop? I found > IFDDR and OFDDR primitives from Xilinx. However, I cannot find more > information on this topic. > > Your comments are appreciated. Ed's correct about only replicating the clock. But look into what the Xilinx DCM (Digital Clock Manager) can do with its DLL (Delay Locked Loop). You can generate a 200 MHz clock with a 100 MHz input clock.Article: 135694
> Tell your idiot stock trader customers to go to blazes. > Anything that makes their greedy silly systems respond > even faster will make the financial markets even more > unstable and chaotic than they already are, and we will > all be worse off. What if I say, technology is inevitable. And secondly, I am not operating in US financial market :) =A0Instead of feeding them with yet more > technology that they're too stupid to use well, give > them a few good books on control theory and hope that > either they all die of boredom or perhaps they might > learn something about making systems stable. > > Not that I'm bitter or anything, of course :-) Hmmmm... I understand.... > -- > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated.Article: 135695
Thanks a lot Brian. Do you have any good book/literature on this topic? Thank You. SohamArticle: 135696
> Why does this need to be on the FPGA ? > SoftCPUs still need external memory, so are a 2-3 chip solution. Correct, but the FPGA is a "must have" in this project, so an embedded softcore will give us allot of advantages: *No extra BOM cost for MCU and needed extra components. *No additional use of "real estate" for the MCU subsystem. *High data bandwidt between our custom hardware and CPU. *"Weird" hardware configurations are supported (e.g. we need 4+ i2c busses). These pros has made us going for the softcore soloution. -- MMJArticle: 135697
On 13 Oct, 03:52, ste...@coppice.org wrote: > On Oct 11, 1:43=A0am, Leon <leon...@btinternet.com> wrote: > > > > > On 10 Oct, 17:42, ste...@coppice.org wrote: > > > > On Oct 10, 9:01=A0pm, Leon <leon...@btinternet.com> wrote: > > > > > I've just ordered my 1600 MIPS XMOS XC-1 design kit. > > > > > The XMOS chips will replace DSPs and FPGAs in a lot of applications= . > > > > > I haven't been so excited about a new chip since the transputer cam= e > > > > out. David May designed them both, of course. > > > > > Leon > > > > leon...@btinternet.com > > > > Is the comparison with the Transputer supposed to imply this is a hal= f > > > thought out design with brain dead execution? :-\ > > > > Steve > > > The transputer was ahead of its time, and really pushed the technology > > that was available. I sold a lot of systems using it, mostly to > > universities and research establishments, because there was nothing > > else around with that sort of performance then. Inmos even had their > > own fab! > > > Leon > > The Transputer wasn't ahead of its time. It was brain dead. A chip > only effective in substantial arrays selling for hundreds of pounds > per device was a dead duck from the start. The only people who could > seriously look at it for substantial arrays were military > applications. However, when approached about military parts Transputer > gave evasive answers. > > There was nothing innovative about the design of the Transputer. The > device as it was supposed to be (i.e. separate comms and execution > planes), rather than the crippled one they shipped, was similar to > designs several people in the UK (and presumably elsewhere) were > toying with at that time. The others did not proceed because the > economics looked so wrong. It was used very widely ar the time, because there wasn't anything comparable for sale. I even sold several of my modules to hobbyists and university students - at =A3500 each! Some of the customers for my 16 module system were prestigious outfits such as BAe, Plessey Roke Manor, GCHQ and Oxford University PRG. It delivered 320 MIPS with very good floating-point performance at a comparatively low price (about =A313,000 with T800 chips). I even had inquiries from Russia, indirectly, but it was embargoed because of the performance. I did once apply for an export license for Russia, to see what happened, and actually got it! I contacted the DTI about it; they got very excited, admitted thay had made a mistake and insisted that I returned the document. I'm quite sure that Russia did get the technology, though. I heard on the grapevine that there were companies in Finland that acted as intermediaries. LeonArticle: 135698
Brian Drummond wrote: > On Sun, 12 Oct 2008 12:52:06 -0700 (PDT), Equinox <sohamdas@gmail.com> > wrote: > >> Hi All, >> >> Can somebody suggest me a technical report/paper/case study of >> implementation of Complex Event Processing in FPGA. >> >> Basically, I want to know how to implement CEP in FPGA. >> >> Your suggestions, comments are most welcome >> > > Decompose your Complex Events into their Real and Imaginary components, > and process these in parallel. > > Please note, it is an all too common mistake to take algorithms > originally designed for real values, and apply them to imaginary values. > Given the OP says it's for "trading", and we have imaginary values, it must be for CDOs & suchlike :)Article: 135699
> Since the complete design fits the pins, > why not run STA on that? Because there are about 5 people writing RTL for the design and the complete design doesn't exist yet and I want to check that I meet timing closure before the complete design gets plugged together. heiner
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