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On Jan 31, 8:37=A0pm, rickman <gnu...@gmail.com> wrote: > On Jan 31, 7:56=A0pm, maher <xfiles.detec...@gmail.com> wrote: > > > > > > > On Jan 31, 4:36=A0pm, rickman <gnu...@gmail.com> wrote: > > > > On Jan 31, 1:02=A0pm, maher <xfiles.detec...@gmail.com> wrote: > > > > > well, if you understand the difference then please let me know. But= if > > > > you don't, then don't pretend to be "Abo El3oreef" -- translates to= : a > > > > person who pretends to be knowledgeable while he don't know anythin= g! > > > Sorry if you understand my reply in a wrong way. I just replied the > > same way you replied my original message! > > > > Are you asking what the difference is or are you just being rude? > > > > This is the sort of stuff that can be figured out with a simple googl= e > > > search. =A0Every question asked here does not have to be answered her= e. > > > Back to my original question: I don't ask what is the different > > between transmission gates and pass gates; I know exactly what the > > difference is. What I am asking about (as specified in my first post, > > sorry I changed my nick name from "abbas" to "maher") is the circuit > > level design of lookup tables in commercial FPGAs such as Vitretx-II > > pro from Xilinx. Simply, this is my question. I would be grateful to > > those who can reply and provide references. > > A transmission gate is a lot bigger, requiring two pass transistors > and an inverter to drive the complemented one. =A0A simple pass > transistor will do nicely for nearly any digital signal gating. =A0A > transmission gate is typically used for analog signals where you need > the resistance to remain relatively constant. =A0A simple pass > transistor has a variable resistance as the input voltage changes... > ok for most digital stuff, but not so good for analog. > > I think if you actually understood the difference, you would > understand why transmission gates are not used in FPGAs. =A0These parts > are all about density and pass transistors are used both for route > switching and in the LUTs for the output mux from the memory elements > (a RAM is just memory elements with their outputs muxed together.) > What did you find when you searched on Google? > > Rick- Hide quoted text - > > - Show quoted text - Thanks rick. You are right about the point that FPGAs are about density, and it is important to have smaller size components, i.e. pass transistors to implement lookup tables rather than transmission gate, though level restorers and buffer are used with pass-transistor based LUTs to restore the signal level since pass gates are not perfect for all levels. What made me confused, and originally ask the question, is that I found the following patent filed by Xilinx in 2003: http://www.google.com/patents?id=3Dz4IOAAAAEBAJ&dq=3Dlow+power+lookup+table= +transmission+gate If you read the abstract, you will notice that the inventors claim that although the gate count increases in the LUT when TGs are used, this can be mitigated by removing the level restoring circuits (they call it half latches) required in pass-transistor based designs, and removing initialization circuitry that is unnecessary by the TG-based design. Please have a look at that patent and let me know if you have any references that describe the circuit design of LUTs for low power operation used in the industry.Article: 137851
Hi, I'm trying to implement a design on the Xilinx FPGA which is heavily pipelined, let say 50 stages, and each stage has a data width of aorund 30 bits. Now, I want to halt the pipeline or "freeze" it at some instances. One way would be to tie up all the clock enable signals of those registers and then control the pipleline using this clock_enable signal. However, I'm affraid about that control signal's fan-out (probably something around 1500). Do you think it's a good design practice? Any suggestions or similar experience? BTW, Will using the clock-enable signal of FFs affect the amount of consumed resources? Or they are simply built-in features that we can choose either to use or not to use?Article: 137852
> Hi, > > I'm trying to implement a design on the Xilinx FPGA which is heavily > pipelined, let say 50 stages, and each stage has a data width of > aorund 30 bits. Now, I want to halt the pipeline or "freeze" it at > some instances. One way would be to tie up all the clock enable > signals of those registers and then control the pipleline using this > clock_enable signal. However, I'm affraid about that control signal's > fan-out (probably something around 1500). > Can you anticipate this freeze? > Do you think it's a good design practice? Any suggestions or similar > experience? > > BTW, Will using the clock-enable signal of FFs affect the amount of > consumed resources? Or they are simply built-in features that we can > choose either to use or not to use? > It will probably consume routing resources. ---Matthew HicksArticle: 137853
rickman <gnuarm@gmail.com> wrote: (snip) > A transmission gate is a lot bigger, requiring two pass transistors > and an inverter to drive the complemented one. A simple pass > transistor will do nicely for nearly any digital signal gating. A > transmission gate is typically used for analog signals where you need > the resistance to remain relatively constant. A simple pass > transistor has a variable resistance as the input voltage changes... > ok for most digital stuff, but not so good for analog. Driven by SRAM cells, which have the complement signal available, you don't need the inverter. So now it is down to one transistor vs. two, something that will have to be optimized along with the rest of the design. In early FPGAs the routing lines could be driven from different points through pass transistors (or transmission gates). With the scaling to current sizes, they require intermediate buffers such that signals can only go one direction. Presumably the exact location for buffers along with the decision for pass transistors vs. transmission gates are just a small part of the design decisions that need to be made to make a high performance FPGA design work. -- glenArticle: 137854
On Jan 31, 8:34=A0pm, Ehsan <ehsan.hosse...@gmail.com> wrote: > Hi, > > I'm trying to implement a design on the Xilinx FPGA which is heavily > pipelined, let say 50 stages, and each stage has a data width of > aorund 30 bits. Now, I want to halt the pipeline or "freeze" it at > some instances. One way would be to tie up all the clock enable > signals of those registers and then control the pipleline using this > clock_enable signal. However, I'm affraid about that control signal's > fan-out (probably something around 1500). > > Do you think it's a good design practice? Any suggestions or similar > experience? > > BTW, Will using the clock-enable signal of FFs affect the amount of > consumed resources? Or they are simply built-in features that we can > choose either to use or not to use? Ehsan, you did not mention the clock frequency, only the high fan-out of 1500. You can gate the clock, with the enable input to the global clock buffer/multiplexer. Seems like a better solution to me. Peter AlfkeArticle: 137855
"Peter Alfke": > On Jan 31, 8:34 pm, Ehsan <ehsan.hosse...@gmail.com> wrote: >> I'm trying to implement a design on the Xilinx FPGA which is heavily >> pipelined, let say 50 stages, and each stage has a data width of >> aorund 30 bits. Now, I want to halt the pipeline or "freeze" it at >> some instances. One way would be to tie up all the clock enable >> signals of those registers and then control the pipleline using this >> clock_enable signal. However, I'm affraid about that control signal's >> fan-out (probably something around 1500). Can the ce signal be pipelined, too? If not: Does it actually have a high combinatorial delay, compared to the expected clock period? >> Do you think it's a good design practice? Any suggestions or similar >> experience? Hm, I'm not fully sure about this. At least it might be the way to go if you want the tool chain to not bore with warnings about things you intended. >> BTW, Will using the clock-enable signal of FFs affect the amount of >> consumed resources? Or they are simply built-in features that we can >> choose either to use or not to use? You'll likely already have a lot of ce-signals, and many of them might actually be non-combinatorial, so comining with a global ce would require some combinatorial logic per local ce. > Ehsan, you did not mention the clock frequency, only the high fan-out > of 1500. > You can gate the clock, with the enable input to the global clock > buffer/multiplexer. > Seems like a better solution to me. But if the pipeline requires quater-clocks, this would end up with two additional global clock buffers. Probably a little too much, compared to the percentage of area-usage, that 1.5K FF might mean. Gruss Jan BrunsArticle: 137856
Ehsan <ehsan.hosseini@gmail.com> wrote:
>Hi,
>
>I'm trying to implement a design on the Xilinx FPGA which is heavily
>pipelined, let say 50 stages, and each stage has a data width of
>aorund 30 bits. Now, I want to halt the pipeline or "freeze" it at
>some instances. One way would be to tie up all the clock enable
>signals of those registers and then control the pipleline using this
>clock_enable signal. However, I'm affraid about that control signal's
>fan-out (probably something around 1500).
>
>Do you think it's a good design practice? Any suggestions or similar
>experience?
Just try it first. If the signal gets too slow or too heavily loaded,
make multiple clock enable signals which do the same to divide the
load. But my guess is that the routing software already takes care of
this issue.
>BTW, Will using the clock-enable signal of FFs affect the amount of
>consumed resources? Or they are simply built-in features that we can
>choose either to use or not to use?
The CE is usually included in the combinatorial logic so expect some
additional combinatorial logic to be used.
--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
"If it doesn't fit, use a bigger hammer!"
--------------------------------------------------------------
Article: 137857Hi to all I haven't touched FPGAs or VHDL since the university years so I was thinking to get a starter board in order to get back to the path. I did find some cheap boards out there but I am not sure if I could burn something like a 32-bit RISC soft core on that. I mean how many logic blocks (for example of the Xilinx architecture) would be needed for a project like this, assuming that it is of the size of an OpenSPARC? Could you suggest me a cheap board (up to $400) with some good features and maybe an FPGA capable of hosting a good-sized core. Also good features would be VGA,PS/2,ethernet. Thanks Best regards GMArticle: 137858
gm <gm@nomail.com> wrote: > I haven't touched FPGAs or VHDL since the university years so I was > thinking to get a starter board in order to get back to the path. I did > find some cheap boards out there but I am not sure if I could burn > something like a 32-bit RISC soft core on that. (snip) > Also good features would be VGA,PS/2,ethernet. Thanks I recently got a Digilent Spartan3E board, which was the XC3S500E. There are many boards with VGA, serial, and PS/2 keyboard, but not so many with ethernet. That might be a little small for some 32 bit processors, if you want a lot of extra logic (ethernet MAC, video generator), but if you keep the rest of the design small it might fit. I plan to start with smaller processors (such as the 8080) and work up to larger ones. Maybe the 68020 wouldn't be so big (maybe even microcoded), or a small SPARC. UltraSPARC is probably too big. -- glenArticle: 137859
On 2009-02-01, Ehsan <ehsan.hosseini@gmail.com> wrote: > Mathew, > No, the freeze cannot be anticipated. Actually, the output of the > pipeline would be connected to a FIFO and once the FIFO is full the > pipe should be halted. The data within the stages should not be lost. > However, we can change the pipeline design so that the number of > working cycles are known. I mean, we can wait until the FIFO becomes > empty and then start writing to it. In the mean time, there would be > no FIFO reads until it gets Ful. Therefore, the number of working > cycles are known, i.e. the size of the FIFO. Could you create a high watermark signal in the FIFO when there is room for around 4 more words in the FIFO? If so you will have plenty of time to propagate a pipelined "clock enable" signal to your datapath with a moderate amount of fan-out for every level of pipelining in your CE signal. /AndreasArticle: 137860
On Feb 1, 11:27=A0am, gm <g...@nomail.com> wrote: > Hi to all > > I haven't touched FPGAs or VHDL since the university years so I was > thinking to get a starter board in order to get back to the path. I did > find some cheap boards out there but I am not sure if I could burn > something like a 32-bit RISC soft core on that. I mean how many logic > blocks (for example of the Xilinx architecture) would be needed for a > project like this, assuming that it is of the size of an OpenSPARC? > Could you suggest me a cheap board (up to $400) with some good features > and maybe an FPGA capable of hosting a good-sized core. Also good > features would be VGA,PS/2,ethernet. Thanks > > Best regards > GM OpenSPARC is truly huge, so it may not fit into any board below $400 budget (unless it is special university discount board) ok, i take it back, even with educational pricing the board cost $750 xilinx s3 500 is enough for 32 bit cores/base desing, but something with s3 1000+ size is better if you some more peripheral features now, it depends how quickly do you want the board, if i would be buying a new FPGA eval board, i would defenetly wait til the Spartan-6 evaluation boards are available (i know when they have been promised to be ready but can not tell this before the info comes public), ok, i can say that it probably may fit your desired deadline to wait the spartan-6 board. as the new technologies make the LUT/$ ratio better there are chances you get more LUTs for the $ spend on the eval board. There are some other considerations why it makes sense to get an Spartan-6 or Virtex-6 based board :) AnttiArticle: 137861
On Feb 1, 1:02=A0pm, Matthew Hicks <mdhic...@uiuc.edu> wrote: > > Hi, > > > I'm trying to implement a design on the Xilinx FPGA which is heavily > > pipelined, let say 50 stages, and each stage has a data width of > > aorund 30 bits. Now, I want to halt the pipeline or "freeze" it at > > some instances. One way would be to tie up all the clock enable > > signals of those registers and then control the pipleline using this > > clock_enable signal. However, I'm affraid about that control signal's > > fan-out (probably something around 1500). > > Can you anticipate this freeze? > > > Do you think it's a good design practice? Any suggestions or similar > > experience? > > > BTW, Will using the clock-enable signal of FFs affect the amount of > > consumed resources? Or they are simply built-in features that we can > > choose either to use or not to use? > > It will probably consume routing resources. > > ---Matthew Hicks Mathew, No, the freeze cannot be anticipated. Actually, the output of the pipeline would be connected to a FIFO and once the FIFO is full the pipe should be halted. The data within the stages should not be lost. However, we can change the pipeline design so that the number of working cycles are known. I mean, we can wait until the FIFO becomes empty and then start writing to it. In the mean time, there would be no FIFO reads until it gets Ful. Therefore, the number of working cycles are known, i.e. the size of the FIFO.Article: 137862
On Feb 1, 2:26=A0pm, Peter Alfke <al...@sbcglobal.net> wrote: > On Jan 31, 8:34=A0pm, Ehsan <ehsan.hosse...@gmail.com> wrote: > > > > > > > Hi, > > > I'm trying to implement a design on the Xilinx FPGA which is heavily > > pipelined, let say 50 stages, and each stage has a data width of > > aorund 30 bits. Now, I want to halt the pipeline or "freeze" it at > > some instances. One way would be to tie up all the clock enable > > signals of those registers and then control the pipleline using this > > clock_enable signal. However, I'm affraid about that control signal's > > fan-out (probably something around 1500). > > > Do you think it's a good design practice? Any suggestions or similar > > experience? > > > BTW, Will using the clock-enable signal of FFs affect the amount of > > consumed resources? Or they are simply built-in features that we can > > choose either to use or not to use? > > Ehsan, you did not mention the clock frequency, only the high fan-out > of 1500. > You can gate the clock, with the enable input to the global clock > buffer/multiplexer. > Seems like a better solution to me. > Peter Alfke- Hide quoted text - > > - Show quoted text - Peter, The clock would be at say 100 MHz, and the FPGA is virtex4 FX100 speed grade -10. I've not tried clock gating so far. But, I was thinking of something similar, using the clock resources for the global ce. Since they are routed all over the chip and are low skew, they might help.Article: 137863
On Sat, 31 Jan 2009 20:34:56 -0800 (PST), Ehsan wrote: >I'm trying to implement a design on the Xilinx FPGA which is heavily >pipelined, let say 50 stages, and each stage has a data width of >aorund 30 bits. Now, I want to halt the pipeline or "freeze" it at >some instances. One way would be to tie up all the clock enable >signals of those registers and then control the pipleline using this >clock_enable signal. However, I'm affraid about that control signal's >fan-out (probably something around 1500). > >Do you think it's a good design practice? Any suggestions or similar >experience? From a later post it seems you're stalling the pipe because of back-pressure from its output (sink) FIFO. I agree that it seems pretty ugly to do this by propagating a _combinational_ signal all the way back up the pipe, when you've taken so much trouble to make each stage _registered_ (by pipelining) in the forward direction. One possible solution is to provide a 1-place holding buffer (effectively a 1-deep FIFO) every few stages. Having the holding buffer there means that you can now register the back-pressure "freeze" signal, introducing a cycle of latency in the freeze operation. This costs an additional data register, but you don't need one at every stage - just often enough to alleviate the fanout issues you describe. I suspect roughly one buffer per 5 pipe stages is about the right compromise, but that is very much a guess. This arrangement also introduces a chain of registers into the freeze signal's path, which is likely to make it far easier for the tools to deal with any large fanout issues that may arise. One final point: Introducing these holding buffers along the pipe effectively gives the whole pipe some FIFO behaviour. That may mean that you don't need the pipe's output FIFO at all, which could be another useful resource trade-off. Obviously a full-dress FIFO localised at the end of the pipe will be implemented in blockRAM, whereas the holding buffers will burn up logic cells, so this probably isn't a real win in practice. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 137864
Hi I have the Cyclon III dev kit as well the Bitec composite video in / VGA out and DVI in/out boards Using the Quartus II and Nios both v 8.1. I have the sample code up running and can do some modification to the code and move and mirror the video Now I realy need to rotate the video signal 90 degree.... and I'm a bit out of ideas Please have a look at http://www.alteraforum.com/forum/showthread.php?t=4457 so you can see what I want to obtain.... I would be very happy for a hint to succes to rotate the video... Perhaps a HDL code to copy / rotate video from one part of the DDR2 ram to another without taking all the resources Best regards WiljanArticle: 137865
On Jan 31, 1:39=A0pm, Antti <Antti.Luk...@googlemail.com> wrote: > On Jan 31, 8:53=A0pm, Antti <Antti.Luk...@googlemail.com> wrote: > the problem seems to be that the minimum number of APB slaves is 2 ! What is it like using LIbero with CoreABC? Do they offer small low cost packages? John GriessenArticle: 137866
>Could you create a high watermark signal in the FIFO when there is >room for around 4 more words in the FIFO? If so you will have plenty >of time to propagate a pipelined "clock enable" signal to your >datapath with a moderate amount of fan-out for every level of >pipelining in your CE signal. Most FIFOs have an almost-full signal. It's needed for things like this. -- These are my opinions, not necessarily my employer's. I hate spam.Article: 137867
On Feb 1, 5:45=A0pm, john_griessen <j...@foseda.com> wrote: > On Jan 31, 1:39=A0pm, Antti <Antti.Luk...@googlemail.com> wrote: > > > On Jan 31, 8:53=A0pm, Antti <Antti.Luk...@googlemail.com> wrote: > > the problem seems to be that the minimum number of APB slaves is 2 ! > > What is it like using LIbero with CoreABC? =A0Do they offer small low > cost packages? > > John Griessen Hi I am writing User manual (reference designs section!) for the FPGA- Stamp http://trioflex.com/index.php?option=3Dcom_content&task=3Dview&id=3D22&Item= id=3D26 i am surprised how nice the Libero has become, the smart design is really nice thing for quick wiring one example that i made, CoreABC+CorePWM with small program that set the LED PWM intensity and loops and changes it, that takes 249 logic cells, with code implemented as hard rom in logic sure it only 5 instructions and most of the stuff is optimized away still the CoreABC is pretty much useable similarly to PicoBlaze AnttiArticle: 137868
> now, it depends how quickly do you want the board, if i would be > buying a new FPGA eval board, i would defenetly > wait til the Spartan-6 evaluation boards are available (i know when > they have been promised to be ready but > can not tell this before the info comes public), ok, i can say that it > probably may fit your desired deadline > to wait the spartan-6 board. as the new technologies make the LUT/$ > ratio better there are chances you > get more LUTs for the $ spend on the eval board. There are some other > considerations why it makes sense > to get an Spartan-6 or Virtex-6 based board :) > > Antti > I am not in a rush (this is not job-related, it is more for practice and as a hobby) so I can wait and maybe save money for getting something better. Until then I could do some practice with VHDL simulations. So, I think I am going to follow your advice Antti! Thank you Antti and Glen for your advices Best Regards GMArticle: 137869
> I would be very happy for a hint to succes to rotate the video... Just flip your monitor on its sideArticle: 137870
Hi, I am seeing the following error when trying to configure my Spartan 3A/3AN eval board using ISE 10.1 // *** BATCH CMD : ReadIdcode -p 1 INFO:iMPACT:583 - '1': The idcode read from the device does not match the idcode in the bsdl File. INFO:iMPACT:1578 - '1': Device IDCODE : 00000100010001010000000100100110 INFO:iMPACT:1579 - '1': Expected IDCODE: 00000010001000101000000010010011 It appears to be an extra shift and I thought this may be the USB or signal integrity to blame. However, I can get the following info (with no problem) using the Cable Setup utility (Output -> Cable Set-up): Checking cable driver. Driver file xusbdfwu.sys found. Driver version: src=1027, dest=1027. Driver windrvr6.sys version = 8.1.1.0. WinDriver v8.11 Jungo (c) 1997 - 2006 Build Date: Oct 16 2006 X86 32bit SYS 12:35:07, version = 811. Cable PID = 0008. Max current requested during enumeration is 74 mA. Type = 0x0004. Cable Type = 3, Revision = 0. Setting cable speed to 6 MHz. Cable connection established. Firmware version = 1303. File version of D:/Xilinx/10.1/ISE/data/xusb_xlp.hex = 1303. Firmware hex file version = 1303. PLD file version = 0012h. PLD version = 0012h. So it looks like the USB communications is OK. Can anyone give a pointer to what may be wrong? I have followed the documentation (Spartan-3A/3AN Starter Kit Board User Guide) and it looks like its set up properly for a USB download. The Demo program is working well (LED's flashing user screen displaying demo message). Thanks for your attention, MikeArticle: 137871
Ehsan wrote:
> I'm trying to implement a design on the Xilinx FPGA which is heavily
> pipelined, let say 50 stages, and each stage has a data width of
> aorund 30 bits. Now, I want to halt the pipeline or "freeze" it at
> some instances. One way would be to tie up all the clock enable
> signals of those registers and then control the pipeline using this
> clock_enable signal. However, I'm afraid about that control signal's
> fan-out (probably something around 1500).
What if you just clock disabled the last stage?
-- Mike Treseler
Article: 137872gm wrote: > I am not in a rush (this is not job-related, it is more for practice and > as a hobby) so I can wait and maybe save money for getting something > better. Until then I could do some practice with VHDL simulations. An excellent idea. If you can write synchronous code and verify it with a vhdl testbench, you will be ahead of the game, whatever you decide to do. -- Mike TreselerArticle: 137873
Antti I don't think any boards supporting the next families will be available generally for a some time but tomorrow might tell us different. I expect we will be one the first to have such a product but that's not giving anything away. Meanwhile it's worth pointing out to Euro and Dollar countries our products are now much cheaper due to our currency and $400 goes a long way. I would think we stand a chance of possibly doing something under US$400 that might do an OpenSparc. It's more a question of whether the full ISE is needed or Webpack can be used. Do you have a size for OpenSparc? John Adair Enterpoint Ltd. On 1 Feb, 12:40, Antti <Antti.Luk...@googlemail.com> wrote: > On Feb 1, 11:27=A0am, gm <g...@nomail.com> wrote: > > > Hi to all > > > I haven't touched FPGAs or VHDL since the university years so I was > > thinking to get a starter board in order to get back to the path. I did > > find some cheap boards out there but I am not sure if I could burn > > something like a 32-bit RISC soft core on that. I mean how many logic > > blocks (for example of the Xilinx architecture) would be needed for a > > project like this, assuming that it is of the size of an OpenSPARC? > > Could you suggest me a cheap board (up to $400) with some good features > > and maybe an FPGA capable of hosting a good-sized core. Also good > > features would be VGA,PS/2,ethernet. Thanks > > > Best regards > > GM > > OpenSPARC is truly huge, so it may not fit into any board below $400 > budget (unless it is special university discount board) > ok, i take it back, even with educational pricing the board cost $750 > > xilinx s3 500 is enough for 32 bit cores/base desing, but something > with s3 1000+ size is better if you some more peripheral features > > now, it depends how quickly do you want the board, if i would be > buying a new FPGA eval board, i would defenetly > wait til the Spartan-6 evaluation boards are available (i know when > they have been promised to be ready but > can not tell this before the info comes public), ok, i can say that it > probably may fit your desired deadline > to wait the spartan-6 board. as the new technologies make the LUT/$ > ratio better there are chances you > get more LUTs for the $ spend on the eval board. There are some other > considerations why it makes sense > to get an Spartan-6 or Virtex-6 based board :) > > AnttiArticle: 137874
Hi, I recently started to look for an mp3 encoding and decoding IP, but to my surprise I cannot find anything suitable or anything at all for that matter. By various reasons I=92m kind of stuck to the Xilinx range of FPGAs so I naturally started out by having a look at their cores and 3rd party cores listed at their webpage, but there are only full blown MPEG-2 and MPEG-4 cores and I only want an MPEG-1 Layer 3 core. I also had a look at opencores.org, but that search was also fruitless. So, is it really that bad? Is there nothing to buy or at least start from? Regards Fredrik
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