Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Hi Everyone, I am a student trying to build a project with Altera's Cyclone FPGA board. For my project, I need to access a large amount of data, which I would like to store in the board's memory. I did not find any simple example which could show me how to simply read and write to the chip's built-in memory. Is there any ready made interface I could use? I would like not to use the Nios implementations, as they seem to be very large and complex for me at this stage. Any help would be appreciated !!! Thanks, RoiArticle: 102276
the best advice dear student is to learn. learn by doing. you refer both on-board and on-chip memry, so which one do you want to use?? FPGAs are not programmed, but rather you write the "description" of the hardware that you wish the FPGA to implement, this description may include different memory interfaces to either onchip or off chip (on-board) memories. but the way you ask there is no response possible. you can use Altera tools to create various onchip memories, and connect your logic to them. that is if you want to use the onchip memories the interface to on-board memories depends on the type of the memory, and that can be very different. SRAMs are very simple, DDR would be way more complex as example. anttiArticle: 102277
roiavidan@gmail.com wrote: > Hi Everyone, > > I am a student trying to build a project with Altera's Cyclone FPGA > board. > For my project, I need to access a large amount of data, which I would > like to store in the board's memory. I did not find any simple example > which could show me how to simply read and write to the chip's built-in > memory. > Is there any ready made interface I could use? > I would like not to use the Nios implementations, as they seem to be > very large and complex for me at this stage. > > Any help would be appreciated !!! > > Thanks, > Roi > Learn a bit about the Avalon bus, used by SOPC builder. You don't need a Nios II processor on the bus - you can happily link up standard Altera SOPC components and your own components (and Wishbone modules from opencores). It's a lot easier than trying to learn how to make DDR memory interfaces and the like.Article: 102278
I'm having a problem understanding a Synplicity timing report. For the
input ports of the design, the report gives column headings of 'port
name', 'falling user constraint', 'rising user constraint', 'arrival
time', 'required time', and 'slack'. The problem is, I can't make any
sense of what 'arrival time' and 'required time' are, and so I can't
work out how they arrived at the slack figure.
Here's an example for input port 'INPA', clocked by 'CLKA'. CLKA is
20ns. At the device pins, INPA has a setup of 8ns and a hold of 1ns
relative to CLKA, so this is how I constrained INPA:
define_input_delay {INPA} -rise 8 -fall 8 -min_rise -1 -min_fall -1
-ref {CLKA:r}
I think this is correct; the rise/fall times are relative to the
*next* clock edge, so in other words INPA will be available >= 8ns
before a clock edge, and will hold for >= 1ns after that clock edge.
This is what the timing report says:
Port clock cons(F) cons(R) AT RT SLACK
INPA CLKA (rising) 8.000 8.000 8.000 5.125 -2.875
So what does this mean? Why is the 'arrival time' always shown as
being equal to the setup constraint (it is in all the reports, and
even the picture in the docs shows this)?
This is what the manual says:
>Port Name Port name
>Reference Clock Source clock
>Falling User Constraint Specified falling input delay constraint
>Rising User Constraint Specified rising input delay constraint
>Arrival Time Clock latency - input delay constraint
>Required time Requested period - clock delay at destination -
> setup of destination
>Slack (max/min analysis) Required time - arrival time.
I haven't specified any latency on CLKA. My head is spinning - I'll be
eternally grateful to anyone who can explain this!
Jack
Article: 102279Start a project and open a new block diagram/schematic file. Once the block diagram workspace is open, double click anywhere within that space and the Symbol window will pop open. In the "Name" field type altsyncram and click on the "Ok" button, this will start the MegaWizard for Altera's on-chip RAM. Once you're in the MegaWizard's setup screens you will see a button labeled "Documentation". Clicking on this will give you documentation on how the internal RAM works. <roiavidan@gmail.com> wrote in message news:1147530640.153796.263270@i40g2000cwc.googlegroups.com... > Hi Everyone, > > I am a student trying to build a project with Altera's Cyclone FPGA > board. > For my project, I need to access a large amount of data, which I would > like to store in the board's memory. I did not find any simple example > which could show me how to simply read and write to the chip's built-in > memory. > Is there any ready made interface I could use? > I would like not to use the Nios implementations, as they seem to be > very large and complex for me at this stage. > > Any help would be appreciated !!! > > Thanks, > Roi >Article: 102280
Weng Tianxiang wrote: > 10 years ago when I was in China, there was a Chinese electronics > company in Beijing boasting every kind of FPGA chips in the world could > be decrypted and I really believed it, because they had many products > copied from other manufactures' products without designing: just copy, > including copies of PCB, FPGA and software driver. Yep ... anybody interested in having your PCB's produced in China?Article: 102281
On Sat, 13 May 2006 17:59:20 +0100, Jack Daly <jd1033@yahoo.com>
wrote:
>Here's an example for input port 'INPA', clocked by 'CLKA'. CLKA is
>20ns. At the device pins, INPA has a setup of 8ns and a hold of 1ns
>relative to CLKA, so this is how I constrained INPA:
>
>define_input_delay {INPA} -rise 8 -fall 8 -min_rise -1 -min_fall -1
>-ref {CLKA:r}
It looks like I got the constraint wrong - define_input_delay seems to
specify the total delay from the previous clock edge to when the
signal is available at the port. This explains why the arrival time is
the same as the constraint.
I've spent hours going through the docs and the website, and I
eventually found this out by checking the documentation on
*Synopsys's* set_input_delay, which Synplicity says is (almost) the
same. This is bizarre - there's not one picture or timing diagram
describing this in the entire manual, and the text describing it was
written by someone who certainly didn't understand it. Has anyone got
any useful pointers to a proper explanation of Synplicity constraints?
Jack
Article: 102282hi everyone!! i designed a fir filter with the Xinlinx ipcore two days ago. and i am facing a problem! in my design, i have two signal multiplied, one is sin(2*Pi*240k*t) and the other one is -sin(2*Pi*240k*t+F).so it is obvious that the result has a signal of 480K,which is undesired in my system. and this is what the filter for! the system clk of the filter is 48M and the sample rate is 4.8M! the problem i met is that the output of the filter has a freqency of 4.8M.i know it may have some relation to the sample rate,cause there is no more 4.8M clks! in additon ,i simulated the model in Matlab and the result turned out to be perfect!i got the coefficients of the filter from the simulation. could anyone help me? any comments would be appreciated! thanksArticle: 102283
Hi Phil, I am new to using these tools and designing with FPGA's. Can you tell me how to set static timing constraints on the pins that can only be reached with IOB FFs? Thanks & Regards, Srini.Article: 102284
Hi, My target architecture is ViretxII FPGA. I dont know whether there is any fanout limitation or not. But I was of the opinion that a driver having a high fanout might affect the timing in my design and I kept it to minimum(100). I could see some synthesis notes telling that some of the nets were replicated 'x' times bcoz of soft fanout limit of 100. I am meeting my timing constraints with this spevs. Now, if I increase the fanout limit to the default value of 10,000, will it affect my timing or will there be any change in the synthesis results?Article: 102285
On 13 May 2006 18:27:00 -0700, "light" <linhaidu840329@163.com> wrote: >hi everyone!! i designed a fir filter with the Xinlinx ipcore two days >ago. and i am facing a problem! in my design, i have two signal >multiplied, one is sin(2*Pi*240k*t) and the other one is >-sin(2*Pi*240k*t+F).so it is obvious that the result has a signal of >480K,which is undesired in my system. and this is what the filter for! >the system clk of the filter is 48M and the sample rate is 4.8M! the >problem i met is that the output of the filter has a freqency of 4.8M.i >know it may have some relation to the sample rate,cause there is no >more 4.8M clks! in additon ,i simulated the model in Matlab and the >result turned out to be perfect!i got the coefficients of the filter >from the simulation. could anyone help me? any comments would be >appreciated! thanks I'm not an expert on FIRs (sic), but, since you designed this filter only "two days ago", it's clear that you've spent almost no time trying to get it right yourself. Remember that, if anyone here decides to help, they'll be doing it for nothing, so it would be polite if you made some effort to write clearly, to express your problem clearly and to press your "shift" key now and again at the appropriate times. Instead, we're expected to respond to a continuous string of text which most of us wouldn't have written at age 10. If the style in which you ask for free help reflects how you document your design (and it makes sense to me that it should be at least as good), you should give it up now, because no-one will be able to maintain it.Article: 102286
>> 10 years ago...Chinese electronics company...boasting every kind of >> FPGA chips...could be decrypted...copies of PCB, FPGA and software driver. > >Yep ... anybody interested in having your PCB's produced in China? It's a good point. My first thought with production in China is "How do we stop them from copying it?" Perhaps that's a little unfair, because it's an important question, no matter to whom you transfer a design. Certainly, for any product in which I have a commercial interest, I wouldn't touch a processor which doesn't offer code protection. I'm not clear that the question has yet been addressed for all FPGAs. I'm thinking of the Altera mid-range, for which the program load signals aren't encrypted (as I understand it). I only mention that manufacturer because I know some of their products. Their competitors may have similar deficiencies.Article: 102287
Hi I'm new to fpga.. I do not have any dev-kit yet I'm looking for a fpga application to build a high res picture frame Input: Read a CF or SD card with jpg or gif or bmp picture 1280x1024 Output: DVI or LVDS as 1280x1024 60hz Function: Load a new picture(slide) every X second Advanced in the future: play video in native resolution (No need now) Please if anyone can point me in the right direction for what fpga to use? Any link to a project are welcome. Regards WiljanArticle: 102288
First of all - thanks alot for all of your quick replies. I will try to ask my question in a more precise manner. I need to build a piece of hardware ( I already wrote most of it in vhdl and as schematic designs ) that will manipulate a large amount of data - data that i believe cannot fit on-chip with the design itself. thus i would like to use one of the on-board memories available to me. i believe the cyclone board comes with SRAM (or SDRAM), and with this board i also have a 32mb flash card. what i'd like to know is how to use a simple ready-made interface for either one of these memories ( i don't care which one ). i do not want to write my own interface. i want the ability to read and write to memory without needing to know how the "memory internals" work. is there such a solution for me? many thanks again!! RoiArticle: 102289
if you dont know if the memory is SRAM or SDRAM how can anyone really help you ??? SRAM has virtually no interface needed at all, just supply address, ce, rd wr and thats it SDRAM needs special controller. if you dont want to use nios/SOPC then you need to find some SDRAM controller and adapt it to your own use. I bet finding the SDRAM controller from opencores should not take long ? If you ask for simple interface to SDRAM then all the SDRAM IP cores assume some local bus interface what in turn may not be what you call simple, but here nobody can really help you, SDRAMs just arent so easy to handle as SRAMs, sure some SDRAM IP cores are simpler and easier to use then others. But wich one suites your application the best is up to you to decide. AnttiArticle: 102290
srini wrote: > Hi, > My target architecture is ViretxII FPGA. I dont know whether there is > any fanout limitation or not. But I was of the opinion that a driver > having a high fanout might affect the timing in my design and I kept it > to minimum(100). I could see some synthesis notes telling that some of > the nets were replicated 'x' times [because] of soft fanout limit of 100. I > am meeting my timing constraints with this spe[c]s. Now, if I increase > the fanout limit to the default value of 10,000, will it affect my > timing or will there be any change in the synthesis results? If there were notes saying the nets were replicated, there will be changes in the synthesis results, though probably minor. The only way to find out if timing is an issue is to rerun your synthesis and place & route to see if your timing is worse (and by how much) or better!Article: 102291
I plan to use a Spartan3E device, namely XC3S500E-4PQG208C,
in my next project, but there are several questions I would like to ask:
1. what is their performance (relatively to the older Spartan 3 stepping 4)
a) maximal clock frequency;
b) peak and average power consumption at 250MHz (Vcc, Vaux, Vio);
c) average mW/MHz;
2. can I use a multiplier and its "neighbour" BRAM simultaneously,
i.e. is there enough routing?
3. can I clock the device (preferably differential mode) using
a 50MHz sine, extremely pure clock? It's Vpp can be adjusted
to meet the requirements (what are they?).
Best regards
Piotr Wyderski
Article: 102292> It's a good point. My first thought with production in China is "How > do we stop them from copying it?" The only way is to keep on deveoping new things faster than the old ones get copied. Witholding knowledge seems to be a "no-no" in evolutionary sense, this is how we are designed. The smarter a society, the more rewards it offers for knowledge creation. This is not to say I am all open, of course. The above strategy is probably optimized at an (inter?) species level, and I also am only an individual... This is part (not a predominant one, though) of the reason why I maintain a complete in-house tooling/development capability, once you do a design on a wintel machine it is anything but proprietary (can become public on a click beyond the control of the design owner). Dimiter ------------------------------------------------------ Dimiter Popoff Transgalactic Instruments http://www.tgi-sci.com ------------------------------------------------------ MikeShepherd564@btinternet.com wrote: > >> 10 years ago...Chinese electronics company...boasting every kind of > >> FPGA chips...could be decrypted...copies of PCB, FPGA and software driver. > > > >Yep ... anybody interested in having your PCB's produced in China? > > It's a good point. My first thought with production in China is "How > do we stop them from copying it?" Perhaps that's a little unfair, > because it's an important question, no matter to whom you transfer a > design. > > Certainly, for any product in which I have a commercial interest, I > wouldn't touch a processor which doesn't offer code protection. I'm > not clear that the question has yet been addressed for all FPGAs. I'm > thinking of the Altera mid-range, for which the program load signals > aren't encrypted (as I understand it). I only mention that > manufacturer because I know some of their products. Their competitors > may have similar deficiencies.Article: 102293
Piotr Wyderski <wyderski@mothers.against.spam-ii.uni.wroc.pl> wrote: > I plan to use a Spartan3E device, namely XC3S500E-4PQG208C, > in my next project, but there are several questions I would like to ask: > 1. what is their performance (relatively to the older Spartan 3 stepping 4) > a) maximal clock frequency; > b) peak and average power consumption at 250MHz (Vcc, Vaux, Vio); > c) average mW/MHz; > 2. can I use a multiplier and its "neighbour" BRAM simultaneously, > i.e. is there enough routing? > 3. can I clock the device (preferably differential mode) using > a 50MHz sine, extremely pure clock? It's Vpp can be adjusted > to meet the requirements (what are they?). First question to ask (if you are no really _big_ customer): Where to I get XC3SE from? -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 102294
Uwe Bonnes wrote:
"> First question to ask (if you are no really _big_ customer):
>
> Where to I get XC3SE from?
There is a small Polish shop which sells them:
http://www.kamami.pl/?id_k1=87&id_k2=76&id_k3=20
1 PLN = 0.26 Euro.
The largest device they have is 3S500, which costs 38,5 Euro @ 1
piece quantity. But I don't know whether they sell the chips outside
the country. Anyway, that's the reason I have decided to divorce
with Altera -- nobody sells their nice chips. :-(
Best regards
Piotr Wyderski
Article: 102295Hi All ! I saw on the web site lots of add-on, but is there "soon available" a kind of IO rear bracket to fit in the pc slot; to easily access IO from the rear of the pc ? Regards, X.Article: 102296
Hi all ! Do you if we can find the schematics and other spec, of the "viewable version" on the website ? Like, price, Io counts, and so on ? Regards, Xavier.Article: 102297
Piotr Wyderski <wyderski@mothers.against.spam-ii.uni.wroc.pl> wrote: > Uwe Bonnes wrote: > "> First question to ask (if you are no really _big_ customer): > > > > Where to I get XC3SE from? > There is a small Polish shop which sells them: > http://www.kamami.pl/?id_k1=87&id_k2=76&id_k3=20 > 1 PLN = 0.26 Euro. > The largest device they have is 3S500, which costs 38,5 Euro @ 1 > piece quantity. But I don't know whether they sell the chips outside > the country. Anyway, that's the reason I have decided to divorce > with Altera -- nobody sells their nice chips. :-( Make sure they have them on stock. Every other lokation I have seen, that lists them, state no explicit lead time. -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 102298
Piotr Wyderski <wyderski@mothers.against.spam-ii.uni.wroc.pl> wrote: >Uwe Bonnes wrote: >"> First question to ask (if you are no really _big_ customer): >> >> Where to I get XC3SE from? >There is a small Polish shop which sells them: >http://www.kamami.pl/?id_k1=87&id_k2=76&id_k3=20 >1 PLN = 0.26 Euro. >The largest device they have is 3S500, which costs 38,5 Euro @ 1 >piece quantity. But I don't know whether they sell the chips outside >the country. Anyway, that's the reason I have decided to divorce >with Altera -- nobody sells their nice chips. :-( www.elfa.se does, and they have office in Poland. For over the desk buying if so required. http://www.elfa.se/pl/kontakt.html Now if altera only had webpack for linux.. ;)Article: 102299
H have recently been working on a floating point unit for a Virtex 4 SX 35. I have a floating point adder and a floating point multiplier. The adder has 6 pipeline stages and the multiplier has 3 stages. The idea behind this project is to find out the kind of floating point performance that is possible in a modern FPGA. Our floating point format uses up to 15 bits of mantissa (with an implicit one) and up to 10 bits of exponent. We have managed to get a complex butterfly running at up to 250 MHz. So my question now is if these numbers are reasonable or if anyone knows of a reference to a faster fpu. We have already used some tricks to improve performance, for example by manually instantiating LUTs so that we can build an adder with a 2 to 1 MUX on one of the operands using only one LUT per bit. We have also tried to build up the design using RLOC:ed modules. This did not lead to improved performance as compared to a non RLOC:ed design. This could change once we start to fill up the device though. At the moment we are only utilizing about 20% of the FPGA. /Andreas
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z