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Dear Slurp, I do not know what you mean with easier, but the Altera design promises only 267 MHz max, that is 20% slower than the Xilinx design at 333 MHz. Nice try! Peter Alfke, XilinxArticle: 102476
In article <e488iq$b1d6@xco-news.xilinx.com>, Austin Lesea wrote: > > > > 1. what is their performance relative to the older Spartan 3 > > Almost identical. 3E uses the same process as 3. The families > are cost optimized for logic, and the other for IO. What I don't get is why the 3E "only" has such small devices if they are trully logic optimized? Personally, I would love to use a 208-pin version of an FPGA with 4+ million "gates"... My I/O requirements for my current project are minimal... the logic requirements are somewhat larger. --Toby.Article: 102477
Hi, A basic question what are the possible ways to make PowerPC communciate with the FPGA fabric. I know the Coreconnect buses is one way, APU is aother but is there any other way like shared memory etc. Please guide me to some paper or application note describing the connection between the PPC405 and FPGA fabric ThanksArticle: 102478
Guru schrieb: > For my design, which is implemented in Virtex-4 FX12 (speed grade -10) > I need to get an adjustable (in operation) clock of frequency 30 to 66 > MHz with the smallest possible increments. On the board I have 100MHz What is "smallest possible increment" If I spent a hell of stuff and money on it, I will have microhertz resolution with jitter down to a few picoseconds. Hey man, give us some numbers. Frequency resolution? Jitter? > oscillator from which I tried to get 400 MHz (the higher the frequency > the smaller the clock adjusting increments) using EDK 8.1's DCM (CLKFX > 4/1). From this DCM I also power the PPC at 200MHz (CLK2X). > I coupled the 400MHz clock to clock divider using rising edge as a > process reference and an integer counter. This configuration does NOT > work. The first problem is the frequency - EDK can compile my design if > I lower the frequency to 200MHz, which is unaceptable. The other > problem is a structure of my clock divider - if I make a process with > rising edge detection the clock divider can only be even (clock is > always divided by a factor of two!). > How to build a fast dual edge (DDR) clock divider in VHDL? Such a question from someone who calls himself Guru? ;-) > Is there any other way to solve my problem? There are many ways to skin a cat. One way is to have two counters, on counting on the rising edge, the other on the falling edge. Combining the two outputs in a clever fasion in a LUT can work. Or routing a signal to an output pin, make a connection to another pin back into the FPGA makes it possible to use the output DDR Flipflops. If you have a spare MGT, you can use it to make a real high frequncy DDS. Regards FalkArticle: 102479
Tobias Weingartner schrieb: > What I don't get is why the 3E "only" has such small devices if they > are trully logic optimized? Personally, I would love to use a 208-pin > version of an FPGA with 4+ million "gates"... My I/O requirements for > my current project are minimal... the logic requirements are somewhat > larger. Maybe because you application is not the typical one, that was found by evaluating sales/custumer requirements. A FPGA will never be a perfect match in IO, logic, whatever. Thats the "sacrifice" to flexibility. Regards FalkArticle: 102480
Does any buddy have any idea or guide me to some document explaing how the budgeting can be done in XilKernel on PP405. I need the kernel to tell me when a thread is hanged or when its execution passes the allocated time. ThanksArticle: 102481
Hi, Tobias, Falk said it: we are not a boutique. Spartan, even more than Virtex, is aimed at the high-volume market. If you have peculiar requirements, you must make trade-offs. C'est la vie. Peter Alfke, XilinxArticle: 102482
Peter, I'm a bit confused. Do you tell now that you can get as high as DDR2-667 on a Spartan3 device? Or did you actually mean on a V4? Regards, Luc On 16 May 2006 13:46:57 -0700, "Peter Alfke" <peter@xilinx.com> wrote: >Dear Slurp, I do not know what you mean with easier, but the Altera >design promises only 267 MHz max, that is 20% slower than the Xilinx >design at 333 MHz. >Nice try! >Peter Alfke, XilinxArticle: 102483
Nial- > I wouldn't have any problems paying normal_1off_price * 1.5 to be able to > get any quantity I want, even if this meant a longer lead time than > normal. Gallen offers an insightful, detailed explanation. Or you can apply the "Mom Test" for high tech products. If your Mom knows what it is (even vaguely) and might actually have a need to buy one, then you can get qty 1 at normal price or close to it. If not, then its out of the mainstream and its cost is going to be off the chart. -JeffArticle: 102484
Tobias Weingartner <weingart@cs.ualberta.ca> wrote: > In article <e488iq$b1d6@xco-news.xilinx.com>, Austin Lesea wrote: > > > > > > 1. what is their performance relative to the older Spartan 3 > > > > Almost identical. 3E uses the same process as 3. The families > > are cost optimized for logic, and the other for IO. > What I don't get is why the 3E "only" has such small devices if they > are trully logic optimized? Personally, I would love to use a 208-pin > version of an FPGA with 4+ million "gates"... My I/O requirements for > my current project are minimal... the logic requirements are somewhat > larger. What about using some module, like the Zefants (www.zefant.de) or the HydraX (http://www.hydraxc.com/)? -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 102485
>> One thing I would complain about is being forced to buy a MOQ of 48 >> devices when building prototypes. >> I wouldn't have any problems paying normal_1off_price * 1.5 to be able to >> get any quantity I want, even if this meant a longer lead time than >> normal. >> (BTW, this is a complaint at all FPGA distributors). >> Nial. You might try a specialized distributor such as Mouser for smaller quantities. It is my understanding that proto quantities are their specialty, so they are setup to have stock on hand of FPGAs and a very low minimum order qty (1pc.?). If you're interested in Mouser, they do stock Lattice FPGAs: http://www.mouser.com/latticesemi/ Hope this helps. Regards, Bart Borosky, LatticeArticle: 102486
Luc, let me un-confuse you: I referred to Virtex-4, but why do you ask? The OP did not specify a device family, and Virtex always outperforms Spartan. And Spartan is always lower priced than Virtex. That's why we have the two different families. I do not understand the reason for your question. Peter Alfke, Xilinx ApplicationsArticle: 102487
Let me explain one reason why distis are reluctant to break a standard tray of ICs: Practically all ICs nowadays come in plastic packages. Plastic inevitably absorbes moisture. When plastic packages with absorbed moisture are run through a molten solder bath, the humidity vaporizes and can cause the package to crack. That's a serious problem. The standard remedy is to bake all ICs if they have been in normal air for more than 24 hrs. You be the judge whether this is the real reason for the minimum purchase quantity requirements. Peter AlfkeArticle: 102488
Hi, > And you're surprized that they're not giving away their design? Who's talking about their design ? I'm not trying to create a cheap clone, but to drive the programmer using free software. I don't mind paying $38 (or even $150) for a good USB JTAG dongle, as long as I can use it. > Not to rain on your parade, but the typical FPGA engineer has spent a > hundred bucks or so on the part, a grand or two on the PCB, and 1/2 a > man-year on the code. $38 for a JTAG dongle is down in the noise. > > If it's hobby use you're after, you can stretch the JTAG signals off of > your card to another target. > > There is an open-JTAG effort on SourceForge. You might want to check > it out. I've checked that out, but it only support parallel port bit-banging adapters. I want to buy a USB JTAG programmer that I can actually use with free softwares. Why is there none available ? Laurent PinchartArticle: 102489
Laurent Pinchart wrote: > > I want to buy a USB JTAG programmer that I can actually use with free > softwares. Why is there none available ? > > Laurent Pinchart > I reread the thread and didn't see this asked. Why aren't you just using our iMPACT software. Linux is one of the supported OSes after all. You do have to compile the drivers into your Kernel as explained here: http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&getPagePath=22648 and the iMPACT software is included in the free WebPack download. Ed McGettigan -- Xilinx Inc.Article: 102490
Hi Ed, >> I want to buy a USB JTAG programmer that I can actually use with free >> softwares. Why is there none available ? >> > > I reread the thread and didn't see this asked. Why aren't you just > using our iMPACT software. Linux is one of the supported OSes after all. > > You do have to compile the drivers into your Kernel as explained here: > http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&getPagePath=22648 > > and the iMPACT software is included in the free WebPack download. Because iMPACT requires the Jungo binary driver, which has serious security issues. Linux offers a user-space USB library called libusb (available for win32 as well) which would let iMPACT access the Platform Cable USB without using a binary kernel driver. As I can't modify iMPACT to get rid of the Jungo dependency, I went the other way and tried to write a simple command line software to drive the cable. Unfortunately, the USB protocol seems to be classified top secret, and reverse engineering the EZUSB firmware didn't give me enough information. That's why I asked for more information on here. Laurent PinchartArticle: 102491
Sorry, based on subsequent postings, I'd like to clarify that a 333 MHz DDR2 (667 Mbps) solution exists for Virtex-4. In specific, take a look at XAPP721 and XAPP723, which use the ISERDES and OSERDES features in the Virtex-4 I/O block. XAPP721: High-Performance DDR2 SDRAM Interface Data Capture Using ISERDES and OSERDES http://www.xilinx.com/bvdocs/appnotes/xapp721.pdf XAPP723 - DDR2 Controller for ISERDES and OSERDES Interface Using Virtex-4 Devices http://www.xilinx.com/bvdocs/appnotes/xapp723.pdf For Spartan-3 fans, DDR2 SDRAM interfaces operate at 167 MHz (333 Mbps) using the -5 speed grade. For this solution, check out XAPP454, which also includes a reference design. XAPP454: Spartan-3 DDR2 Memory interface http://www.xilinx.com/bvdocs/appnotes/xapp454.pdf -- Steve KnappArticle: 102492
Peter Alfke wrote: > The best way to create clocks with tiny increments is using Direct > Digital Synthesis (DDS), a.k.a. phase accumulation. Peter, Original poster mentioned that he was using V4. Can he use the dynamic reconfiguration feature of the DCM? If memory serves this allows for changing the M and D values. Regards, Erik. --- Erik Widding President Birger Engineering, Inc. (mail) 100 Boylston St #1070; Boston, MA 02116 (voice) 617.695.9233 (fax) 617.695.9234 (web) http://www.birger.comArticle: 102493
Austin already replied on some of these topics ... http://groups.google.com/group/comp.arch.fpga/tree/browse_frm/thread/2f44e953c9d0052e/a7f66e74262ec61f?rnum=1&hl=en&_done=%2Fgroup%2Fcomp.arch.fpga%2Fbrowse_frm%2Fthread%2F2f44e953c9d0052e%2Fae5338cdf729767e%3Flnk%3Draot%26hl%3Den%26#doc_b4f2887d8472620e ... but I wanted to amplify a bit further on your second question. > 2. can I use a multiplier and its "neighbour" BRAM simultaneously, > i.e. is there enough routing? For most applications, you can simultaneously use both the block RAM and its neighboring embedded mutliplier. There is a limit, however, if and only if you use the block RAM in x36 mode (512 x 36). There is further information on page 46 (right hand column) in the Spartan-3E data sheet. http://www.xilinx.com/bvdocs/publications/ds312.pdf -- Steve KnappArticle: 102494
I think he can, but this gets us into the subject that Falk addressed, and I was too polite to mention: Be more specific! What is "smallest possible?" How much jitter is acceptable? If you can tolerate jitter, DDS is unbeatable. M/D still leaves big holes... Peter AlfkeArticle: 102495
Laurent Pinchart wrote: > Because iMPACT requires the Jungo binary driver, which has serious security > issues. > > Linux offers a user-space USB library called libusb (available for win32 as > well) which would let iMPACT access the Platform Cable USB without using a > binary kernel driver. > > As I can't modify iMPACT to get rid of the Jungo dependency, I went the > other way and tried to write a simple command line software to drive the > cable. Unfortunately, the USB protocol seems to be classified top secret, > and reverse engineering the EZUSB firmware didn't give me enough > information. That's why I asked for more information on here. > > Laurent Pinchart > I've never heard of any Linux security issue with the Jungo drivers and a quick Google search produced nothing indicating any problems. There was a single discussion on freshmeat.net in the windriver project, but there was no conclusive or specific issue mentioned and no other net sources. Based on the first comment on the freshmeat.net site by "omerz" it appears that you could put superuser/root permissions on the driver that theoretically could be misused, but if don't leave it as root then you get just normal user permissions. It seems like you want to go to whole lot of effort to redo work that already exists and ships for free. If so, then I guess everyone needs a hobby to work on. If you could cite a single instance of Linux box being "owned" through a Jungo USB/Parallel driver exploit I would be interested in seeing the reference. Ed McGettigan -- Xilinx Inc.Article: 102496
laurent has a point. i would like too having usb programs for fpga/jtag interface using libusb with sources available. linux version of ISE works without problems under FreeBSD but i can not do programming using iMPACT due problems with the cable[s] (parallel and USB). linux was supposed to be about open source not about free software. ---Article: 102497
Are there any examples out there that i can take as reference and build my SPI master on Virtex 4 FX ThanksArticle: 102498
To clarify, Altera's posted DDR2 SDRAM controller supports operation up to 267 Mhz. There is another core that supports 333 Mhz operation available by contacting your local sales rep. Paul Leventis Altera Corp.Article: 102499
1. Can it support LVDS inputs/outputs. (many of the FPGA's do, both the low and high end ) 2. Does it have on chip terminating resistors for the receiver inputs. If not, you would have to put them on the PCB. 3. You might be interested in the VCCIO voltages for the banks running the LVDS. Some FPGA's want this voltage to be 2.5, which would necessitate another power source of some kind. 4. I'm assuming by high-speed LVDS you mean a SERDES type interface. The question then is, can the FPGA handle your speed? For instance: if you have 4 lanes with a x7 format running at 66MHz your serialized lanes will be running at 66MHz x 7 = 462Mbps. Dealing with a SERDES interface requires a PLL (for instance) to generate the high-speed clock from the system clock (66MHz in my example). The jitter spec on the FPGA becomes important because it will dictate how much skew the rest of the system (cable, board, etc) can tolerate. <praveen.sethuram@gmail.com> wrote in message news:1147762433.451152.157990@i40g2000cwc.googlegroups.com... > hi all, > wat all the basic requirements needed to be analysed before selecting a > FPGA chip for using high speed LVDS. > thanks in advance > praveen >
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