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"alpha" <zhg.liu@gmail.com> writes: > I designed a 2-way issue out-of-order processor recently. It has 8 > slot deep reorder buffers and 4 execute unites - 2 ALUs, 1 Branch and 1 > L/S. Simple branch taken scheme. > It takes about 9000 LC(s) in a Xilinx V4 FX12 FPGA running 33 MHz with > 1.2-1.5 IPC. Sounds like an interesting challenge, and perhaps useful if you plan to move it to an ASIC, but I wouldn't think it would be too useful in an FPGA, since it's not too difficult to make a single-issue processor run at more than 100 MHz in a V4 part. Are there any published HDL designs for out-of-order superscalar processors? Everything I've looked at has been single-issue in-order.Article: 102676
pbdelete@spamnuke.ludd.luthdelete.se.invalid writes: > Which Spartan3 device are you using? There is an eratta for the > XC3S1500 stating that some of the engineering sample parts have a > readback bug in them. > > Is there a workaround .. ? The workaround is to use production (non-ES) XC3S1500 parts.Article: 102677
Austin Lesea wrote: > Found them! > http://www.selse.org/presentations/UIUC_SBorkar_April_11_2006.pdf Brilliant! Thanks :) -- PeterArticle: 102678
Eli, I don't know whether this is of any use: http://www.xilinx.com/bvdocs/appnotes/xapp502.pdf Apologies if you have already seen it. -- Peter Eli Hughes wrote: > This is a very simple question, but is something that I have taken for > granted with all of the nice tools. For the Xilinx FPGAs (Spartan, > Virtex), the ISE tools generated a .bit file for configuration for > specific device. > > If I wanted an MCU on my PCB to hold the configuration data and > configure the FPGA on my target board, could I literally just send in > the the data in the .bit file bit by bit with the CCLK, DIN, etc pins? > Or do I convert this file into a different hex file for an direct bit > for bit configuration. > > > Thanks, > Eli HughesArticle: 102679
Eli I have doen this before with a Power PC and Virtex EM, the confgiuration will give you out a raw hex file which contains all the data need to configure the device, I then worte a simple script which configured this into a C array which could could be read through by the application software and written to the FPGA which was being configured via the select MAP mode. I beleive it is also possible to get an S Record version out which can be used to download into flash directly via a bootloader, the only reason i did it the way i did was our bootloader was not that complicated. I have the schematics for this and the script if that would help ? hope this helps AdArticle: 102680
hum, lasted time I checke the readback was not available on any S3 production silicon at all due to wafer bug. has it really been fixed now? If so then its a good thing of course. AnttiArticle: 102681
"Roger Bourne" <rover8898@hotmail.com> wrote in message news:1147982908.936074.101820@y43g2000cwc.googlegroups.com... > Hello all, > > I recently learned/heard that when implementing a IIR digital filter > of direct form I, the gain has to be finely adjusted with an > additionnal module on the output. Otherwise, the 0dB level will not be > perfectly reached in your passband (filter is low pass) and e.g. > consequently a digital value that is suppose to be 40000.0000 will be > 4000.0001. > Essentially, I imagine this output module to be a multiplier of > 1.0000000XXXX or 0.99999XXX > > I was led to believe this problem does not arise with digital filter > implementations of direct form II. > > Is this true ? > Looking over the flow diagrams of the 2 type of filters, I do not > understand why one form would require a gain adjustement and the other > would not. > > P.S The filter is being implemented in an FPGA, not in a DSP. > P.S The passband ripple is tiny, below 1e-4dB I haven't heard this myself. I would think that any error is simply quantization (round-off error), i.e. it wouldn't exist if implemented with infinite-precision arithmetic and isn't intrinsic to the DF I. But some filter forms do fair better than others in terms of numerical issues such as round-off, so it is possible that one implementation might be "better" than another, even though they are theoretically equivalent. (In actuality, they are only equivalent if implemented with infinite-precision arithmetic.) Is your FPGA filter doing floating-point? I'm curious, as that seems pretty uncommon in the FPGA world. "In theory, theory and practice are identical. But in practice, they are not!" -- Jon Harris SPAM blocker in place: Remove 99 (but leave 7) to replyArticle: 102682
Hello Brad, Thanks for your reply. It seems I was doing everything similiarly with one exception though that I didn't enter the IOSTANDARD and DRIVE parameters in my UCF file. Without this, there was no signal present on AD17. Actually, leaving only DRIVE = 16 for the clock output does its job (the signal is feeded back where it should be) and could end the topic, however I've got yet another question. When I set the IO standard for sram_clk_fb, as in your example, I cannot get through the PAR stage as it terminates with errors: ERROR:Place:311 - The IOB ZBTRAM_CLKFB_PIN is locked to site IOB_X1Y51 in bank 4. This violates the SelectIO banking ERROR:Place:207 - Due to SelectIO banking constraints, the IOBs in your design cannot be automatically placed. This confuses me a lot since it's not the first time I've got this message (it happens quite frequently when I set IO standards manually). There are no other specific constraints in my design that could mess with those settings (or at least I think there aren't), I just make some simple pin assignments. Regards, Tomasz Dziecielewski >Hello Tomasz, > >Here is part of my UCF file > >NET sram_clk_pin LOC = AF7; >NET sram_clk_pin IOSTANDARD = LVCMOS33; >NET sram_clk_pin DRIVE = 16; >NET sram_clk_pin SLEW = FAST; >NET sram_clk_fb LOC = AD17; >NET sram_clk_fb IOSTANDARD = LVCMOS33; > >As you can see, I am driving AF7 and receiving feedback on AD17. > >The problem might be on the schematic that both signals are labeled with the >same name, they have to, since they share common copper. I recall that the >designer put a comment on AD17 indicating that it is feedback although I >didn't trace the paths to see if there would be a difference in switching >the two lines. > >I am also using, per Xilinx instruction, two DCMs, one for the internal >workings and one to drive the external clock pin. > >I am using 100 MHz, clk90, with an initial tap delay of 55 or about 2.1ns. >Not too sure about my reset circuitry. Hope you read VHDL: > > sbuf_external_clock_pin_dcm: sram_dcm > port map ( > clkfb_in => sbuf_domain_m_clk_fb, > psclk_in => sbuf_domain_d_psclk, > psen_in => sbuf_domain_d_psen, > psincdec_in => sbuf_domain_d_psinc, > clkin_in => sbuf_domain_m_clk, > rst_in => sbuf_domain_m_reset_raw, > clk0_out => open, -- 170 taps > clk90_out => sbuf_domain_m_clk_pin, -- 22 taps to 74 taps > clk180_out => open, -- 160 taps > clk270_out => open, -- 100 taps to 120 taps > locked_out => sbuf_domain_m_lock, > psdone_out => sbuf_domain_d_psdone ); > > -- Set the following: > -- CLKIN FREQ 100 MHz > -- PHASE DELAY VARIABLE_POSITIVE 55 taps > -- CLKIN EXTERNAL > -- Feedback External Single > > sbuf_domain_m_reset_delay_SRL16 : SRL16 > generic map ( > INIT => X"0000") > port map ( > Q => sbuf_domain_m_lock_delayed, > A0 => '1', -- 16 clock delays > A1 => '1', > A2 => '1', > A3 => '1', > CLK => sbuf_domain_m_clk, > D => sbuf_domain_m_lock ); > > sbuf_domain_m_reset_process: process(sbuf_domain_m_clk) > begin > if( sbuf_domain_m_clk'event and sbuf_domain_m_clk='1') then > sbuf_domain_m_reset <= not( sbuf_domain_m_lock and >sbuf_domain_m_lock_delayed ); > end if; > end process; > > > >Brad Smallridge >Aivision dot comArticle: 102683
Austin Lesea wrote: > Found them! > > http://www.selse.org/presentations/UIUC_SBorkar_April_11_2006.pdf Thanks Austin ... Great set of slides, wish I had seen the talk to go with them :) I see this industry is headed down the design for defect management path too, and the huge wastes behind the zero defect policies are finally going to be addressed in at least that consumer market.Article: 102684
Hi while looking for help at Xilinx website I found already application notes about the DDR2 and Virtex5, but I am still having some trouble even with V4 DDR2 so I am looking for anyone who has succesfully used EDK DDR2 IP Core, it sounds and looks like easy to use, specially for the V4 the clocking requirements are relaxed, but well it doesnt work, well I am still fighting with it. To my big disappointment there are no example design available for EDK that use DDR2. So I would be very thankful for any links points info an the use of DDR2 IP Cores with EDK for V4, yes I know the BEE2 project but those designs are all for DDR2 and V2Pro. I might be able offer some reward for any actual help in this matter AnttiArticle: 102685
Hi, I want to generate this kind of signal with my spartan 3 XCS200 : http://www.abcelectronique.com/forum/attachment.php?attachmentid=4490 I am using the DCM to multiply my oscillator ( 50Mhz ) by 2 ; but, I don't succeed to have this "3.8 ns plate" for each level. I have it only for high logic level. How can I do ??? ( My english is awful , sorry )Article: 102686
Hi, I'm a beginner to Verilog. Is there any standardized or "typical" Application Interface Layer for accessing general memory in Verilog? I found a document showing an example of how to access Block Select RAM in Spartan II. (www.xilinx.com/bvdocs/appnotes/xapp173.pdf) I also found an internet page showing a small example (www-ee.eng.hawaii.edu/~msmith/ASICs/HTML/Book/CH12/CH12.8.htm) Both examples end up in something like module MYMEM(CLK, WE, ADDR, DIN, DOUT) My question is; is this the accepted common way of accessing general memory? Are there any good links or references for this subject? Thanks DeMarcusArticle: 102687
Hi everybody! I would like to use the ethernet port on my ML401 development board (equipped with a Xilinx Virtex4 FPGA and Marvel Alaska 88e1111 PHY), but I don't know what to do? Can you help me? Thanks, MaxArticle: 102688
http://direct.xilinx.com/bvdocs/appnotes/xapp807.pdf Cheers, JonArticle: 102689
Scope wrote: > http://www.abcelectronique.com/forum/attachment.php?attachmentid=4490 This appears to require registration. Can you put it somewhere public? -- PeterArticle: 102690
Austin Lesea wrote: > Found them! > > http://www.selse.org/presentations/UIUC_SBorkar_April_11_2006.pdf Austin, Just a curiosity-driven long-shot, but did the presenter (or anyone else) give any clues as to what the interconnect fabric would be like? How similar to FPGA routing is it? -- PeterArticle: 102691
The board I'd like to use (ML401) is equipped with a Virtex4 LX (not FX) FPGA; The AppNote807 is about V4FX, that has an embedded TEMAC core, so it's not usefull for me. Thanks anyway, MAxArticle: 102692
thanks Rob i will certainly take this.Article: 102693
Fizzy schrieb: > Then if that's the case DCM is only for high frequency what are my > option to have low skew and jitter on clock. Actually let me explain a > little bit so i can ask the question properly. I am designing an > application which will run on 200 Hz (Hertz just). I ahve system clock What is the problem? 100 MHz / 500000 = 200 Hz 100 MHz / 1250000 = 80 Hz No jitter. As easy as it gets! > running at 100 MHz. I have PowerPC405 running at 100 Mhz. The custom > design is connected to PPC405 through PLB. What is the best way to > clock now. What i was thinking earlier is to have on chip clock comming > to DCM and extract the required clock from it (200 Hz) but you guys > saying its not possible so waht are my options? Use a *zensored* counter! Regards Falk P.S. Of cource, dont use the 200 Hz out of the counter directly as a clock. Run the logic on the 100 MHZ and use a 200Hz clock enable. I gues the 200Hz is only for interupt generation?Article: 102694
"Peter Alfke" <peter@xilinx.com> wrote in message news:1147896100.445238.78820@i39g2000cwa.googlegroups.com... > This is what I wrote 15 yars ago, and it still applies: > "..Note that there can never be a decoding glitch when only one select > (address) input changes. (Even a non-overlapping decoder cannot > generate a glitch problem, since the node capacitance will retain the > previous logic level until the new pass gate is activated a fraction of > a nanosecond later) > When more than one input changes "simultaneously", the user must > analyze the logic output for any possible intermediate address code > permutation. If any of them would produce a different output, the user > must assume that a glitch might occur. If all of the possible address > variations produce the identical output, then the user can be sure that > there will be no glich at the output. > > The designers of synchronous systems generally do not worry about such > glitches, since synchronous designs are inherently immune to data > glitches, except on clocks and asynchronous Set or reset inputs." > > I hope this helps > Peter Alfke, 15 years later still at Xilinx... Thanks a lot Peter. It DID help sort out this protential problem :) Btw.. I compressed the URL at http://tinyurl.com/fufdtArticle: 102695
<fpga_toys@yahoo.com> wrote in message
news:1148019845.176556.277810@g10g2000cwb.googlegroups.com...
>
> Any of the Xilinx guys do a performance study for wider adders with
> this new carry architecture in relation to carry select or Brent-Kung
> FPGA implementations, or maybe able to offer revised versions of those
> for the V5 given new tradeoffs with the 6-LUT and carry changes?
Yes indeed. Obviously the new LUT6 architecture changes the playing field
somewhat when it comes to arithmetic. There has been plenty of work done on
identifying the optimal mappings for basic arithmetic functions so the tools
can do a Good Job. (Nominally. :))
The improvements in the carry chain speed are substantial. Although there's
still a noticable hit when getting on and off them, the raw propagation
speed is a real step up from previous generations. The fabric speed is
really catching up to the embedded IP blocks now...
Cheers,
-Ben-
Article: 102696>Scope wrote: >> http://www.abcelectronique.com/forum/attachment.php?attachmentid=4490 > >This appears to require registration. Can you put it somewhere public? > >-- Peter > Sorry, try this >>>>> http://www.hiboox.com/image.php?img=g3t-rnp.gif Regards RGArticle: 102697
their webmaster is on hawai vaccation as usual ! anttiArticle: 102698
Hi,
on the upcoming ECOOP conference in Nantes, France, the 3rd European
LISP Workshop will be held. Part of that workshop is a breakout group
on hardware for LISP systems:
The Breakout group "Reclaim the Hardware Design Space!" on the 3rd
European Lisp Workshop is about creating hardware that is suited to
dynamic programming languages in general, and LISP in particular. We
will be investigating current hardware technologies to find out what
they have to offer for systems that are dynamic from the ground up.
The breakout group is meant to provide a meeting point for researchers
and practitioners working on hardware implementation techniques for
dynamic languages. To participate, you should know something about the
implementation of dynamic languages, about hardware, or both. You are
not required to actually have created a LISP machine yourself, but you
should be aware of some of the associated issues in order to take part
in the discussion.
Some of the topics of interest are:
* Implementation of LISP-friendly CPUs in hardware
* Hardware assisted garbage collection
* Self-Synthesis and Hardware/Software Co-Design
* LISP based ASLs for hardware description and synthesis
* Techniques for CPU implementation on FPGAs
* Reengineering ancient CPUs in software or hardware
In the breakout group, time will be provided for researchers to
demonstrate their achivements and position. If you have something to
present, please let us know and we will provide you with presentation
time. You may also publish information on this web site in order to let
participants get some idea of what you are working on in advance.
We hope that the breakout group will help in advancing dynamic hardware
and provide for a place for researchers and practitioners to work
together.
3rd European LISP Workshop: http://lisp-ecoop.bknr.net/
LISP Hardware breakout group: http://vaxbusters.org/workshop/
Regards,
Hans
Article: 102699Dan: Using a production XC3S200-FT256-4C on a Digilent Spartan 3 starter kit, nothing funny, hundreds of them must be in use out there... I haven't found anyone complaining that they can't do readback on them, but not many people are doing readback on S3s (apart maybe from the Xilinx Rosetta program) thanks
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