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Messages from 94475

Article: 94475
Subject: Re: "failed to create empty document"
From: "Symon" <symon_brewer@hotmail.com>
Date: Thu, 12 Jan 2006 10:24:40 -0000
Links: << >>  << T >>  << A >>
<krishnans@hotmail.com> wrote in message 
news:1137031629.836968.325050@o13g2000cwo.googlegroups.com...
>
> Also you may need this patch forWInXP
> "MFC applications leak GDI objects on computers that are running
> Windows XP"
> http://support.microsoft.com/?id=319740
>
FWIW, I (probably!) downloaded this patch from 
http://www.cakewalk.com/Support/kb/kb2005243.asp
Cheers, Syms. 



Article: 94476
Subject: Re: ISE 8.1i WebPack available
From: "Leon" <leon_heller@hotmail.com>
Date: 12 Jan 2006 02:57:04 -0800
Links: << >>  << T >>  << A >>
Modelsim has to be downloaded and licensed seperately.

Leon


Article: 94477
Subject: Re: Conflicts between ISE4.2 and win2000 SP4
From: "Leon" <leon_heller@hotmail.com>
Date: 12 Jan 2006 03:01:06 -0800
Links: << >>  << T >>  << A >>
It was a long time ago, but I think Xilinx told me to download an
earlier version of iMPACT. I only had a problem with CPLDs, IIRC. It
found the cable OK, but they wouldn't program.

Leon


Article: 94478
Subject: Re: DSP soft processors
From: "Leon" <leon_heller@hotmail.com>
Date: 12 Jan 2006 03:05:00 -0800
Links: << >>  << T >>  << A >>
I have seen one or two, but it was a long time ago. People doing DSP on
FPGAs prefer implementing the function directly in hardware as it's
much faster and more cost-effective.

Leon


Article: 94479
Subject: Re: DSP soft processors
From: Ray Andraka <ray@andraka.com>
Date: Thu, 12 Jan 2006 07:18:06 -0500
Links: << >>  << T >>  << A >>
Sudhir.Singh@email.com wrote:
> Hi folks,
> are there any DSP soft processor cores for fpgas available. I have done
> a search and only found 32 bit RISCs but no DSP processor cores.
> Thanks in advance
> Sudhir
> 


Why?

If you have  DSP function to perform, do it in hardware, it is much 
faster and consumes less power.  Otherwise, use a dedicated DSP 
microprocessor...again, far faster and consumes less power, and more 
supportable.

Article: 94480
Subject: Newbe Startup Time Question
From: dannymarcus@gmail.com
Date: 12 Jan 2006 04:41:06 -0800
Links: << >>  << T >>  << A >>
Hi,

I'm completely new to FPGA:s.
Assume the FPGA is up and running and all startup settings are
initiated. How long
does it take to load a new logic scheme into the FPGA? For instance if
I want to
change the scheme from some previously uploaded image algorithm to some
encrypter algorithm, how long time would that take in average? Are we
talking microseconds or
even seconds?

Thanks
Daniel


Article: 94481
Subject: Xilinx Vertex II Pro with tow VDEC videodevices
From: Ludwig Lenz <Ludwig.Lenz@gmx.de>
Date: Thu, 12 Jan 2006 13:55:57 +0100
Links: << >>  << T >>  << A >>
Hello,

I want to use a second Digilent VDEC videodevice at one time with another on
the Vertex II Pro Developmentsystem board. Because this board has only one
highspeed Digilent Connector (J37), I need to construct an adapter for the
lowspeed Connector (J5 - J6). 

Does someone know, where I can get an Hirose FX2 connector (in
germany/europe)? Can I use J5 - J6 with the signal-clock, which is
necessary for a Digilent VDEC videodevice (54MHz)?  

Thanks,
Ludwig

Article: 94482
Subject: Re: PCI compliance ?
From: "Pouria" <pouria@hotmail.com>
Date: Thu, 12 Jan 2006 07:28:32 -0600
Links: << >>  << T >>  << A >>
Hi
Just use level shifters between the PCI and FPGA .... Have made that my
slef and works fine ... Send me an email for schemtics 

Regards,
p

>Hello,
>
>I have to design a board with a PCI interface which shall be compliant
with
>a larg range of PCI versions !
>3.3V 32bits / 33Mhz
>5V 32bits / 33Mhz
>3.3V 64 bits / 66 Mhz
>
>The board should use V2P xilinx FPGA so what bothers me is the 3.3V and
5V
>compliance.
>Is there a simple solution to achieve this ?
>
>Thanks.
>
>Stéphane.
>
>
>
>



Article: 94483
Subject: Re: Newbe Startup Time Question
From: "Gabor" <gabor@alacron.com>
Date: 12 Jan 2006 05:55:42 -0800
Links: << >>  << T >>  << A >>
dannymarcus@gmail.com wrote:
> Hi,
>
> I'm completely new to FPGA:s.
> Assume the FPGA is up and running and all startup settings are
> initiated. How long
> does it take to load a new logic scheme into the FPGA? For instance if
> I want to
> change the scheme from some previously uploaded image algorithm to some
> encrypter algorithm, how long time would that take in average? Are we
> talking microseconds or
> even seconds?
>
> Thanks
> Daniel

This depends on the part.  If you use the largest FPGA's and a serial
loader
you could be in the seconds range.  Many FPGA's have parallel
configuration
interfaces if you're willing to give up the I/O pins for it.  This can
reduce timing
to low milliseconds for the whole part or even microseconds if the part
can
be partially reconfigured.

Lattice has some new parts that are marketed as CPLD's, but are really
FPGA's.
The MACHXO series allows you to reconfigure the internal flash while
the part
is still running the previous version.  Then you can switch to the new
program
quite quickly.  The largest of these parts has only 2280 LUTs, though.
Large
FPGA's can have 150,000 LUTs.

If you know how large a part you need to do your job, you can generally
find
the configuration time in the data sheet.  You might find for example
that a
medium sized FPGA has 2 megabits of configuration data and can load
serially at 20 MHz, so configuration would take about 100 milliseconds.
 There
is usually some additional time for the part to initialize itself, but
small compared
to the serial bit loading.

If you're serious about quickly changing configuration you need to look
at
parallel configuration methods and partial reconfiguration.  Together
these
attributes can allow you to quickly and seamlessly switch
functionality.
However expect a lot of headaches in the design process.  Google for
partial reconfig in this group.

Hope this helps,
Gabor


Article: 94484
Subject: Re: UCF-File problem
From: "Gabor" <gabor@alacron.com>
Date: 12 Jan 2006 06:03:25 -0800
Links: << >>  << T >>  << A >>

Sean Durkin wrote:
[snip]
> There's a configuration switch you can set to "Allow unmatched
> LOC"-attributes which would allow you to finish the flow despite of the
> error, but that's not what you want since obviously there's something
> wrong with your design which you otherwise wouldn't notice.
>
> cu,
> Sean

Actually this can be quite useful, since you'll have the reports that
follow the "translate" process.  This can show you whether your clock
has actually been removed from the design or somehow got re-named
so it didn't match the LOC constraint.  A look at the pad report can
show this problem.

Godd luck,
Gabor


Article: 94485
Subject: Re: How to create a delay BUF?
From: backhus <nix@nirgends.xyz>
Date: Thu, 12 Jan 2006 15:27:46 +0100
Links: << >>  << T >>  << A >>
wuyi316904@gmail.com schrieb:
> Hi,in my project,i need some bufs to delay some signals,but after
> synthesising,the code:#20 does't have any affects.Is there some way to
> keep the delay?For example,some constraint for synthesis or other.
> 
Hi,
The verilog # operater and the vhdl after statement are not 
synthesizable and (as you already observed) therefore ignored during 
synthesis.

As mentioned before by cationebox, Flipflops/registres are a proper way 
to delay signals by n clock periods (n = number of serialized ffs ).

Have a nice synthesis
   Eilert

Article: 94486
Subject: Re: Newbe Startup Time Question
From: "Antti Lukats" <antti@openchip.org>
Date: Thu, 12 Jan 2006 15:45:43 +0100
Links: << >>  << T >>  << A >>
<dannymarcus@gmail.com> schrieb im Newsbeitrag 
news:1137069666.760894.93190@g47g2000cwa.googlegroups.com...
> Hi,
>
> I'm completely new to FPGA:s.
> Assume the FPGA is up and running and all startup settings are
> initiated. How long
> does it take to load a new logic scheme into the FPGA? For instance if
> I want to
> change the scheme from some previously uploaded image algorithm to some
> encrypter algorithm, how long time would that take in average? Are we
> talking microseconds or
> even seconds?
>
> Thanks
> Daniel
>
milliseconds to seconds in worst case, dependig the configuration type and 
solution being used

-- 
Antti Lukats
http://www.xilant.com 



Article: 94487
Subject: Re: Newbe Startup Time Question
From: "DeMarcus" <dannymarcus@gmail.com>
Date: 12 Jan 2006 07:31:09 -0800
Links: << >>  << T >>  << A >>
Thanks. I'll look around in some whitepapers I got hold of.


Article: 94488
Subject: Re: Why 'a plurality of N' must be used for 'N' in patent claims
From: soar2morrow@yahoo.com
Date: 12 Jan 2006 08:53:34 -0800
Links: << >>  << T >>  << A >>

> I am with the jury on this one.

Which is exactly my point: this contract was reviewed by lawyers for
accuracy and they felt that "bodily injury" includes death. So much for
legal "precision".

Tom


Article: 94489
Subject: Xilinx simullation error
From: "Brad Smallridge" <bradsmallridge@dslextreme.com>
Date: Thu, 12 Jan 2006 09:01:22 -0800
Links: << >>  << T >>  << A >>
After switching from ISE 6.i to 7.i (What is the i anyway? integer?)
I find that I can simulate a dcm ok but can't simulate a BRAM.
I get this error:

# ** Error: (vcom-11) Could not find 
C:/Modeltech_xe_starter/win32xoem/../xilinx/vhdl/xilinxcorelib.blkmemdp_v6_1.

I get this error on the ISE simulator which I'm finding seems to be a 
disguised
version of the ModelSim simulator.  Can anyone comment on the politics
behind this move?

Brad Smallridge
aivision dot com



Article: 94490
Subject: boundary scan of altera epm570F
From: "colin" <colin_toogood@yahoo.com>
Date: 12 Jan 2006 09:41:43 -0800
Links: << >>  << T >>  << A >>
Guys

I'm going home with a problem unsolved.

After an ALTERA EPM570F has been programmed can it still be boundary
scanned using the original BSDL file or does the fact that IO pins are
now hard wired as Input or Output mean that they can only be scanned as
Inputs or Outputs. (nneding the BSDL to be changed).

I have spent an hour on the ALTERA website and it is not at all clear.
In some places it suggests that ISP is the last JTAG thing that would
be done.

Apologies for perhaps being very slightly off topic but a simple yes or
know from someone who knows is all that I'm hoping for.

Regards

Colin


Article: 94491
Subject: Re: Will ISE 8.1 work together with EDK 7.1?
From: "Alan Nishioka" <alan@nishioka.com>
Date: 12 Jan 2006 09:53:37 -0800
Links: << >>  << T >>  << A >>
Zara wrote:
> On 11 Jan 2006 22:22:55 -0800, "Alan Nishioka" <alan@nishioka.com>
> wrote:
>
> >Zara wrote:
> >> BTW, someone from Xilinx told me some time ago that EDK 8.1 will, at
> >> last!, support C++. I hope it will.
> >
> >C++ works for me in 6.3 and 7.1  What doesn't work?
> >I had to add extern "C" to a few header files.  I don't use many C++
> >features, however.
> >
> Whenever I use templates, chaos begins...

I see.  Not something I use.  I assumed that it would work since it is
gcc, but I guess more stuff needs to be ported.

Alan Nishioka


Article: 94492
Subject: Re: Virtex2 I/O state in configure phase
From: Jerzy Gbur <furia1024@wp.pl>
Date: Thu, 12 Jan 2006 20:16:25 +0100
Links: << >>  << T >>  << A >>
Hello!

> As I wrote earlier I'll be at work next tuesday, and I'll try to use 
> your advices.
> I'll post results on this topic.

Time is going so fast....

Ok, my fault, It is following reason of V2 behaving, I've checked lines 
which was pulluped. That's all, false alert. I'm sorry, I've disturbed you.

Kind regards

Jerzy Gbur

Article: 94493
Subject: Re: boundary scan of altera epm570F
From: "Subroto Datta" <sdatta@altera.com>
Date: 12 Jan 2006 12:12:21 -0800
Links: << >>  << T >>  << A >>
Hi Colin,

    In the Assembler settings tab, select 'Always enable input
buffers' and recompile the design.

Hope this helps,
Subroto Datta
Altera Corp.


Article: 94494
Subject: FPGA Journal Article
From: "Kevin Morris" <kevin@techfocusmedia.com>
Date: 12 Jan 2006 12:15:13 -0800
Links: << >>  << T >>  << A >>
I'm writing a feature article for FPGA Journal (www.fpgajournal.com)
about FPGAs and the re-birth of the electronics hobbyist.  My theory is
that electronics as a hobby went through a "dark age" period, maybe
from the early/mid 1970s until recently becuase of the inaccessibility
and cost of designing with state-of-the-art technology.  Radio Shack
shifted their focus from 50-in-1 project kits and hobbyist parts to
selling toys, cell-phones, and stereo equipment.

Now, with the emergence of low-cost, high-capability FPGAs, development
boards, and design software, I see a new age of hobbyist activity
beginning (as often evidenced in this group).

I'm looking for a few people that would be willing to express views on
this topic for the article.

I know, Austin will probably post a strong technical argument that
Xilinx FPGAs are uniquely attractive to the hobbyist, somebody from
Altera will send me a Cubic Cyclonium prototyping paperweight (they're
very cool), and Actel and Lattice people will post just to remind us
that they have low-cost kits too, but I'm primarily interested in some
info from real, live, "working" hobbyists.

Any takers?


Article: 94495
Subject: Re: How to create a delay BUF?
From: Jeremy Stringer <jeremy@_NO_MORE_SPAM_endace.com>
Date: Fri, 13 Jan 2006 09:29:24 +1300
Links: << >>  << T >>  << A >>
backhus wrote:
> wuyi316904@gmail.com schrieb:
>> Hi,in my project,i need some bufs to delay some signals,but after
>> synthesising,the code:#20 does't have any affects.Is there some way to
>> keep the delay?For example,some constraint for synthesis or other.
>>
> Hi,
> The verilog # operater and the vhdl after statement are not 
> synthesizable and (as you already observed) therefore ignored during 
> synthesis.
> 
> As mentioned before by cationebox, Flipflops/registres are a proper way 
> to delay signals by n clock periods (n = number of serialized ffs ).

Probably worth mentioning DCMs/PLLs as well here - these allow you to do 
fine phase shifting on a clock, which can then be used (assuming clock 
domain boundaries are crossed correctly) to clock flip-flops with 
different timings than your original clock.

Jeremy

Article: 94496
Subject: Re: FPGA Journal Article
From: hmurray@suespammers.org (Hal Murray)
Date: Thu, 12 Jan 2006 14:32:50 -0600
Links: << >>  << T >>  << A >>
The low cost starter kits are great - not restricted to FPGAs.
  Both Microchip/PIC and Atmel/AVR have starter kits under $100,
  available from Digikey.

Anybody got a list of hobbyist friendly vendors?  I'm thinking
of places like Digilent.



The problem with FPGAs and CPLDs that I see is getting the raw
parts in small quantities at hobbyist friendly stores.

Most distributors are interested in large volumes.  They aren't
really setup for hobbyists.

The Xilinx store still doesn't carry the small Coolrunner IIs.
Digikey doesn't stock any of them.

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 94497
Subject: Re: FPGA Journal Article
From: "Antti Lukats" <antti@openchip.org>
Date: Thu, 12 Jan 2006 21:39:55 +0100
Links: << >>  << T >>  << A >>
"Kevin Morris" <kevin@techfocusmedia.com> schrieb im Newsbeitrag 
news:1137096913.255199.239090@o13g2000cwo.googlegroups.com...
> I'm writing a feature article for FPGA Journal (www.fpgajournal.com)
> about FPGAs and the re-birth of the electronics hobbyist.  My theory is
> that electronics as a hobby went through a "dark age" period, maybe
> from the early/mid 1970s until recently becuase of the inaccessibility
> and cost of designing with state-of-the-art technology.  Radio Shack
> shifted their focus from 50-in-1 project kits and hobbyist parts to
> selling toys, cell-phones, and stereo equipment.
>
> Now, with the emergence of low-cost, high-capability FPGAs, development
> boards, and design software, I see a new age of hobbyist activity
> beginning (as often evidenced in this group).
>
> I'm looking for a few people that would be willing to express views on
> this topic for the article.
>
> I know, Austin will probably post a strong technical argument that
> Xilinx FPGAs are uniquely attractive to the hobbyist, somebody from
> Altera will send me a Cubic Cyclonium prototyping paperweight (they're
> very cool), and Actel and Lattice people will post just to remind us
> that they have low-cost kits too, but I'm primarily interested in some
> info from real, live, "working" hobbyists.
>
> Any takers?
>
I am actually not so hobbyist, but I have my fun some times


Spartan3E VQ100 on single sided toner transfer made PCB
http://xilant.com/content/view/35/2/

DIL24 (GAL like) Spartan3-100 based module works as
MMC card in card reader

http://xilant.com/content/view/33/55/

my FPGA protoboard pictures are lost unfortunatly

xilinx isnt actually the best for hobby because of the 3 power supplies 
required
sometimes you can get it with 2 power supplies (if VCCIO is 2.5)

so all other vendors have an small advantage here, with the true single 
supply
chips being the best, in generic it really looks like it may come to
DIY electronic rebirth again - if I can help here I would be glad -

there are so many thing any FPGA board can do because of
its reprogrammability

for true do it all yourself hobby bastler Lattice XP in TQ144
is possible the easiest to handle

so what info are you looking and what is it where you look
for takers ?

Actel has no low kits (no real low cost). for xilinx/lattice
kit prices start from 50USD 50EUR, for Altera has been same
all actel kits are 149USD+

the only interesting Actel thing is the Fusion starterkit and
that costs already 399EUR



-- 
Antti Lukats
http://www.xilant.com






Article: 94498
Subject: Re: FPGA Journal Article
From: Jim Granville <no.spam@designtools.co.nz>
Date: Fri, 13 Jan 2006 10:44:52 +1300
Links: << >>  << T >>  << A >>
Kevin Morris wrote:
> I'm writing a feature article for FPGA Journal (www.fpgajournal.com)
> about FPGAs and the re-birth of the electronics hobbyist.  My theory is
> that electronics as a hobby went through a "dark age" period, maybe
> from the early/mid 1970s until recently becuase of the inaccessibility
> and cost of designing with state-of-the-art technology.  Radio Shack
> shifted their focus from 50-in-1 project kits and hobbyist parts to
> selling toys, cell-phones, and stereo equipment.
> 
> Now, with the emergence of low-cost, high-capability FPGAs, development
> boards, and design software, I see a new age of hobbyist activity
> beginning (as often evidenced in this group).

There is also a parallel in the Microcontroller sector.
With most new devices having FLASH and OnChip debug, the level
of entry for capable in-system debug, has dropped.

SiLabs have a sub $10 USB ToolStick, Zilog had some sub $10
demos, and I think now have $39 Eval/Demo Boards.
Freescale have a new $50 promo USB system...

> 
> I'm looking for a few people that would be willing to express views on
> this topic for the article.

> I know, Austin will probably post a strong technical argument that
> Xilinx FPGAs are uniquely attractive to the hobbyist, somebody from
> Altera will send me a Cubic Cyclonium prototyping paperweight (they're
> very cool), and Actel and Lattice people will post just to remind us
> that they have low-cost kits too, but I'm primarily interested in some
> info from real, live, "working" hobbyists.

Lattice have the OpenSource Mico8, and their MachXO means you can get
a tiny, but working, SoftCPU in one low cost chip.

AS Assembler has added support for the Mico8, giving a second ASM tool flow.

> 
> Any takers?


<paste>
Hal Murray wrote:

> The Xilinx store still doesn't carry the small Coolrunner IIs.
> Digikey doesn't stock any of them.

Yes, alas, more signs of 'big company syndrome' from Xilinx :(

How hard can it have been to have ensured the newish '32A/64A'
were there, before they yanked the older ones.... ?
( and in the new packages too ?! )

With the Webstore as it is now, users might think any/all of
a) They do not want these in new designs
b) There is some supply problem, with smaller CPLDs
c) Xilinx is phasing out emphasis on smaller CPLDs
[Xilinx are now last in release of new CPLD devices..]

-jg




Article: 94499
Subject: Re: FPGA Journal Article
From: Brian Drummond <brian_drummond@btconnect.com>
Date: Thu, 12 Jan 2006 21:45:39 +0000 (UTC)
Links: << >>  << T >>  << A >>
On 12 Jan 2006 12:15:13 -0800, "Kevin Morris" <kevin@techfocusmedia.com>
wrote:

>I'm writing a feature article for FPGA Journal (www.fpgajournal.com)
>about FPGAs and the re-birth of the electronics hobbyist.  My theory is
>that electronics as a hobby went through a "dark age" period, maybe
>from the early/mid 1970s until recently becuase of the inaccessibility
>and cost of designing with state-of-the-art technology.  Radio Shack
>shifted their focus from 50-in-1 project kits and hobbyist parts to
>selling toys, cell-phones, and stereo equipment.

er, no, I wouldn't have said the late 70's or 80s were in any way a dark
age for the hobbyist...

admittedly around 1980 all a hobbyist had to play with was the Z80 or
6502, but at the time they WERE state of the art. It was probably the
last time a hobbyist could build a computer, modify or even write the
BIOS, and actually understand pretty much every detail of a machine
capable of running the leading OS and applications. 

>Now, with the emergence of low-cost, high-capability FPGAs, development
>boards, and design software, I see a new age of hobbyist activity
>beginning (as often evidenced in this group).

If anything, it's a return to those days, with Linux in the place of
CP/M, (though Linux is too big to _really_ understand), and with WebPack
in the place of that fat orange book (you know the one), 16-pin sockets,
and the wire wrap tool.

Pete A will probably maintain the fat book was actually bright red!

>I'm looking for a few people that would be willing to express views on
>this topic for the article.
> but I'm primarily interested in some
>info from real, live, "working" hobbyists.

Digital clock, 1978.

FM tuner, 1979.

Dictation type cassette recorder, hacked for hi-fi stereo headphone use,
in progress summer 1980. Yes, the summer the Walkman came out. Grrr...

Richard Russell Board (Z80, 32k later 64k RAM; a BBC OS (not BBC Micro!)
and later CPM 1982,3,4) An oddball (but good!) in the ZX80, ZX81 era.

Mahogany laptop (64180 based) ca 1987, but it was getting obsolete
faster than I could finish it... 

Vacuum tube amp restorations, various.

Some deaf microphones, ca 1995, until I gave up and used commercial
capsules. (The electronics and enclosures were my own though)

Don't know if these count.

...then working from home and non-electronic hobbies started taking
over... 

- Brian




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2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

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