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Hello, I don't have the specification of PCI e ( that doesn't help ! ) and I'm trying to figure out how the clock scheme works on PCI express. For me when using serial high speed links, the clock was included within the 8B/10B and hardware low layers stuffs. I did a design with aurora and MGT on fiber links, and no clock was transmitted as a signal, it was integrated on the data line. For me PCIe is the same thing but on LVDS. And I saw on a reference design that a LVDS clock was given the PCIe interface chip and send to the bus connector. So when I design a PCIe board, what is the clock scheme to implement ? Clock generation or not on the bus ?!! I'm missing something. Obviously..... Thanks for your help ! Stéphane.Article: 94526
Our design is a board with PCI/PCIe 4x interface. My question concern is on the PCI express bus connector side. Stéphane. "mk" <kal*@dspia.*comdelete> a écrit dans le message de news: l9pes1573ffm9nftbr05f9ccba2af2q7mu@4ax.com... > On Fri, 13 Jan 2006 09:05:23 +0100, "sjulhes" <t@aol.fr> wrote: > > >Hello, > > > >I don't have the specification of PCI e ( that doesn't help ! ) and I'm > >trying to figure out how the clock scheme works on PCI express. > > > >For me when using serial high speed links, the clock was included within the > >8B/10B and hardware low layers stuffs. > >I did a design with aurora and MGT on fiber links, and no clock was > >transmitted as a signal, it was integrated on the data line. > > > >For me PCIe is the same thing but on LVDS. > >And I saw on a reference design that a LVDS clock was given the PCIe > >interface chip and send to the bus connector. > > > >So when I design a PCIe board, what is the clock scheme to implement ? > >Clock generation or not on the bus ?!! > > At what level are you implementing PCIE ? Are you doing a controller > where your interface is to the PHY ? Even if then you need a parallel > interface to the PHY (most probably through PIPE) and the clock for > PIPE is generated by the PHY at a low speed. There is a no clock at > the wire for PCIE. The receive side is supposed to recover the clock > by looking at the 8b10b encoded data (and tolerate dropped/added bits > by using some extra codes added by the protocol). The PIPE level PHY > should isolate you from all clocking at 2.5 GHz speed. >Article: 94527
"sjulhes" <t@aol.fr> schrieb im Newsbeitrag news:43c75f44$0$19976$626a14ce@news.free.fr... > Hello, > > I don't have the specification of PCI e ( that doesn't help ! ) and I'm > trying to figure out how the clock scheme works on PCI express. > > For me when using serial high speed links, the clock was included within > the > 8B/10B and hardware low layers stuffs. > I did a design with aurora and MGT on fiber links, and no clock was > transmitted as a signal, it was integrated on the data line. > > For me PCIe is the same thing but on LVDS. > And I saw on a reference design that a LVDS clock was given the PCIe > interface chip and send to the bus connector. > > So when I design a PCIe board, what is the clock scheme to implement ? > Clock generation or not on the bus ?!! > > I'm missing something. Obviously..... > > Thanks for your help ! > > Stéphane. > > PCIe reference clock 125MHz may (but doesnt have to!) be transmitted in the PCIe connector however Virtex2Pro MGT do not guarantee safe locking from data only, so external PLL circtuit that delivers MGT clock (from ref clock) is required for Virtex PCIe solution. check out the materials from nital, you will see that PLL circuit in some of their data sheet for their PCIe boards -- Antti Lukats http://www.xilant.comArticle: 94528
On Fri, 13 Jan 2006 09:05:23 +0100, "sjulhes" <t@aol.fr> wrote: >Hello, > >I don't have the specification of PCI e ( that doesn't help ! ) and I'm >trying to figure out how the clock scheme works on PCI express. > >For me when using serial high speed links, the clock was included within the >8B/10B and hardware low layers stuffs. >I did a design with aurora and MGT on fiber links, and no clock was >transmitted as a signal, it was integrated on the data line. > >For me PCIe is the same thing but on LVDS. >And I saw on a reference design that a LVDS clock was given the PCIe >interface chip and send to the bus connector. > >So when I design a PCIe board, what is the clock scheme to implement ? >Clock generation or not on the bus ?!! At what level are you implementing PCIE ? Are you doing a controller where your interface is to the PHY ? Even if then you need a parallel interface to the PHY (most probably through PIPE) and the clock for PIPE is generated by the PHY at a low speed. There is a no clock at the wire for PCIE. The receive side is supposed to recover the clock by looking at the 8b10b encoded data (and tolerate dropped/added bits by using some extra codes added by the protocol). The PIPE level PHY should isolate you from all clocking at 2.5 GHz speed.Article: 94529
Kevin, I agree with you. (even if I think that the starter kit are still too expensive for people that want electronics as an hobby) I'm going to write some articles for an italian magazine (Fare Elettronica) about FPGA. This magazine is for people that like electronics as hobby. In my articles I'll talk about the Xilinxs FPGA and in 5 aticles I will introduce people to this technology. FrancescoArticle: 94530
Thanks for saving me a lot of time. Allthough putting it right is going to take lots more! Unfortunately the firmware has been formerly released by a third party in the US and I have to prepare it for volume manufacture in the far east and I work in the UK. I will go and check, but I think that all the "errors" were stuck at ones. Is the result that should be expected? Allthough you have saved me some considerable time could you tell me where the designer should have found this info. If it's very obvious then I will have a quiet word with him. If it's not in a very obvious place (and I have spent longer than I feel I should have looking) then perhaps you could have a quiet word with your technical authors. Regards ColinArticle: 94531
wuyi316904@gmail.com wrote: > Thank for ur suggests,Is there independent Impact for download and what > the Impact version u used? > Release version 4.2i Application version E.35 I don't recall exactly where it came from: possibly one of the Xilinx FAE's on this group can help?Article: 94532
Anyone have experience with designing band pass filters for ACTEL FPGAs? Tools, appnotes anything is of interest. I my project I have to make some DSP on 3 audio signals (100Hz-22Khz). Planing on using the new Fusion mixed-signal FPGA from ACTEL.Article: 94533
> No one really knows the long term effects of moving to RoHS. That's the bottom line. I think you can mix component types, but, even if you had RoHS-only, your statement holds. The whole RoHS thing is a disaster waiting to happen, simply because of the way it has been approached. But...what do I know? I've had conversations with people from various companies across markets who have told me that their whole R&D budget for a year would be consumed if they decided to re-design every product in their product line to meet RoHS. Most will discontinue some products and retool a few and simply make others not available to the EU. I think you are right, mass-market producers (cell phones, PC's, etc) probably got it together 'cause they are used to very short product cycles anyway. An associate of mine visited a phone manufacturer at the Consumer Electronics Show and asked them when they were going to fix a bug on one of their fairly new high end phones. The answer was to get the new model that just came out. To go back to the topic of the thread, the gravest concern is that of mid to long term reliability of RoHS or mix-technology assemblies. This whole mess could actually result in MORE electronic trash being produced until metalurgy/chemestry/whatever goes through the required process of "natural selection". ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian eCinema Systems, Inc. To send private email: x@y where x = "martineu" y = "pacbell.net"Article: 94534
Kevin I'll start by saying I represent manufacturer making low cost boards but I can pass offline some of the feedback we get from users of our products particularly our Raggedstone1 and low cost modules that we sell also. Generally I would say that the fact that FPGA boards like ours now cost less that it takes to fill my car with fuel so that the start-up cost is nearly inconsequential to most hobby engineers. Coupled to that you get free fully function tools from most silicon vendors, and that achieving timing in designs at frequencies below say 50MHz is now easy, the marriage of factors is allowing hobbyists to use the technology. Looking back to say 10 years ago most of these factors didn't exist or were very limited and the barrier to hobby use was hugh. I can be contacted through our support email or telephone number, available on our website, if you want a bit more feedback. John Adair Enterpoint Ltd. - Home of Raggedstone1. The Low Cost Spartan3 PCI Development Board. http://www.enterpoint.co.uk "Kevin Morris" <kevin@techfocusmedia.com> wrote in message news:1137096913.255199.239090@o13g2000cwo.googlegroups.com... > I'm writing a feature article for FPGA Journal (www.fpgajournal.com) > about FPGAs and the re-birth of the electronics hobbyist. My theory is > that electronics as a hobby went through a "dark age" period, maybe > from the early/mid 1970s until recently becuase of the inaccessibility > and cost of designing with state-of-the-art technology. Radio Shack > shifted their focus from 50-in-1 project kits and hobbyist parts to > selling toys, cell-phones, and stereo equipment. > > Now, with the emergence of low-cost, high-capability FPGAs, development > boards, and design software, I see a new age of hobbyist activity > beginning (as often evidenced in this group). > > I'm looking for a few people that would be willing to express views on > this topic for the article. > > I know, Austin will probably post a strong technical argument that > Xilinx FPGAs are uniquely attractive to the hobbyist, somebody from > Altera will send me a Cubic Cyclonium prototyping paperweight (they're > very cool), and Actel and Lattice people will post just to remind us > that they have low-cost kits too, but I'm primarily interested in some > info from real, live, "working" hobbyists. > > Any takers? >Article: 94535
Ycan create small delays on signals by passing the signal through a LUT configured to act as a buffer. Here it is in VHDL LUT_DELAY: LUT1 generic map( INIT => X"10") port map( O => signal_in_delayed, I0 => signal_in); <wuyi316904@gmail.com> wrote in message news:1137053886.979267.61360@g14g2000cwa.googlegroups.com... > Hi,in my project,i need some bufs to delay some signals,but after > synthesising,the code:#20 does't have any affects.Is there some way to > keep the delay?For example,some constraint for synthesis or other. >Article: 94536
Martin schrieb: >>No one really knows the long term effects of moving to RoHS. I am not so sure about this. There are people who are doing lead free for decades now. For example in cases where you can not tolerate the alpha particles emitted by the lead. Or in cases where your electronic is inside a strong magnetic field. (High Energy Physics) Kolja SulimmaArticle: 94537
"Peter Alfke" <peter@xilinx.com> wrote in message news:1137114655.967499.118700@g44g2000cwa.googlegroups.com... >I have struggled for decades to come up with enticing demo projects for > digital circuits, and I have made my rules: > It must be something that cannot be done with just a microprocessor. > That means it must be something fast. Audio, video, radio, robotics > come to mind. > Or, for FPGAs, it must be a platform that allows all sorts of > variations. Like the Swis Army knife of electronics. > Most likely it must be something that appeals to a limited number of > people. That way the toy industry has not yet made it available for $ > 9.99. (That was the death of some of my keyboard synthesizer projects > in the 'seventies.) > I think a secondary light-triggered (slave) flash unit would be very > useful for all those small digital cameras, but that does not need an > FPGA... :-( > Peter Alfke Why not an fpga synthesizer project ? Projects like that appeal to people. Things like the fpga4fun projects. Something like a music visualiser like the ones in winamp etc most micros aren't powerful enough for that. Or a software am radio. Use a fpga to replicate a couple of dollar tranny radio. Or some simple dsp projects like filters without using system generator or core generator. Pitch shifter, simple wah effect etc Update all the old analog type projects the hobby magazines have/had for fpga. One company could probably capture a lot of the hobbyist market if they produced a pdf magazine or quarterly with these sort of projects. As others have said provide the source code and maybe even an area to share projects. A bit like the Atmel applications journal when it started out. I'm still surprised non of the fpga companies have targeted the US board of education market like parallax has with the basic stamp. Use a s3e or s3 starter kit or dip module, with a "simple" soft-core that has a basic compiler for it that hides the internals. Simplify the schematics with like an icon based design environment like corechart http://www.elabtronics.com/products_cat_CoreChart.htm Could also easily target this at robotics as well. Get them using your products from 12 years onwards. Could stimulate designs like this by having a circuit cellar design contest and targeting it at the hobby market. AlexArticle: 94538
Kolja Sulimma wrote: > For example in cases where you can not tolerate the > alpha particles emitted by the lead. In its naturally abundant form, lead is stable. It does not emit alpha (or any other) particles... > Or in cases where your electronic is inside a strong magnetic field. > (High Energy Physics) Can you explain how and why lead behaves differently in strong magnetic fields than the ROHS materials? This whole ROHS thing is such an idiotic thing to do that it is really frightening how easy it was to drag the whole industry into it... "Only two things are infinite - the universe and human stupidity, and I'm not sure about the former." A. Einstein Dimiter ------------------------------------------------------ Dimiter Popoff Transgalactic Instruments http://www.tgi-sci.com ------------------------------------------------------Article: 94539
On a sunny day (12 Jan 2006 17:10:56 -0800) it happened "Peter Alfke" <peter@xilinx.com> wrote in <1137114655.967499.118700@g44g2000cwa.googlegroups.com>: >I have struggled for decades to come up with enticing demo projects for >digital circuits, and I have made my rules: >It must be something that cannot be done with just a microprocessor. >That means it must be something fast. Audio, video, radio, robotics >come to mind. >Or, for FPGAs, it must be a platform that allows all sorts of >variations. Like the Swis Army knife of electronics. >Most likely it must be something that appeals to a limited number of >people. That way the toy industry has not yet made it available for $ >9.99. (That was the death of some of my keyboard synthesizer projects >in the 'seventies.) >I think a secondary light-triggered (slave) flash unit would be very >useful for all those small digital cameras, but that does not need an >FPGA... :-( >Peter Alfke > OK I wanted to shut up on this, no I am no hobbyist, but I once was one. Still I tinker with stuff on the side. No running light etc.. is the interest of the 'current tinkerer'. Yes, high speed video. The current tinkerer (in me) needs an FPGA board with H264 decoder capable of doing H264 main profile, something like this: Stream #0.0, 50.00 fps(r): Video: h264, yuv420p, 1920x1088 The current tinkerer knows there is no real H264 acceleration graphics card with Linux driver, the current tinkerer also want to decode any encrypted.... The current tinkerer KNOWS systems change every few years, and wants to keep using the same hardware as long as possible, the current tinkerer wants VGA DVI and perhaps HDCP, and the current tinkerer wants Ethernet RJ45 100 MB/s to connect to the board.. and Linux soft like WebPack-8.1 to program it. The current tinkerer knows he needs a dual core Pentium 4 3.2 to pull it all of in software (better then that, even dual Opteron does not hack it actually), so here comes the price advantage of the FPGA solution. But only for so long, until the first H264 chips or accelerated graphics cards are on the market. So, throw in the H262 codec IP (or just the decoder) with the required soft and 'demo board', make sure it has that VGA (without earth noise problems), and RJ45 connector... and put it in the web shop. Hey I have it all working in C, have the source... developing a H264 decoder is some job.... maybe one of those C to HDL compilers... dunno. So the real hobbyist I was in the sixties build his own vidicon camera and TVs and what not... do not underestimate the real hobbyist ;-) And that kind of person will go for FPGA. The E Hobbyist was never 'dead', look at all the micro boards, then PICs, but indeed these demo FPGA boards are much more then that, they are universal building blocks. Just make sure it has the right IO.Article: 94540
"dp" <dp@tgi-sci.com> wrote in message news:1137154709.867377.108660@g49g2000cwa.googlegroups.com... > Kolja Sulimma wrote: >> For example in cases where you can not tolerate the >> alpha particles emitted by the lead. > > In its naturally abundant form, lead is stable. It does not emit > alpha (or any other) particles... > Yeah, but only 1.4% of naturally occuring lead is not radiogenic. The rest comes from decay of thorium, actinium and uranium. Some of those radioactive elements are likely to mixed in with your lead. Cheers, Syms. http://en.wikipedia.org/wiki/Lead#Isotopes http://periodic.lanl.gov/elements/82.htmlArticle: 94541
"Antti Lukats" <antti@openchip.org> wrote in message news:dq7m71$s50$03$1@news.t-online.com... > "Anonymous" <someone@microsoft.com> schrieb im Newsbeitrag > news:rRFxf.9618$Kp.656@southeast.rr.com... > > This is a commercial project. I was under the impression Xilinx provides a > > working Linux build for the V4? I don't expect to be doing much Linux > > hacking per se, maybe just a custom device driver to interface to my DSP > > circuit/code. > > > > "John Williams" <jwilliams@itee.uq.edu.au> wrote in message > > news:newscache$6670ti$oeg$1@lbox.itee.uq.edu.au... > >> Anonymous wrote: > >> > Thanks. But that brings up another question: Is it better to go with > > ucLinux > >> > or use the PPC version of linux? I suspect the latter if I have the FX > > part, > >> > right? > >> > >> Being the maintainer of the MicroBlaze uClinux port, and offering > >> commercial services for the platform, I'm obviously biased :), however I > >> think the decision is not as automatic as you suggest. > >> > >> Unless you are prepared to shell out a reasonable number of dollars to > >> MontaVista, developing for uClinux with the free tools is a lot easier > >> than PPC. There are some guides out there on DIY Linux for Xilinx PPC, > >> but they aren't for the faint-hearted. > >> > >> The board port/bringup procedure for uClinux on MicroBlaze is also a lot > >> faster than PPC Linux, with the free auto-config tools. > >> > >> It depends on what you are trying to do, and how much you value your > >> time. > >> > >> Is this a hobbyist, study or commercial project? > >> > >> Regards, > >> > >> John > >> > > I stand here with John - the Xilinx PPC linux setup is not for > faint-hearted. > > That is because of Xilinx politics - everybody who is not MontaVista > gets just ignored - DENX was doing lots of work towards PPC linux > support but as Xilinx did not talk to them so Denx dropped any further > work on Xilinx support for PPC linux. Thats too bad. > > Setting up a new MicroBlaze uCLinux systems is just a piece of cake > So if you need some DSP code setup uClinux/Microblaze, connect > your DSP functions to FSL links and you are all set > > -- > Antti Lukats > http://www.xilant.com > > That's interesting. So if I have an FX12 part, for example, your suggestion is that I run uclinux in a soft core and implement my DSP code in the PPC core? This is the opposite of what I had expected. What do I give up for ucLinux versus PPC Linux? Speed? Device driver support? Also, what's your suggestion for unit control? I imagined a webserver interfaced to some type of CGI. Maybe perl scripts or php? Thanks, ClarkArticle: 94542
Symon wrote: > Yeah, but only 1.4% of naturally occuring lead is not radiogenic. Radiogenic and stable - non-radioactive. > The rest comes from decay of thorium, actinium and uranium. This is what radiogenic means; the result (in this case) being stable isotopes. > Some of those radioactive elements are likely to mixed in with your lead. Ummm, what? Any figures? Did you ever try to add up the percentages of Pb, Sn and other listed materials at the label of some soldering wire? Such nonsense - like the entire multi-billion euro ROHS exercise (we have yet to see into whose pockets the billions will flow). Dimiter (over and out...) ------------------------------------------------------ Dimiter Popoff Transgalactic Instruments http://www.tgi-sci.com ------------------------------------------------------Article: 94543
Antti Lukats wrote: > "sjulhes" <t@aol.fr> schrieb im Newsbeitrag > news:43c75f44$0$19976$626a14ce@news.free.fr... > > Hello, > > > > I don't have the specification of PCI e ( that doesn't help ! ) and I'm > > trying to figure out how the clock scheme works on PCI express. > > Do yourself a favor and buy a copy of the spec. In the long run it's cheaper than redesigning due to mis-information. > > For me when using serial high speed links, the clock was included within > > the > > 8B/10B and hardware low layers stuffs. > > I did a design with aurora and MGT on fiber links, and no clock was > > transmitted as a signal, it was integrated on the data line. > > > > For me PCIe is the same thing but on LVDS. > > And I saw on a reference design that a LVDS clock was given the PCIe > > interface chip and send to the bus connector. > > > > So when I design a PCIe board, what is the clock scheme to implement ? > > Clock generation or not on the bus ?!! > > > > I'm missing something. Obviously..... > > > > Thanks for your help ! > > > > St=E9phane. > > > > > PCIe reference clock 125MHz may (but doesnt have to!) be transmitted in t= he > PCIe connector My copy of the PCIe spec says the nominal frequency is 100MHz +/-300ppm. It also clearly states that the reference clock does not need to be used by the plug- in card, but I don't see anywhere that the system doesn't have to provide it. The point of delivering a reference clock was to reduce the depth of FIFO's dealing with differences in clock generation between ends of a link. The spec says the plug-in card should maintain its own reference clock within +/-600ppm of the system reference if the system reference isn't used (not too hard with a crystal oscillator, but still easier to use the system reference if you can). > > however Virtex2Pro MGT do not guarantee safe locking from data only, so > external PLL circtuit > that delivers MGT clock (from ref clock) is required for Virtex PCIe > solution. > > check out the materials from nital, you will see that PLL circuit in some= of > their data sheet for > their PCIe boards >=20 > --=20 > Antti Lukats > http://www.xilant.comArticle: 94544
Alex We are half way there at the moment and a lot more is coming to fill in the gaps.So wait and see. John Adair Enterpoint Ltd. - Home of Raggedstone1. The Low Cost Spartan-3 Development Board. http://www.enterpoint.co.uk "Alex Gibson" <news@alxx.org> wrote in message news:42pjalF1isg56U1@individual.net... > > "Peter Alfke" <peter@xilinx.com> wrote in message > news:1137114655.967499.118700@g44g2000cwa.googlegroups.com... >>I have struggled for decades to come up with enticing demo projects for >> digital circuits, and I have made my rules: >> It must be something that cannot be done with just a microprocessor. >> That means it must be something fast. Audio, video, radio, robotics >> come to mind. >> Or, for FPGAs, it must be a platform that allows all sorts of >> variations. Like the Swis Army knife of electronics. >> Most likely it must be something that appeals to a limited number of >> people. That way the toy industry has not yet made it available for $ >> 9.99. (That was the death of some of my keyboard synthesizer projects >> in the 'seventies.) >> I think a secondary light-triggered (slave) flash unit would be very >> useful for all those small digital cameras, but that does not need an >> FPGA... :-( >> Peter Alfke > > Why not an fpga synthesizer project ? > > Projects like that appeal to people. > > Things like the fpga4fun projects. > > Something like a music visualiser like the ones in winamp etc > most micros aren't powerful enough for that. > > Or a software am radio. > Use a fpga to replicate a couple of dollar tranny radio. > > Or some simple dsp projects like filters without using system > generator or core generator. > Pitch shifter, simple wah effect etc > > Update all the old analog type projects the hobby magazines have/had for > fpga. > > One company could probably capture a lot of the hobbyist market if they > produced a pdf magazine or quarterly with these sort of projects. > As others have said provide the source code and maybe even an area to > share projects. > > A bit like the Atmel applications journal when it started out. > > I'm still surprised non of the fpga companies have targeted the > US board of education market like parallax has with the basic stamp. > > Use a s3e or s3 starter kit or dip module, with a "simple" soft-core that > has a basic compiler for it > that hides the internals. > Simplify the schematics with like an icon based design environment like > corechart > http://www.elabtronics.com/products_cat_CoreChart.htm > > Could also easily target this at robotics as well. > > Get them using your products from 12 years onwards. > > Could stimulate designs like this by having a circuit cellar > design contest and targeting it at the hobby market. > > Alex >Article: 94545
Gabor wrote: [snip] > My copy of the PCIe spec says the nominal frequency is 100MHz > +/-300ppm. It > also clearly states that the reference clock does not need to be used > by the plug- > in card, but I don't see anywhere that the system doesn't have to > provide it. "REFCLK-/REFCLK+ (required): low voltage differential signals." - PCI Express Card Electromechanical Specification, Rev. 1.1, chapter 2, "Auxiliary signals"Article: 94546
Dimiter, I'll try again. ;-) Production of Solder and Flux with Low Radioactivity http://hep1.snu.ac.kr/misc/nim1997.ps Quote:- "The lead in solder typically contains trace amounts of U238, Th 232 and K40." I agree the RoHS is nonsense. However, Kolja is correct that putting lead in solder makes it slightly radioactive. Not because of the lead; because of the contaminants. The contaminants are present as most lead is radiogenic. Cheers, Syms. p.s. Here's another link! http://www.puretechnologies.com/category_s/17.htmArticle: 94547
"Gabor" <gabor@alacron.com> schrieb im Newsbeitrag news:1137162950.844821.141000@o13g2000cwo.googlegroups.com... > > Gabor wrote: > [snip] >> My copy of the PCIe spec says the nominal frequency is 100MHz >> +/-300ppm. It >> also clearly states that the reference clock does not need to be used >> by the plug- >> in card, but I don't see anywhere that the system doesn't have to >> provide it. > > "REFCLK-/REFCLK+ (required): low voltage differential signals." > > - PCI Express Card Electromechanical Specification, Rev. 1.1, > chapter 2, "Auxiliary signals" > Hi Gabor, I hope you replied to the OP and not to my comments, I do know the specs. V2Pro MGT have CDR hard lock region +150 -110 ppm, what is not sufficent to cover the +-300 ppm spec requirement of PCIe, those if V2PRo MGT are used and external PLL solution is required. so that is what I was referring to V4MGT have extended CDR lock region that covers the +-300 ppm PCIe spec requirement -- Antti Lukats http://www.xilant.comArticle: 94548
In version 6.1 of the XIlinx tools, I was able to configure the s/w to use an external editor (in my case, gvim) to view reports. So, if I clicked on the 'Pad Report' icon, it would open a new gvim window with the report. In 8.1, this no longer seems to work. I've changed the preferences, and if I click on a module name, I get a gvim window. If I click on a report, 8.1 uses the internal viewer. Anyone else seeing this? John ProvidenzaArticle: 94549
can you give me a verilog code,thank u!
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