Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 102700

Article: 102700
Subject: Re: Virtex4 FX12 dynamic clock divider
From: "Guru" <ales.gorkic@email.si>
Date: 19 May 2006 02:48:57 -0700
Links: << >>  << T >>  << A >>
Thanks Erik,

I did my homework:

DDFS at 300MHz using DDR primitive has 1.67ns of jitter.
The DDFS problem are high frequencies, where 1.67ns of resolution
results in 66.6 to 60 increment (15 to 16.6ns). This is the are where I
need the finest resolution.
Another problem is building from a scratch - it takes lots of time.

I will use DCM_ADV solution with dynamic M/D. With one DCM I will
produce 66.66MHz (100*4/6) which will be used as an input clock of
DCM_ADV. To simplify the design I will lock the divider D to 32 (input
31) and change only the multiplier value from 12 to 32 (25 to 66.6
MHz). In this way I get 2.083MHz resolution (which I think is enough)
in the whole range and only 0.5ns of jitter (according to Xilinx
LogiCore calculation).
>From my opinion this the best solution for the purpose.

Thank you all,

Guru


Article: 102701
Subject: Re: Virtex 5 announced and sampling: apologia for FX woes on V4
From: "Tim" <tim@rockylogiccom.noooospam.com>
Date: Fri, 19 May 2006 10:49:44 +0100
Links: << >>  << T >>  << A >>

Antti wrote:

> hm to my understanding the V4 MGT are stripped down from original spec
> (10G) to meat the serdes in Stratix-IIGX ? So where do the V4 serdes
> beat SII-GX ? Perhaps they do, but for me it's not so obvious (not
> since the virtex 10G rocketio is "taken out" from V2Pro-X and V4).

I've missed the twists and turns of the SERDES/MGT saga.

I would be grateful if someone could briefly summarise what was promised in 
the various product generations and what was (eventually) provided. 



Article: 102702
Subject: Use USB ports on ML401
From: max.giacometti@libero.it
Date: 19 May 2006 02:55:46 -0700
Links: << >>  << T >>  << A >>
Hi everybody!
I would like to use the USB host and peripheral ports on my ML401
development board but I don't know what to do.

Can you help me?

Thanks,

Max

PS The board has a Virtex 4 LX Fpga, a Cypress CY7C67300 embedded USB
host controller.


Article: 102703
Subject: Re: Virtex 5 announced and sampling: apologia for FX woes on V4
From: "Antti" <Antti.Lukats@xilant.com>
Date: 19 May 2006 02:57:32 -0700
Links: << >>  << T >>  << A >>
WAS
===================================
V2Pro-X (highest speed grade only!) - 10GB/s
V4FX - 10GB/s

REALITY
===================================
V2Pro-X highes speed grade - not available any more
V4 spec reduced to 6.x GB/s
V5 spec also 6.x GB/s

that how I understand the "saga"

Antti


Article: 102704
Subject: Re: Spartan 3 Readback
From: "jvdh" <johannes.vanderhorst@gmail.com>
Date: 19 May 2006 02:58:44 -0700
Links: << >>  << T >>  << A >>
Antti:
That is scary, to say the least...

I found the errata stating that all parts for GQ fabrication process
and date code prior to 0532 do not supprt readback of any nature
(SelectMap and JTAG).

Now I'm just trying to decypher my part number...


Article: 102705
Subject: Re: Spartan 3 Readback
From: "Antti" <Antti.Lukats@xilant.com>
Date: 19 May 2006 03:10:39 -0700
Links: << >>  << T >>  << A >>
I was scared too, a while ago.
the errata looked like the issue is not going to be fixed at all, but
ASFAIK Xilinx is committed to eventually fix the S3 readback on all
production silicon from the new wafer/fab

antti


Article: 102706
Subject: Re: Output gain adjuster of digital filters
From: "Rune Allnor" <allnor@tele.ntnu.no>
Date: 19 May 2006 03:19:50 -0700
Links: << >>  << T >>  << A >>

Roger Bourne wrote:
> Hello all,
>
> I recently learned/heard  that when implementing a IIR digital filter
> of direct form I, the gain has to be finely adjusted with an
> additionnal module on the output. Otherwise, the 0dB level will not be
> perfectly reached in your passband (filter is low pass) and e.g.
> consequently a digital value that is suppose to be 40000.0000 will be
> 4000.0001.
> Essentially, I imagine this output module to be a multiplier of
> 1.0000000XXXX or 0.99999XXX

Seems to be tough demands. You are playing with deviations in
the 7th-9th significant digit, which is on the order of the numerical
accuracy of single precision floating-point numbers.

> I was led to believe this problem does not arise with digital filter
> implementations of direct form II.
>
> Is this true ?

Assuming you use single precision floats: No, this is not true.
Numerical inaccuracies on this scale occur, no matter what
filter structure you use.

> Looking over the flow diagrams of the 2 type of filters, I do not
> understand why one form would require a gain adjustement and the other
> would not.

One difference between type i and type 2 filters, is that one is more
robust with respect to numerical noise than the other. However, I find
it hard to believe that a gain adjustement is used in order to
correct for deviations on the scale indicated above.

It may be that the magnitudes of internal variables are different, so
that the gain needs to be adjusted in order to prevent overflow
in fixed-point arithmetics implementations.

Rune


Article: 102707
Subject: Re: DCM and Clock
From: "Piotr Wyderski" <wyderskiREMOVE@ii.uni.wroc.pl>
Date: Fri, 19 May 2006 12:29:55 +0200
Links: << >>  << T >>  << A >>
Peter Alfke wrote:

> Be careful with multiple clock domains. Any domain crossing is fraught
> with danger.

How about the output x and 2x of a DCM? Are they synchronous
enough to make resource timesharing without fancy synchronization
bridges? How should I express that in VHDL? Say:

    input A, B
    output A', B'

     A' := do_something(A) on every even clk2x pulse
      B' := do_something(B) on every odd clk2x pulse        

    Best regards
    Piotr Wyderski

Article: 102708
Subject: Re: EDK OPB DDR2 IP Core, looking for tested example
From: "Antti" <Antti.Lukats@xilant.com>
Date: 19 May 2006 03:36:12 -0700
Links: << >>  << T >>  << A >>
unfortunatly I managed to get the MCH_OPB_DDR2 ip core working myself
:(
there is no reward budget for me :(

so for anyone intererested the OPB_MCH_DDR2 IP core just works, there
is one minor bug
http://bugs.xilant.com/view.php?id=28
but there workaround is to implement the invisible in GUI wiring in MHS
manually

Antti


Article: 102709
Subject: Re: generate a square signal with a 3.8 ns "plate"
From: Kolja Sulimma <news@sulimma.de>
Date: Fri, 19 May 2006 12:38:12 +0200
Links: << >>  << T >>  << A >>
Scope schrieb:
> Hi,
> 
> I want to generate this kind of signal with my spartan 3 XCS200 :
> 
> http://www.abcelectronique.com/forum/attachment.php?attachmentid=4490
> 
> I am using the DCM to multiply my oscillator ( 50Mhz ) by 2 ; but, I don't
> succeed to have this "3.8 ns plate" for each level. I have it only for high
> logic level. How can I do ???

Are you sure that you do not succeed?
You need more than 1GHz of Scope and probe bandwidth to reliably measure
signal slopes in the order of 1ns.
(As the frequency is fixed, the plate width is defined by the slope of
the signal and the duty cycle)

For example with a 150MHz scope you will see a sine wave, no matter what
waveform the FPGA generates.

Kolja Sulimma

Article: 102710
Subject: Re: Use USB ports on ML401
From: "Antti" <Antti.Lukats@xilant.com>
Date: 19 May 2006 03:53:32 -0700
Links: << >>  << T >>  << A >>
try reading the manuals for the CY7C67300, it may help.

Antti


Article: 102711
Subject: Re: ADC implementation on FPGA ?
From: Rene Tschaggelar <none@none.net>
Date: Fri, 19 May 2006 13:23:49 +0200
Links: << >>  << T >>  << A >>
Scope wrote:

>>What's the speed ..?
> 
> up to 100 Mhz.
> 
>>Voltage levels ..?
> 
> analog input signal is between -1V and 1V
> 
>>Cost ..?
> 
> cost is not a problem
> 
>>Complexity ..?
> 
> What do you want to say with the term "complexity" ?
> 
> I need to convert it to an 8 bits format.

About the fastest ADC you can make from digital
logic is an R-2R network ladder successive
approximation ADC. You first generate an analog
voltage with the the R-2R network driven my MOS
outputs. 16 bits are beyond .. I'd guess about 10
bits to be feasible. The DAC voltage would of
cource be within the output voltage range. Then
you have an external comparator telling whether
the value is too low or too high. 100MSamples
are too fast too. You cannot work with high
impedance stuff there anymore. The R-2R network
with 100 Ohms each ? That is a lot of current.

Rene
-- 
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net

Article: 102712
Subject: Re: Virtex 5 announced and sampling: apologia for FX woes on V4
From: David Brown <david@westcontrol.removethisbit.com>
Date: 19 May 2006 13:30:33 +0200
Links: << >>  << T >>  << A >>
Paul Leventis wrote:
> Hi Antti,
> 
> No comment means that we could be coming out any time.
> 
> Max II is pretty awesome in many ways (performance, cost per logic
> function, etc.).  There are some applications where non-volatility and
> RAM would be handy, and these aren't addressed by Max II.  We've got
> that feedback and will factor it into future architecture decisions --
> but its always a trade-off of the cost (die-size impact) of adding
> additional features vs. the size of the market that those additional
> features will open to us.
> 

A couple of RAM banks and a PLL would make all the difference to the MaxII.

I'd also add 5V tolerant inputs, and smaller/cheaper versions to a wish 
list, if you making a collection.

mvh.,

David



> Regards,
> 
> - Paul
> 

Article: 102713
Subject: Re: SystemACE bootloader for PowerPC on Virtex4 FX
From: "Jon Beniston" <jon@beniston.com>
Date: 19 May 2006 04:32:48 -0700
Links: << >>  << T >>  << A >>
Hi Peter,

Thanks, that is exactly what I needed.

I guess this is all obvious to anyone who got up an running with a
ML40x board, but I'm starting from scratch :(

Thanks a lot,
Jon


Article: 102714
Subject: Re: V5 and carry lookahead
From: fpga_toys@yahoo.com
Date: 19 May 2006 04:37:23 -0700
Links: << >>  << T >>  << A >>

Ben Jones wrote:
> Yes indeed. Obviously the new LUT6 architecture changes the playing field
> somewhat when it comes to arithmetic. There has been plenty of work done on
> identifying the optimal mappings for basic arithmetic functions so the tools
> can do a Good Job. (Nominally. :))

We've already been looking at technology specific mapping for FpgaC,
and one of the things noticed was that LUT4s didn't pack well with
arithmetics, and were already looking at F5/F6 to improve that problem.
Building to LUT6s is certainly a better fit for the netlists we
generate, so my response is YIPPIE :)

Also the 64x1 LUT RAMs are also a blessing, as it makes it far easier
to support many applications with short arrays that size ... where the
16 and 32 deep arrays are frequently not enough.  Is there an expander
function in the slice fabric to cascade these, like the 32x1 in the V2
and V2Pros?  Dual port fabric?

Any chance I can get some better docs and suggested arithmetic
implementations so we can target these devices with the new technology
mapper?

> The improvements in the carry chain speed are substantial. Although there's
> still a noticable hit when getting on and off them, the raw propagation
> speed is a real step up from previous generations. The fabric speed is
> really catching up to the embedded IP blocks now...

I'm interested in performance for 32bit and 64 bit arithmetics as Long
and Long Long variables, will it be the case that the carry logic is
slower than look ahead functions as with the current carry chains?


Article: 102715
Subject: Re: generate a square signal with a 3.8 ns
From: "Scope" <romaingoron@hotmail.fr>
Date: Fri, 19 May 2006 06:46:19 -0500
Links: << >>  << T >>  << A >>

>You need more than 1GHz of Scope and probe bandwidth to reliably measure
>signal slopes in the order of 1ns.

My Scope is a Tektronix TDS 3054 500Mhz ( 5 GS/s ). Do you think it is not
enough ? Is it possible that I can't see the real signal ? 

( However, Shannon's rule about sampling is respected )

Article: 102716
Subject: Re: Ethernet & ML401
From: "Marco T." <marc@blabla.com>
Date: Fri, 19 May 2006 13:50:53 +0200
Links: << >>  << T >>  << A >>

<max.giacometti@libero.it> wrote in message 
news:1148027312.645907.298790@i40g2000cwc.googlegroups.com...
> The board I'd like to use (ML401) is equipped with a Virtex4 LX (not
> FX) FPGA; The AppNote807 is about V4FX, that has an embedded TEMAC
> core, so it's not usefull for me.
>
> Thanks anyway,
>
> MAx
>

The only way is buying a ethernet core, emac or emac lite.

Marco 



Article: 102717
Subject: Re: Use USB ports on ML401
From: "Marco T." <marc@blabla.com>
Date: Fri, 19 May 2006 13:52:17 +0200
Links: << >>  << T >>  << A >>

<max.giacometti@libero.it> wrote in message 
news:1148032546.307102.321380@i39g2000cwa.googlegroups.com...
> Hi everybody!
> I would like to use the USB host and peripheral ports on my ML401
> development board but I don't know what to do.
>
> Can you help me?
>
> Thanks,
>
> Max
>
> PS The board has a Virtex 4 LX Fpga, a Cypress CY7C67300 embedded USB
> host controller.
>

There are some examples into xilinx site:

http://www.xilinx.com/products/boards/ml401/reference_designs.htm

Marco 



Article: 102718
Subject: Re: ADC implementation on FPGA ?
From: Falk Brunner <Falk.Brunner@gmx.de>
Date: Fri, 19 May 2006 13:57:26 +0200
Links: << >>  << T >>  << A >>
Rene Tschaggelar schrieb:

> About the fastest ADC you can make from digital
> logic is an R-2R network ladder successive
> approximation ADC. You first generate an analog
> voltage with the the R-2R network driven my MOS
> outputs. 16 bits are beyond .. I'd guess about 10
> bits to be feasible. The DAC voltage would of
> cource be within the output voltage range. Then
> you have an external comparator telling whether
> the value is too low or too high. 100MSamples
> are too fast too. You cannot work with high
> impedance stuff there anymore. The R-2R network
> with 100 Ohms each ? That is a lot of current.

With all necessary respect to tweaks, tricks and clever design, but 
there ARE reasons why certain functions like 100 MSps ADCs are discrete 
components. I dont think that ther are pure rip-off.
So if you want a 100 Msps ADC, buy one and connect it to the FPGA. Done.

Regards
Falk

P.S. If all you got is a hammer, everything looks like a nail.

Article: 102719
Subject: Re: generate a square signal with a 3.8 ns
From: Falk Brunner <Falk.Brunner@gmx.de>
Date: Fri, 19 May 2006 13:59:59 +0200
Links: << >>  << T >>  << A >>
Scope schrieb:
>>You need more than 1GHz of Scope and probe bandwidth to reliably measure
>>signal slopes in the order of 1ns.
> 
> 
> My Scope is a Tektronix TDS 3054 500Mhz ( 5 GS/s ). Do you think it is not
> enough ? Is it possible that I can't see the real signal ? 

And what kind of probe? How attatched?

http://www.signalintegrity.com/Pubs/straight/probes.htm

Regards
Falk

Article: 102720
Subject: Re: Spartan 3e sample: pack power control with M(1)?
From: "rickman" <spamgoeshere4@yahoo.com>
Date: 19 May 2006 05:25:42 -0700
Links: << >>  << T >>  << A >>
radarman wrote:
> Guys/Gals,
> I was lucky enough to score a Digilent Spartan 3e sample pack board.
> This board is interesting in that it can only (generally) boot from
> JTAG or NOR FLASH (BPI). It also is interesting because it has a
> push-button power switch, instead of a normal switch or jumper.
>
> On an unrelated note, I modded my board by routing four unused inputs
> and CCLK to the unused 5 pins on the 40-pin connector. At first, I
> thougth I could use CCLK to drive the pushbutton, but the datasheet
> indicates that a clock is present during configuration for BPI mode.
> That would most assuredly cause problems for the LTC 2950 power control
> chip.
>
> So, I started looking around on the board, and noticed that the
> configuration mode pins were fairly clear, and become GPIO (except for
> M2) after configuration. I also noticed that both BPI UP/DOWN and JTAG
> require M1 to be high, or unconnected (since the pins have internal
> pull-ups).
>
> I figure it should be a cince to run M1 to the pushbutton - since the
> pullup will keep the pin high during configuration. After
> configuration, the design would be able to turn its own power off.
> After configuration, the design could turn itself off by driving the
> line low.
>
> Next, with a bit of careful design, and use of tri-states, it should be
> possible to emulate an open-collector output, and run the M1 pin
> offboard to allow the power to be controlled by both the onboard
> Spartan FPGA and offboard logic on a remote board. This would
> essentially entail running a cable between the M1 jumper position and
> the remote board.
>
> The first problem with this idea is possible contention between the
> FPGA and the remote logic. This is solveable by bringing up the
> external board first and having it briefly drive the signal low to
> begin the power up sequence on the sample back board, then tri-state
> its output. To make sure the signal is solidly high - and because
> during operation, both will be tri-stated, an external pull-up is added
> on the Spartan board's Vcc.
>
> Once configuration of the Spartan is complete, both devices switch
> between low and tri-state to control power. The remote board can sense
> when the Spartan board is powered by looking at the I/O pin, allowing
> status to be read dynamically, rather than stored in a FF.
>
> This should work, as it will take several hundreds of nanoseconds, or
> even microseconds, for the power supplies to stabilize enough that the
> Spartan 3E can begin configuration. So long as the control signal is
> brief enough trigger the LTC 2950, but not so long as to confuse the
> Spartan 3E (since we are manipulating a mode control pin), I don't see
> why this shouldn't work.
>
> Another problem would be that the remote board would, during it's own
> configuration, pull-up the GPIO line to its own Vccio - which would
> drive M1 while the Spartan is unpowered, causing latchup. I think that
> a diode circuit could be used to prevent this, but I'm still not sure
> how to wire it.
>
> Is this a doable circuit, or am I risking damage to the Spartan 3e
> board doing this? What would be a good way to handle the potential
> latch-up problem, or is there one?

I'm no expert on the Spartan 3e parts, but I would not expect any
damage if you use a fairly weak pullup, say 10 kohms.  But I see
another issue with the push button.  From your discription, it would
seem to me that the push button connects the *input* voltage to the
LTC3590 input to turn on power.  Isn't that voltage higher than the I/O
voltage that you will be using with the Spartan?  On the S3 parts, the
M1 signal is only 2.5 volts.  How will you prevent damage from this
higher voltage from the input of the regulator?


Article: 102721
Subject: Re: generate a square signal with a 3.8 ns
From: "Scope" <romaingoron@hotmail.fr>
Date: Fri, 19 May 2006 07:35:15 -0500
Links: << >>  << T >>  << A >>

>> My Scope is a Tektronix TDS 3054 500Mhz ( 5 GS/s )

>And what kind of probe? How attatched?

My probe is a Tektronix P6139A Voltage probe 500 MHz 8.0 pF 10 Mohms 10x





Article: 102722
Subject: Xilinx-ise, invert input?
From: pbdelete@spamnuke.ludd.luthdelete.se.invalid
Date: 19 May 2006 12:38:45 GMT
Links: << >>  << T >>  << A >>
How does one modify say a 'fdcp' block/object such that PRE & CLR
is inverted..?  without resorting to adding external inverters.



Article: 102723
Subject: Re: Processing DVI signals with an FPGA
From: pbdelete@spamnuke.ludd.luthdelete.se.invalid
Date: 19 May 2006 12:42:22 GMT
Links: << >>  << T >>  << A >>
patches11@gmail.com wrote:
>A friend and I have come up with some interesting ideas that involve
>messing around with DVI interfaces, and we'd like to physically
>implement them. Neither of us has a whole lot of knowledge in the way
>of FPGAs, just that they're faster for low-level tasks than a
>firmware-based controller would be.

You could try a quick hack I have been thinking on. Configure two ports per
tmds channel and use them to send dvi data. Would be interesting to see if
it works..


Article: 102724
Subject: Re: Xilinx-ise, invert input?
From: "Antti" <Antti.Lukats@xilant.com>
Date: 19 May 2006 05:46:41 -0700
Links: << >>  << T >>  << A >>
noway, its not Altera SW!




Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search