Messages from 102825

Article: 102825
Subject: Re: How simple can FPGA design be? (Mission Possible 2006)
From: "Nial Stewart" <nial@nialstewartdevelopments.co.uk>
Date: Sun, 21 May 2006 22:01:49 +0100
Links: << >> << T >> << A >>

> Antti Lukats
> from work on Sunday 21:50 local time


Lightweight, it's _22:01_ here, and I'm still in work :-(



Nial (about to go home).

Article: 102826
Subject: Forgot to say....
From: "Nial Stewart" <nial@nialstewartdevelopments.co.uk>
Date: Sun, 21 May 2006 22:04:37 +0100
Links: << >> << T >> << A >>

I see you don't know how to work the iron Antti.

Good job!


Nial

Article: 102827
Subject: Re: Superscalar Out-of-Order Processor on an FPGA
From: Tommy Thorn <foobar@nowhere.void>
Date: Sun, 21 May 2006 14:34:52 -0700
Links: << >> << T >> << A >>

alpha wrote:
> It's just for fun to run it in a FPGA rather than making an ASIC. I
> spent almost all Saturdays in the past 1 year for this project.
> I should say, it has lots challenge than a single-issue one.

Very cool, congratulations.

> True,
> clock speed is pretty low now now (30-60 Mhz). But I am planning to
> enhance it by using a smarter compiler to removing some corner case
> from the design.

How much work would it be to make it fully R3000 compatible (say, 
user-level only)?

> Hopefully I cam make it to 100Mhz range.
> Also, looks I need to buy an evaluation kit from Altera. Xilinx V4
> block ram gives me some trouble during instruction fetching.

Care to elaborate?

> My design is from scratch. Its instruction set is almost same as MIPS
> 3000 (without Multiplication). Lcc C compilier was ported.
> I can publish the source verilog files, do we have public domain for
> this purpose?

Picking a license (eg. GPL, LGPL, BSD, public domain, etc) is a separate 
issue from publishing (opencores, sourceforge, someones own web site 
[I'd be happy to host it for you fx.], etc).  Just be careful about 
third party components (such as LCC) which come with their own licence.

(IMHO: Out-of-Order on an FPGA is very cool, but will probably not lead 
to the best performance/LUT ratio - especially not if you can do 
compiler work also.    For single threaded performance, Nios II and 
MicroBlaze are impressive, as is John Jakson's R16.  A 2- or 4-way LIW 
may also make sense).

Tommy

Article: 102828
Subject: Re: LISP Workshop at ECOOP06
From: Tommy Thorn <foobar@nowhere.void>
Date: Sun, 21 May 2006 15:43:22 -0700
Links: << >> << T >> << A >>

[Following up to a 3-way cross post is likely to hurt my karma, but ...]

Colin Paul Gloster wrote:
> Which features are thought of as being Lisp-friendly?
> 
> Beware of the warning in Chapter 2 on page 109 of Hennessy, John L and 
> Patterson, David A, "Computer Architecture: A Quantitative Approach", 
> second edition:
> 
> "Pitfall: Designing a "high-level" instruction set feature specifically 
> oriented to supporting a high-level language structure.

I don't know about Lisp, but existing implementations on stock hardware 
of functional languages such as ML and Haskell tends to be penalized by 
latency on loads and unpredictable [dynamic] branches.

The same kind of support that helps speculative execution (non-trapping 
loads, predication, etc) is likely to help Lisp and friends.  Loads 
which masks off part of the address (tag bits) can be help. There are 
lots that can be done for hardware assisted garbage collection.  Finer 
control over the caches can help.

All of these are pretty mundane ideas however.  I'd be curious for more 
radical ones.

Tommy

Article: 102829
Subject: Re: How simple can FPGA design be? (Mission Possible 2006)
From: "int19h" <tirath@replacethispartwithmynickname.com>
Date: Mon, 22 May 2006 12:49:49 +1000
Links: << >> << T >> << A >>


"Antti" <Antti.Lukats@xilant.com> wrote in message 
news:1148241083.462402.288560@i40g2000cwc.googlegroups.com...
> Some things are simple.
> Some things are fun.
>
> FPGA's are both Simple and Fun - for all the Family!
> Arent they?
> Even on Sundays (when it rains)?
>
> I think they are, and here is the story:
>
> http://hydraxc.xilant.com/downloads/MissionPossible2006.pdf
>


I hope that iron had cooled down before you let Andre near it!

I got into a world of trouble once; my (at the time) 5 year old brother 
bumped his arm into my soldering iron that was cooling off the edge of my 
table clamped down by a textbook (those were some Spartan hobbyist days). 
Mom and dad gave me a (warranted) verbal thrashing regarding safety... my 
defence of "what was the little bastard doing in my room in the first place" 
didn't cut it.

Article: 102830
Subject: gate level simulation
From: venkatec@gmail.com
Date: 21 May 2006 23:48:41 -0700
Links: << >> << T >> << A >>



HI
             Anybody have  idea about gate level simulation? i am
working on
AMBH AHB Gate level simulation.when i am runing gates simultion for
ahb some of the signals are showing unknown(xxx), high impence(zzz)
state? then cheked for paritculer drivers for particuler signal(the
signal which gives zz state) also. those are same driving as rtl.no
difference in drivers.  when i ran rtl simulation for ahb its showing
correct results i
mean(data). when comes to gates  its givng such a states. if u have any
idea
pls give me suggestion?
waiting for reply
bye

Thanks in advance















Mark Murray wrote:
> On 21 May 2006 04:54:42 -0700, "Antti" <Antti.Lukats@xilant.com>
> wrote:
>
> >you need ByteBlaster II that supports the AS mode,
> >i think I was the first who made the hardware changes public to convert
> >and ByteBlaster to BB 2 but I dont have the reference any more
> >
> >its fairly simple change though
>
> I'm not using a real ByteBlaster, its the Elektor equivalent, and it
> has got an AS mode. Its circuit is close to the Altera one in their
> user guide, and it has the extra feedback bits that the BBII has.
>
> I suspect something to do with the parallel port because I get the
> error whether the "ByteBlaster" is connected or not.
> 
> FWIW, JTAG mode works just fine.
> 
> M

Article: 102831
Subject: Re: Error in XPS 7.1 mb_opb_wrapper
From: "savs" <vidyutg@gmail.com>
Date: 22 May 2006 00:58:47 -0700
Links: << >> << T >> << A >>

hey,
i tried it ..... but it didn't work :(
ne other suggestions ??

Article: 102832
Subject: [Xilinx V4SX55]DDR2 SDRAM controller + dual purpose pins
From: "Tim Verstraete" <tim.verstraete@barco.com>
Date: 22 May 2006 01:25:49 -0700
Links: << >> << T >> << A >>

Hey,

I'm using a V4SX55-FF1148 device and as framebuffer i have build a DDR2
controller ... now i'm having 2 of those controllers in the same device
and controller 1 is working perfectly but in controller 0 i have 2 pins
that always read 1. no matter what. those 2 pins happen to be on a dual
purpose pin (D0/D1 from configuration, but i'm using the serial slave
configuration).

All the VREF's are connected to the device on +0.9V, all the
IDELAYCTRL's are correctly locked since the other pins of the
framebuffer on the same bank give no issue and are working fine ...
this is way i'm thinking that is might have something to do with the
dual purpose pin configuration? i'm using ISE7.1SP4...

Do any of you have seen such a problem/issue?

hopefully someone can give me a hint ... thanks in advance,

kind regards,

tim

Article: 102833
Subject: Re: DDR2 SDRAM controller + dual purpose pins
From: "Antti" <Antti.Lukats@xilant.com>
Date: 22 May 2006 01:55:18 -0700
Links: << >> << T >> << A >>

did you check the 'persist' option for bitgen?
if the D0 is retained as config interface it will not come user io

Antti

Article: 102834
Subject: Re: DDR2 SDRAM controller + dual purpose pins
From: "Tim Verstraete" <tim.verstraete@barco.com>
Date: 22 May 2006 02:06:27 -0700
Links: << >> << T >> << A >>

No i did not use the persist option in bitgen, that was indeed the
first thing i checked ...

thanks in advance,

kind regards

tim

P.S. i add the bitgen log file ...

C:/Xilinx7/bin/nt/bitgen.exe -intstyle ise -w -g DebugBitstream:No -g
Binary:no -g CRC:Enable -g ConfigRate:4 -g CclkPin:PullUp -g
M0Pin:PullUp -g M1Pin:PullUp -g M2Pin:PullUp -g ProgPin:PullUp -g
DonePin:PullUp -g InitPin:Pullup -g CsPin:Pullup -g DinPin:Pullup -g
BusyPin:Pullup -g RdWrPin:Pullup -g TckPin:PullUp -g TdiPin:PullUp -g
TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g
UserID:0xFFFFFFFF -g DCMShutDown:Disable -g DCIUpdateMode:AsRequired -g
StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g
LCK_cycle:NoWait -g Security:None -g DonePipe:No -g DriveDone:No -g
Encrypt:No toplevel_800board.ncd

Summary of Bitgen Options:
+----------------------+----------------------+
| Option Name          | Current Setting      |
+----------------------+----------------------+
| Compress             | (Not Specified)*     |
+----------------------+----------------------+
| Readback             | (Not Specified)*     |
+----------------------+----------------------+
| CRC                  | Enable**             |
+----------------------+----------------------+
| DebugBitstream       | No**                 |
+----------------------+----------------------+
| ConfigRate           | 4**                  |
+----------------------+----------------------+
| StartupClk           | Cclk**               |
+----------------------+----------------------+
| CclkPin              | Pullup**             |
+----------------------+----------------------+
| DonePin              | Pullup**             |
+----------------------+----------------------+
| HswapenPin           | Pullup*              |
+----------------------+----------------------+
| M0Pin                | Pullup**             |
+----------------------+----------------------+
| M1Pin                | Pullup**             |
+----------------------+----------------------+
| M2Pin                | Pullup**             |
+----------------------+----------------------+
| PowerdownPin         | Pullup*              |
+----------------------+----------------------+
| ProgPin              | Pullup**             |
+----------------------+----------------------+
| InitPin              | Pullup**             |
+----------------------+----------------------+
| CsPin                | Pullup**             |
+----------------------+----------------------+
| DinPin               | Pullup**             |
+----------------------+----------------------+
| BusyPin              | Pullup**             |
+----------------------+----------------------+
| RdWrPin              | Pullup**             |
+----------------------+----------------------+
| TckPin               | Pullup**             |
+----------------------+----------------------+
| TdiPin               | Pullup**             |
+----------------------+----------------------+
| TdoPin               | Pullup**             |
+----------------------+----------------------+
| TmsPin               | Pullup**             |
+----------------------+----------------------+
| UnusedPin            | Pulldown**           |
+----------------------+----------------------+
| GWE_cycle            | 6**                  |
+----------------------+----------------------+
| GTS_cycle            | 5**                  |
+----------------------+----------------------+
| LCK_cycle            | NoWait**             |
+----------------------+----------------------+
| Match_cycle          | Auto*                |
+----------------------+----------------------+
| DONE_cycle           | 4**                  |
+----------------------+----------------------+
| Persist              | No*                  |
+----------------------+----------------------+
| DriveDone            | No**                 |
+----------------------+----------------------+
| DonePipe             | No**                 |
+----------------------+----------------------+
| Security             | None**               |
+----------------------+----------------------+
| UserID               | 0xFFFFFFFF**         |
+----------------------+----------------------+
| ActivateGclk         | No*                  |
+----------------------+----------------------+
| ActiveReconfig       | No*                  |
+----------------------+----------------------+
| PartialMask0         | (Not Specified)*     |
+----------------------+----------------------+
| PartialMask1         | (Not Specified)*     |
+----------------------+----------------------+
| PartialMask2         | (Not Specified)*     |
+----------------------+----------------------+
| PartialGclk          | (Not Specified)*     |
+----------------------+----------------------+
| PartialLeft          | (Not Specified)*     |
+----------------------+----------------------+
| PartialRight         | (Not Specified)*     |
+----------------------+----------------------+
| Encrypt              | No**                 |
+----------------------+----------------------+
| Key0                 | pick*                |
+----------------------+----------------------+
| KeyFile              | (Not Specified)*     |
+----------------------+----------------------+
| StartCBC             | pick*                |
+----------------------+----------------------+
| DCIUpdateMode        | AsRequired**         |
+----------------------+----------------------+
| ICAP_Select          | Auto*                |
+----------------------+----------------------+
| IEEE1532             | No*                  |
+----------------------+----------------------+
| Binary               | No**                 |
+----------------------+----------------------+

Article: 102835
Subject: Re: Why do the electronics manufacturers have to spam me?
From: "Symon" <symon_brewer@hotmail.com>
Date: Mon, 22 May 2006 10:19:36 +0100
Links: << >> << T >> << A >>

Rick,
It's because everyone on this newsgroup knows how good you are at dealing 
with stress, we all make up an email address ending @arius.com when we have 
to fill in the boxes. ;-)
Many thanks, Syms.
p.s. Just kidding mate, I still swear by my hotmail account, the spam filter 
features are quite good. I like your different email address idea though, I 
might start using that. (But with my own domain name, of course!)

"rickman" <spamgoeshere4@yahoo.com> wrote in message 
news:1148085652.895237.264580@j55g2000cwa.googlegroups.com...
>I give my email address in order to get support and Xilinx feels the
> need to send me spam.  I know it is through the support channels
> because I create a different address every time I use support.  Every
> time I end up getting spam.
>
> It's not just Xilinx, I once contacted Altera because I was getting
> spam from a third party at an address I only gave to Altera.
>
> I don't recall using this address, tektronix.drawing@arius.com, but I
> don't know why I would be receiving spam from Analog Devices using it.
>
>
> The list goes on and on.  Don't these companies realize the ill will it
> creates?
>

Article: 102836
Subject: Re: Have someone implementate the cpu86 or sparc embeded processor in the v-2 fpga
From: "Jon Beniston" <jon@beniston.com>
Date: 22 May 2006 02:41:09 -0700
Links: << >> << T >> << A >>

http://www.gaisler.com/products/leon2/leon.html

Cheers,
Jon

Article: 102837
Subject: MicroBlaze and IIC
From: Grata <thebestspirit@icqmail.com>
Date: Mon, 22 May 2006 11:54:32 +0200
Links: << >> << T >> << A >>

Hey

I am trying to get familiar by using a I2C-bus to connect to some external  
components, i'm quite new to the Xilinx EDK and Microblaze.
So I'm looking for examples to learn from.

I found a nice example that shows how to use the SPI.

http://www.xilinx.com/products/boards/s3estarter/files/Xil3S500E_Serial_Flash_v81.zip


Does anyone know if there exist something similar for I2C ?

Article: 102838
Subject: Re: Have someone implementate the cpu86 or sparc embeded processor in the v-2 fpga
From: "Antti" <Antti.Lukats@xilant.com>
Date: 22 May 2006 02:59:34 -0700
Links: << >> << T >> << A >>

the OP pretty much knows that url
so what he was actually asking was very unclear

SPARC (that is LEON) can be easily implemented in Virtex FPGA
same for CPU86 from HT-LAB so the answer to OP is YES lots of people
have implemented sparc and cpu86 in virtex.



Antti

Article: 102839
Subject: Re: MicroBlaze and IIC
From: "Antti" <Antti.Lukats@xilant.com>
Date: 22 May 2006 04:05:55 -0700
Links: << >> << T >> << A >>

dont be lazy! (and look at the folders from EDK!)

the I2C examples you asked can be found within 12 seconds, they are in

\EDK\sw\XilinxProcessorIPLib\drivers\iic_v1_02_a\examples

Antti

Article: 102840
Subject: Unknown Processor Version (8)
From: "Raymond" <raybakk@yahoo.no>
Date: 22 May 2006 05:17:48 -0700
Links: << >> << T >> << A >>

Hi there

When I try to start XMD for debugging I get the following error:
Unknown Processor Version (8) and Verify if FPGA Bitstream was
downloaded and DONE pin went High.

Does it mean that the processor on my Spartan Card is different from
the processor I yust have downloaded from my PC? The path in XPS is
pointing at the same elf file that is used in the SDK.

What can I do to make this error go away. Options?

Raymond

Article: 102841
Subject: incremental chip building in ISE
From: Sanka Piyaratna <jayasanka.piyaratna@gmail.com>
Date: Mon, 22 May 2006 23:19:35 +0930
Links: << >> << T >> << A >>

Hi,

I am currently involved in a large FPGA project using Xilinx Virtex 2 
pro devices. Building the FPGA from RTL can take quite a long time and 
therefore, I was looking through the process to build the FPGA 
incrementally. I am wondering if anyone has done this using the ISE 8.1 
and if you know of a reference that explains this process clearly.

Thank you,

Sanka

Article: 102842
Subject: Re: [Xilinx V4SX55]DDR2 SDRAM controller + dual purpose pins
From: "Brian Davis" <brimdavis@aol.com>
Date: 22 May 2006 06:52:05 -0700
Links: << >> << T >> << A >>

Tim Verstraete wrote:
> this is way i'm thinking that is might have something to do with the
> dual purpose pin configuration? i'm using ISE7.1SP4...

 If you by chance are using DCI on those particular pins, they won't
work properly unless you've set DCIUpdateMode = "Noisy"
( aka "Continuous" or "AsRequired" )

See:
 Answer Record # 14887: Virtex-II/-II Pro/-4, Configuration -
   Dual-purpose configuration pins do not function properly when they
   are set to a DCI standard

Brian

Article: 102843
Subject: Re: initial block processing in XST 8.1
From: "Jeff Brower" <jbrower@signalogic.com>
Date: 22 May 2006 07:35:08 -0700
Links: << >> << T >> << A >>

John-

> was using the reg declaration to initialize SRLs with non-zero data
> (reg [15:] MySRL = 16'h0802;) and found the INITs made it to the chip.

Ok... but was this declaration actually inside an "initial begin" block
or outside in some vanilla Verilog?  I've tried the syntax above on
single register declarations and it works, but I've had no luck on
array of registers.  I tried this syntax:

reg [31:0] array [11:0] = 64'h0C0001820C000080;

to set the first 2 regs in the array, but I ended up with no bits set.

> Problem was, everywhere there was a one, the shift register split into
> pieces with the ones implemented as registers and the zeros implemented
> in SRLs as appropriate even though one SRL could have made the whole
> thing work.

This happened just because of the INIT synthesis attribute?  Or XST
wanted to do it anyway, regardless of initial values?

-Jeff

Article: 102844
Subject: Urgent help programming SPI-flash trough JTAG (Spartan3E)
From: "Mellby" <bbb@bbb.com>
Date: Mon, 22 May 2006 16:40:46 +0200
Links: << >> << T >> << A >>

I need help to program the SPI-memory connected to a Spartan3E device. The 
memory is a M25P40.

I already have the devices on a circuit board.

What steps must I take to be able to program the SPI-memory via ISE8.1i?

A step by step guide would be nice.

Article: 102845
Subject: Re: Signal 2 clocks long but only one clock possible
From: "johnp" <johnp3+nospam@probo.com>
Date: 22 May 2006 07:43:05 -0700
Links: << >> << T >> << A >>

Dennis -
Can you post some of the code you use to generate the frame_ready
signal?  I suspect you've got a problem in how you pass the signal
from one clock domain to the other, but without seeing some code
it's hard to guess what's going on.

John Providenza

Article: 102846
Subject: Re: ispLEVER Starter 6.0 FPGA Design Software Available
From: "johnp" <johnp3+nospam@probo.com>
Date: 22 May 2006 07:48:01 -0700
Links: << >> << T >> << A >>

Any idea what the limitations of the OEM version of Modelsim are for
the
Lattice OEM version?

John Providenza

Article: 102847
Subject: Re: Urgent help programming SPI-flash trough JTAG (Spartan3E)
From: "Mellby" <bbb@bbb.com>
Date: Mon, 22 May 2006 16:56:23 +0200
Links: << >> << T >> << A >>

I want to be able to use Indirect In-System Programming (as described in 
XAPP445 page 9).

"Mellby" <bbb@bbb.com> wrote in message 
news:4471cdbd$0$15790$14726298@news.sunsite.dk...
>I need help to program the SPI-memory connected to a Spartan3E device. The 
>memory is a M25P40.
>
> I already have the devices on a circuit board.
>
> What steps must I take to be able to program the SPI-memory via ISE8.1i?
>
> A step by step guide would be nice.
>
>
>

Article: 102848
Subject: Re: Urgent help programming SPI-flash trough JTAG (Spartan3E)
From: "Antti" <Antti.Lukats@xilant.com>
Date: 22 May 2006 08:15:52 -0700
Links: << >> << T >> << A >>

well there are no useable tools ava=EDlable yet.
i have internal tools that do that, either using EXTEST or small
ipcores that are loaded into the S3e
please contact in private if interested=20

Antti

Article: 102849
Subject: Independent clock FIFOs
From: rob.misc@gmail.com
Date: 22 May 2006 08:16:50 -0700
Links: << >> << T >> << A >>

Hi all,

I am using a Virtex-II Pro in ISE 8.1i and have generated a couple of
asynchronous FIFOs in Coregen. The data path is shown below:

Input @ 133 MHz ---> Core @ 150 MHz ---> Output @ 133 MHz

The 133 MHz clock is from the DCM and the 150 MHz clock is from the DCM
FX output. The problem is that when compiling, ISE tries to meet a
timing constraint equal to the difference in the two clock periods
(i.e. 0.852ns) for some nets in the FIFOs. Specifically, the nets with
problems are of the form:

source: output_fifo/BU2/U0/fgas/flblk/clkmod/wrx/pntr_gc_*
dest: output_fifo/BU2/U0/fgas/flblk/clkmod/wrx/pntr_gc_x_*

and

source: input_fifo/BU2/U0/fgas/flblk/clkmod/rdx/pntr_gc_*
dest:  input_fifo/BU2/U0/fgas/flblk/clkmod/rdx/pntr_gc_x_*

I am guessing these must be something to do with the Gray code counter
and that it is a false constraint. Is that so? If so, why is ISE
getting confused?

I don't if it is relevant but the FIFOs have full and empty flags which
are not actually being used and count outputs which are (and I have
checked that they are connected in the right clock domains too!).

Any help appreciated.
Thanks,
Rob.

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