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John, No X-Tracer 25-30% slower as full version (Altera has same limitation, Xilinx has even slower version) That's it. Luc On 22 May 2006 07:48:01 -0700, "johnp" <johnp3+nospam@probo.com> wrote: >Any idea what the limitations of the OEM version of Modelsim are for >the >Lattice OEM version? > >John ProvidenzaArticle: 102851
When you have two independent clocks (133 and 150 MHz), the difference of the two clock periods heas no meaning whatsoever. These two clocks will have any phase- or delay-difference imaginable. They just "walk over each other". That's what makes the design so complex. Meeting timing constraints between independent clock is an exercise in futility. Don't do it! Ignore any complaints! Peter Alfke, XilinxArticle: 102852
Can anyone explain why the quotes that we are getting from Xilinx are 4x their own marketing materials? For example this article http://www.ednasia.com/article.asp?articleid=1913 says that quantity 50k of an fx12 would be $29.99. We are being quoted about $112 for 100k units. Most of the other device prices we are getting are also about 4x what I suspect they must be considering the applications they are going into. Are we talking to the wrong people? Is there a direct xilinx contact to negotiate large volume deals. Thanks, ClarkArticle: 102853
Colin Paul Gloster wrote: > On Fri, 19 May 2006, Hans H=FCbner posted: > Some of the topics of interest are: > > * Implementation of LISP-friendly CPUs in hardware > [..]" > > Which features are thought of as being Lisp-friendly? > > Beware of the warning in Chapter 2 on page 109 of Hennessy, John L and > Patterson, David A, "Computer Architecture: A Quantitative Approach", > second edition: > > "Pitfall: Designing a "high-level" instruction set feature specifically > oriented to supporting a high-level language structure. > > [..] > > [..] often the instructions are simply overkill-they are too general for > the most frequent case, resulting in unneeded work and a slower > instruction. [..] I think you're probably right. It is difficult to introduce instructions useful to Lisp in such a way that they:- * Don't make the machine harder to design, or make it slower * Don't fix the idea of how certain lisp idioms should be implemented But still I'd be interested to see what people come up with. The pitfall H & P describe is that of designing an instruction set in a high-level manner, which is not the subject of the discussion. It may be possible to make a microprocessor more lisp-friendly by doing a lot less than this. I'm not sure it's really necessary though, modern lisp compilers like CMUCL and SBCL produce fast code. Those performance faults that there are are mainly due to their weaknesses as compiler/VMs, rather than any fundamental problem converting lisp into machine language.Article: 102854
the vendor (i cant reveal who that is) is using the CoolRunner in a design. it is not Xilinx. N.Article: 102855
cannot say. vendor is not Xilinx.Article: 102856
FX12 in 100k is defenetly not 112USD the 29.99 for FX12 sure sounds like really nice price.. try direct contacts for 100k volumes you must get better pricing for sure unless you are asking for largest package fastest speed industrial temperature.. the advertized pricing is always the lowest price for given part smallest pack, slowest speed, commercial temp, etc AnttiArticle: 102857
When you say short,: how short is short? Measure the I/V characteristic for both polarities. That might give youa hint whether it is "ohmic" or whether a diode is involves. I still maintain that your mystery vendor is imagining things.( I meant ro write something not fit for this newsgroup...) Peter AlfkeArticle: 102858
Headline pricing often has a date sometime in the future against it. There are also price variations against package. The headline price will also usually be done on the cheapest package and speed grade. I'm guessing that you are using the FF668 package by the prices you have. What you need to do is to talk to your FAE who may be either at distributor level or if you are a big account it will likely be Xilinx or the country rep. Depends where you are and who you are. Alternativly some Xilinx partners like ourselves, or even large assembler operations, can be used as negotiators of price as we know reasonably well how to drive the system and what can be attained in a project with a tight budget. John Adair Enterpoint Ltd. - Home of Raggedstone1. The Low Cost Spartan-3 Development Board. http://www.enterpoint.co.uk "Anonymous" <someone@microsoft.com> wrote in message news:Ajlcg.3653$Qg.2028@tornado.southeast.rr.com... > Can anyone explain why the quotes that we are getting from Xilinx are 4x > their own marketing materials? For example this article > > http://www.ednasia.com/article.asp?articleid=1913 > > says that quantity 50k of an fx12 would be $29.99. We are being quoted > about > $112 for 100k units. Most of the other device prices we are getting are > also > about 4x what I suspect they must be considering the applications they are > going into. > > Are we talking to the wrong people? Is there a direct xilinx contact to > negotiate large volume deals. > > Thanks, > Clark > >Article: 102859
these are the bitgen options i'm using: C:/Xilinx7/bin/nt/bitgen.exe -intstyle ise -w -g DebugBitstream:No -g Binary:no -g CRC:Enable -g ConfigRate:4 -g CclkPin:PullUp -g M0Pin:PullUp -g M1Pin:PullUp -g M2Pin:PullUp -g ProgPin:PullUp -g DonePin:PullUp -g InitPin:Pullup -g CsPin:Pullup -g DinPin:Pullup -g BusyPin:Pullup -g RdWrPin:Pullup -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g DCMShutDown:Disable -g DCIUpdateMode:AsRequired -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:No -g DriveDone:No -g Encrypt:No toplevel_800board.ncd thanks in advance, kind regards, Tim Brian Davis wrote: > Tim Verstraete wrote: > > this is way i'm thinking that is might have something to do with the > > dual purpose pin configuration? i'm using ISE7.1SP4... > > If you by chance are using DCI on those particular pins, they won't > work properly unless you've set DCIUpdateMode = "Noisy" > ( aka "Continuous" or "AsRequired" ) > > See: > Answer Record # 14887: Virtex-II/-II Pro/-4, Configuration - > Dual-purpose configuration pins do not function properly when they > are set to a DCI standard > > BrianArticle: 102860
something is wrong with MDM-JTAG XMD is not able to connect to the processor, its an hardware issue nothing todo with the software applications the best is to try out some working MB soc that has MDM in it, does XMD work with it? if yes then compare with your project AnttiArticle: 102861
lb.edc@telenet.be wrote:
> In my opinion, if your design needs a simulator
Every design needs a simulator. Even as simple as that one from
Quartus Webpack -- it is still infinitely better than no simulator.
> For this price you get the OEM version of ModelSim - and this
> is by far the best deal you can get
Currently the best deal I can get is not to use Lattice or Actel
parts -- the other vendors provide all the necessary tools.
Best regards
Piotr Wyderski
Article: 102862Tim Verstraete wrote: > these are the bitgen options i'm using: Sorry, I managed to chop off a line in my first post - double check the detailed bitgen report to make sure BitGen actually honored your DCIUpdateMode setting. In 6.something, on a V2Pro, BitGen would automagically set the "quiet" mode if DCI usage were detected, overriding the command line flags. Even if the report looks OK, I'd investigate dual usage pins further, if you're using DCI, given the past problems. Although Xilinx removed that DCI pin restriction from the V4 Users Guide, as compared to V2/Pro User's Guide, the restriction has re-appeared in the Answer Records for V4. BrianArticle: 102863
I use xilinx build in simulator for Lattice designs :) or ok usually I am not doing that either. but sure a simulator is a nice a have feature (when it is available) AnttiArticle: 102864
Hi, I am trying to build a very simple Spartan3 - based FPGA board. The idea is to have FPGA + Flash PROM & Jtag header and I/Os. Nothing else. I am running into a problem: Using my DMM, VCCAUX & VCCO seem to be shorted to GND. At this point I am absolutely sure that they are shorted through the Xilinx chip. Does Xilinx chip need to be programmed with some kind of default configuration, before it can even be powered on? In other words, should there be some kind of *safety configuration* programmed into the Flash PROM, prior to applying power to Xilinx FPGA? If you have any references, links, suggestions, guidelines for putting a single FPGA chip on a board with nothing other than the basics for programming it, I would be grateful if you point me to them. I copied my design from Digilent Spartan3 Starter Kit, getting rid of all the *starter kit* peripherals there and just leaving the essentials: JTAG header, Flash PROM, FPGA, expansion I/Os Thanks!Article: 102865
no. DMM is not good to measure but before config the VCCxx pins should take some normal current, eg not short circuit. doing a s3 proto is rather simple, just connect the GND, VCCxx, JTAG and pull PROG_B thats it AnttiArticle: 102866
thanks i will definetly check it out ... and might try the bitgen of ISE8.1 + ISE7.1 and do some investigation on it ... thank you for the interesting tip ... i'll let you know what happens ... thanks, kind regards, TimArticle: 102867
If VccAux appears to be grounded in a powered board, your problems will never be with the device. If VccAux never comes up, there is no configuration to do anything negative to your board. A newly-powered Spartan3 comes up in an innocuous state until the device is programmed at which point it does what it's programmed to do. Check your soldering. Check your gerbers. I've seen problems with both despite the best attempts of engineers and design software. "Telenochek" <interpasha@hotmail.com> wrote in message news:1148318946.683392.228470@j73g2000cwa.googlegroups.com... > Hi, I am trying to build a very simple Spartan3 - based FPGA board. > The idea is to have FPGA + Flash PROM & Jtag header and I/Os. > Nothing else. > > I am running into a problem: > Using my DMM, VCCAUX & VCCO seem to be shorted to GND. > At this point I am absolutely sure that they are shorted through the > Xilinx chip. > > Does Xilinx chip need to be programmed with some kind of default > configuration, before it can even be powered on? > In other words, should there be some kind of *safety configuration* > programmed into the Flash PROM, prior to applying power to Xilinx FPGA? > > If you have any references, links, suggestions, guidelines for putting > a single FPGA chip on a board with nothing other than the basics for > programming it, I would be grateful if you point me to them. > > I copied my design from Digilent Spartan3 Starter Kit, getting rid of > all the *starter kit* peripherals there and just leaving the > essentials: JTAG header, Flash PROM, FPGA, expansion I/Os > > Thanks! >Article: 102868
----------------------------------- doing a s3 proto is rather simple, just connect the GND, VCCxx, JTAG and pull PROG_B thats it ------------------------------------ That's exactly whats on my board + Flash PROM. On a fully working Spartan3 board from Digilent, when the board is not powered up: the VCCO and VCCAUX appear to be shorted to GND (using DMM). Of course, this could be due to low impedance between supplies and GND, due to high Iq through the FPGA. But the board is not powered at all. How do I debug the shorts if I can't even test for them?Article: 102869
Is it possible to get Xilinx to just tell me what the cheapest V4FX device is possible for 100k units? The device also has to be easy path compatible as the eventual product is going to be very price sensitive. Thanks, Clark "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk> wrote in message news:1148315613.24277.0@demeter.uk.clara.net... > Headline pricing often has a date sometime in the future against it. There > are also price variations against package. The headline price will also > usually be done on the cheapest package and speed grade. I'm guessing that > you are using the FF668 package by the prices you have. > > What you need to do is to talk to your FAE who may be either at distributor > level or if you are a big account it will likely be Xilinx or the country > rep. Depends where you are and who you are. Alternativly some Xilinx > partners like ourselves, or even large assembler operations, can be used as > negotiators of price as we know reasonably well how to drive the system and > what can be attained in a project with a tight budget. > > John Adair > Enterpoint Ltd. - Home of Raggedstone1. The Low Cost Spartan-3 Development > Board. > http://www.enterpoint.co.uk > > > "Anonymous" <someone@microsoft.com> wrote in message > news:Ajlcg.3653$Qg.2028@tornado.southeast.rr.com... > > Can anyone explain why the quotes that we are getting from Xilinx are 4x > > their own marketing materials? For example this article > > > > http://www.ednasia.com/article.asp?articleid=1913 > > > > says that quantity 50k of an fx12 would be $29.99. We are being quoted > > about > > $112 for 100k units. Most of the other device prices we are getting are > > also > > about 4x what I suspect they must be considering the applications they are > > going into. > > > > Are we talking to the wrong people? Is there a direct xilinx contact to > > negotiate large volume deals. > > > > Thanks, > > Clark > > > > > >Article: 102870
1) Before you assemble, check for supply and ground shorts. Too late? 2) Do a visual inspection of soldered TQFP leads with a stereo microscope If you're doing a BGA instead, it's a much different issue. Xray inspection of assembled boards would be needed to troubleshoot BGA shorts; this inspection is available from most professional assemblers. "Telenochek" <interpasha@hotmail.com> wrote in message news:1148322083.396270.227300@38g2000cwa.googlegroups.com... > ----------------------------------- > doing a s3 proto is rather simple, just connect the GND, VCCxx, JTAG > and pull PROG_B thats it > ------------------------------------ > That's exactly whats on my board + Flash PROM. > > On a fully working Spartan3 board from Digilent, > when the board is not powered up: > the VCCO and VCCAUX appear to be shorted to GND (using DMM). > Of course, this could be due to low impedance between supplies and GND, > due to high Iq through the FPGA. But the board is not powered at all. > > How do I debug the shorts if I can't even test for them? >Article: 102871
http://xilant.com/content/view/35/2/ EASY - the board as above DOES work, I used it for SPI indirect programming testing AnttiArticle: 102872
> 1) Before you assemble, check for supply and ground shorts. > Too late? Its not too late, I have multiple boards for this. Without FPGA (TQFP144) chip on board, there aren't any shorts. I have checked connections with stereo microscope, no solder bridges. I think the next thing I will try is to assemble everything, but the FPGA and verify that everything without FPGA is fine. Trouble is that FPGA will be harder to solder with all the stuff on the board already. But doable. Thanks!Article: 102873
EASY - the board as above DOES work, I used it for SPI indirect programming testing ----------------------------- Very nice but where is the schematic for it? Thanks!Article: 102874
You really need to get a FAE involved and to check both the Easypath availability and the charges and NRE for using those parts too. The 100K volume market is for Xilinx, and all the other vendors for that matter, a market that they are seriously interested in. My educated guess is that the SF363 will be the package that is cheapest but there will be other considerations such as board layout that you should consider on this package at the same time. I also don't know Easypath status for that package so that needs to be checked. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk "Anonymous" <someone@microsoft.com> wrote in message news:Tincg.3668$Qg.540@tornado.southeast.rr.com... > Is it possible to get Xilinx to just tell me what the cheapest V4FX device > is possible for 100k units? The device also has to be easy path compatible > as the eventual product is going to be very price sensitive. > > Thanks, > Clark > > "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk> wrote > in > message news:1148315613.24277.0@demeter.uk.clara.net... >> Headline pricing often has a date sometime in the future against it. >> There >> are also price variations against package. The headline price will also >> usually be done on the cheapest package and speed grade. I'm guessing >> that >> you are using the FF668 package by the prices you have. >> >> What you need to do is to talk to your FAE who may be either at > distributor >> level or if you are a big account it will likely be Xilinx or the country >> rep. Depends where you are and who you are. Alternativly some Xilinx >> partners like ourselves, or even large assembler operations, can be used > as >> negotiators of price as we know reasonably well how to drive the system > and >> what can be attained in a project with a tight budget. >> >> John Adair >> Enterpoint Ltd. - Home of Raggedstone1. The Low Cost Spartan-3 >> Development >> Board. >> http://www.enterpoint.co.uk >> >> >> "Anonymous" <someone@microsoft.com> wrote in message >> news:Ajlcg.3653$Qg.2028@tornado.southeast.rr.com... >> > Can anyone explain why the quotes that we are getting from Xilinx are >> > 4x >> > their own marketing materials? For example this article >> > >> > http://www.ednasia.com/article.asp?articleid=1913 >> > >> > says that quantity 50k of an fx12 would be $29.99. We are being quoted >> > about >> > $112 for 100k units. Most of the other device prices we are getting are >> > also >> > about 4x what I suspect they must be considering the applications they > are >> > going into. >> > >> > Are we talking to the wrong people? Is there a direct xilinx contact to >> > negotiate large volume deals. >> > >> > Thanks, >> > Clark >> > >> > >> >> > >
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