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When I used coregen to create a DCM it provided the simulation code in verilog (ISE 8.1). My old projects in 7.x created these in VHDL. Is there a way to select which code type is created? I do everything in VHDL. Thanks, JoelArticle: 103201
Hi,
When you create the core with EDK, the IP core is a slave by
default. Make sure you also connect it to the OPB Bus after you create
the core.
Thanks,
Parag
Article: 103202hi folks, i'm looking for suggestions on a good starter board/fpga so i can try my hand at getting uclinux to run on an fpga with ethernet and serial connections. something not too terribly expensive would be nice, but also something capable, something i can use for getting into the whole "fpga uclinux" thing .. that won't tie my hands later because it's too small, slow, or just weak. it would be nice if it used a widely available fpga that i could gain experience with so that at some later time i might surface mount one myself on a board of my own creation. thank you! :)Article: 103203
Ron schrieb: > raarce@gmail.com wrote: > >> Is there a way in Xilinx ISE of knowing the percentage of routing >> resources that have been utilized after Place and Routing? > > > I too would love to see this Rafael. One of the other vendor's tools > (Altera?) prints out the percentage of the FPGA devoted to routing so > that you can see how much routing overhead there is, I would really like to have a routing congestion map in the floorplan. I am sure the people that develop the algorithms have that implemented. Maybe it could be ported to ISE floorplanner? Kolja SulimmaArticle: 103204
>For any of you familar with the Xilinx Values, the 'C' in the catch >phrase (first letter) refers to 'customer.' The customer is the first >thing we (should) think about when deciding anything. For any of you >who ever visited, the "org chart" was my favorite: The top was the >customer, with the Board of Directors at the bottom (upside down of a >traditional org chart). When an organisation grows beyond a certain point it starts to have a life of it's own.. ;)Article: 103205
Hi Ron, You are correct. Altera's Quartus II software will print out average and peak % utilization of routing. There is also the "View Routing Congestion" option in the Timing Closure Floorplan Editor. This tool shows you graphically where routing congestion is occuring in your design, and which types of wires it is affecting. Regards, Paul Leventis Altera Corp.Article: 103206
alpha wrote: > My design is from scratch. Its instruction set is almost same as MIPS > 3000 (without Multiplication). Lcc C compilier was ported. > I can publish the source verilog files, do we have public domain for > this purpose? You could put it on opencores.org - there are quite a number of CPUs on there (and other stuff) -- Daniel O'Connor software and network engineer for Genesis Software - http://www.gsoft.com.au "The nice thing about standards is that there are so many of them to choose from." -- Andrew Tanenbaum GPG Fingerprint - 5596 B766 97C0 0E94 4347 295E E593 DC20 7B3F CE8CArticle: 103207
Thanks Dave. Yes, you were correct sorry that i have serval version of this code now, and i even comfuse myself. as a result, my program is not accroding to the steps. For rdSig and wrSig, I am reading and writeing at the same time, but I just ignore the incoming data while i am sending it. Since serial port using 2 different bus, it should be ok, and it shouldn't effect the outgoing data. Let me know if my assumption is wrong. The send signal is for a process(not shown here) to inform this main process the X and Y is has change and ready to send it out, that's why my program start with sending. Besides these, what are the possiblity that the simulation works correctly, and after the the design flow, the actual on-chip running becomes wired? How could I have the simulation close enough to the on-chip running Thanks for your advice and help, YiQiArticle: 103208
On 27 May 2006 11:07:09 -0700, "savs" <vidyutg@gmail.com> wrote: >Hi, >I was wondering if it is possible to design a peripheral (for >Microblaze) in EDK 7.1 which is connected to more than one OPB bus. >If yes, how can this be done ? > Never tried it, but I think you should create both OPB buses with differente preffixes (i.e. OPB1 and OPB2) and then add two lines to MPD file: BUS_INTERFACE BUS = SOPB1, BUS_STD = OPB, BUS_TYPE = SLAVE BUS_INTERFACE BUS = SOPB2, BUS_STD = OPB, BUS_TYPE = SLAVE But I never tried it! ZaraArticle: 103209
>1) If the UART received a char (RDA = '1') then goto 2, else goto 1 >2) Read the char from the UART. If the char is ASCII '1' (31h) then >goto 3 else goto 1 >( rdSig <= '1'; if dbOutSig = x"31" then goto 3 ) >3) if the UART's Transmit Buffer is Empty (TBE = '1') then goto 4, else >back to 3 >4) write the 1st char into the UART (wrSig <= '1', dbInSig <= char in >signal X) >5) if the UART's Transmit Buffer is Empty (TBE = '1') then goto 6, else >back to 5 >6) write the 2nd char into the UART >( wrSig <= '1', dbInSig <= char in signal Y ) >DONE Dave, I could sorry to say your steps won work, It the 1st char won able to send. Because the speed of the FPGA clock is 50MHz and the UART is lot more slow. For this FSM, it is operating in the FPGA clock in 50MHz, while the first char is place into the data bus, and the FSM just into step 5, the UART component still hasn't been update(slow clocking at 9600). The TBE will still in '1', so it will overwrite the 1st char and send the 2nd one. That's why i will need to wait until TBE to '0'. This could be fix by simply adding a condition that until the TBE = '0' then go to step 5, otherwise stay at step 4. What I don't understand is in my code, why I need to have a waitSend state before the initial state of the next char? Sorry... I think I am a "problem kid", questions keep coming up, and I couldn't solve it. Please do help me. ... Thanks YiQiArticle: 103210
int19h kirjoitti: > try ssh -XY... > > Unfortunately doesn't work. AnttiArticle: 103211
Is there a way, when instantiating a module in Verlog, to specify that
a certain output port of the module was intentionally left not
connected ?
Currently I am using the following syntax:
.MyPort(),
but I do get a warning message (using ISE 8.1i).
Thanks,
Jim
Article: 103212Hi, I'm currently working with ISE 7.1 SP4, but I'd now like to try the 8.1 SP3 version. Can I install 8.1 on the same pc where I have 7.1? Will I get conflicts or will I be able to work with both, installed on the same pc? Thanks, MarcoArticle: 103213
I would like to know more about configuring PCI.Could you suggest some documents which would help me.I would like to know details regarding configuration read and write and the mechanism used to configure PCI using the configuration space.Article: 103214
you will need to have path and env setup to start one of them, but they can be installed on the same PC with no conflicts AnttiArticle: 103215
Ayon kay jpvarkey@gmail.com: > I would like to know more about configuring PCI.Could you suggest some > documents which would help me.I would like to know details regarding > configuration read and write and the mechanism used to configure PCI > using the configuration space. hi, config read/write: those are trasactions initiated by the bus master to read/write from/to a pci card on the bus, like knowing who's in, whats its Device ID, Vendor ID, etc. for more info: try PCI Specification Manual and/or the book PCI System Architecture by Mindshare. -k ---- Reflections of fear makes shadows of nothing.Article: 103216
Hi Antti, so far with ISE 7.1 I've only have the system variable "c:\xilinx71" in my environment variables list, is this the only one I should switch in order to move from 7.1 to 8.1 and back or ate there other settings I should take care about? Thanks, MarcoArticle: 103217
it better to be sure that the path only points to the relevant install location as well, except that its only the XILINX env variable I thinkArticle: 103218
You could look at the hpe mini boards from Gleichmann Electronics Research: http://www.ger-fae.com/hpe_mini.html There is a board for Altera CycloneII EP2C35 (350 Euro) And one for Lattice ECP33 (450 Euro) Stefan.Article: 103219
"alpha" <zhg.liu@gmail.com> wrote in message
news:1148669021.747497.47730@g10g2000cwb.googlegroups.com...
>
> > > Uncle Noah wrote:
> > >> Xilinx block RAM is synchronous read. Is this the source of your
> > >> problem?
>
> [YES, Xilinx's sync read give me trouble.]
You may already know about it, but there's a useful trick you might be able
to make use of to obtain "asynchronous-looking" BRAM in Xilinx parts. It
should work with anyone else's parts as well.
If you disable the output registers of the BRAM, your latency of data out is
a single cycle. More precisely: you set up the read address, apply a clock
edge, and your data comes out a little while later. The key thing is, you
only need a single edge. Now, if you use the opposite edge from the
surrounding logic (i.e. usually the falling edge instead of the rising
edge), you can get the read done within a single cycle (instead of having to
wait until the next rising edge for the data). In the timing diagram below,
point 'B' is the edge used for the BRAM, where the address is sampled. As
you can see, the data addressed by the address value presented at 'A' is
ready by the next edge 'C'. The region marked 'x' is the clock-to-out delay
from the BRAM (2ns or more depending on the device family).
A B C
-----+ +------+ +------+ +----
| | | | | |
+------+ +------+ +------+
_____________
/ \
------------+ Addr +------------------
\_____________/
__________
/x/ \
--------------------+xx| Data +----------
\x\__________/
The only problem with this approach is that it limits the speed of your
circuit. Since you were talking about 33MHz, this won't hurt you at all,
whatever family you're targeting.
Cheers,
-Ben-
Article: 103220Thanks Antti, MarcoArticle: 103221
and there is really uclinux available on the Lattice board?? WAU! I did not know. AnttiArticle: 103222
Hi! I am facing a problem regarding Xilinx CPLD Readback. One of our engineers left the country who designed the system back in 2000 and is out of touch now. I have no idea where are the original design files and the JEDEC files. However I do have two or 3 boards which have the working CPLD with the code I need. I have no experience with a readback feature. Can anyone help in this regard? I have a Xilinx PC4 cable and the ISE software. Can I use it to readback the Jedec file from the CPLD? I have read in the data sheet of XC9572 that it has data protection features. What will I get if the device is protected? Need your expert opinion. ShabanaArticle: 103223
Hi Marco, Using Batch files works well - create a .bat file with lines such as: REM ### start ise/edk 7.1 - setup the paths first set XILINX c:\xilinx71 set XILINX_EDK c:\edk\7.1 set PATH %XILINX%\bin\nt;%XILINX_EDK%\bin\nt;%PATH% REM ### start the program xps.exe Having a separate file for both versions you want should work, as it sets the environment vairables first, and then runs the program. I use this on both linux and windows. hope it helps! Marco wrote: > Hi, > I'm currently working with ISE 7.1 SP4, but I'd now like to try the 8.1 > SP3 version. Can I install 8.1 on the same pc where I have 7.1? Will I > get conflicts or will I be able to work with both, installed on the > same pc? > Thanks, > MarcoArticle: 103224
I removed any DCI and used the -g DCIUpdateMode:AsRequired and still have the same problem ... i also tried using ISE8.1 and ISE7.1 but they both give me the same result ... could it be that i'm using a Stepping ES device ... i might try the Stepping 1 devices? thanks in advance, kind regards, Tim
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