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I've been eyeing the Altium Livedesigner evaluation boards as a potentially cheap way to get a reasonably powerful FPGA board to play with. Either the Altera or Xilinx board seem to have decent size parts, and plenty of accessories - especially for $99 http://www.altium.com/Community/LiveDesignEvaluationBoards/ The problem is that neither have a configuration memory - which is understandable given the target audience. I'm curious if anyone owns one, and has looked to see if the necessary configuration pins are brought out anywhere. The schematic for the Xilinx version shows that all but the din and init_b signals should be available at either resistors or LED's. Not sure what the red lines mean in the schematic. They could be direct vias to either ground or VCC, or test points. Has anyone attempted to add a configuration PROM to either of these boards? Thanks!Article: 103126
Antti wrote: > after is only simulation > you must use some clocked process from some clock to generate the > required timing Thanx, I'll try that! - R.Article: 103127
Jim, > So, there is if anything a _growing_ trend to disconnect design-lab > machines from the NET, or have one Document-NET PC in the corner... this may be more subtle than it seems today. I have been witnessing a wintel PC doing weird things every time I "restart" it: it stays for a long time in a state preceeding the blue screen which says "saving your personal settings", and does a lot of CPU work with brief disk accesses every few seconds. Looks like a typical data compression task at work. More, the time this takes is proportional to the time the PC was up, i.e. the longer I don't reset it the longer this takes to execute (up to tens of minutes if I have not reset it a for a few days). Now when do the data go out, how etc. I really don't know, nor am I particularly worried about it since I keep on that wintel TV set (oops, PC) nothing I don't want being made public (and if someone is keen on listening to my screams while debugging something stubborn - yes, I do have a mike connected - he might just ask me to record and send them, I will :-). So I am not at all surprised by the trend you refer to, it is a healthy one, I just wonder how efficient this can be using todays PCs. Probably doable, but it takes just a small mistake and - ouch, the data are out... > > the connection is always there to web. Question is - how long until license > > codes for software rely on a web access for authorisation? > > Hopefully, that will never happen, as vendors will realise it will > kill their business . Well we can only hope you will be right on this. My personal feeling is that it is unavoidable - what will people do if the single source of their parts suddenly switches to a web-authorising tool while witholding (as they do for decades) the information needed for other parties to write an alternative? I don't think they will have many options except to abandon the product (and possibly get out of busyness), complain to the Pope, or just obey... Dimiter ------------------------------------------------------ Dimiter Popoff Transgalactic Instruments http://www.tgi-sci.com ------------------------------------------------------ Jim Granville wrote: > John Adair wrote: > > > The amount of web linkage is getting very annoying. Personally I block all > > requests with my firewall and run some machines internet isolated but this > > does lead to occasional other issues as the tools are beginning to assume > > the connection is always there to web. Question is - how long until license > > codes for software rely on a web access for authorisation? > > Hopefully, that will never happen, as vendors will realise it will > kill their business . > ( I suppose some 'slow learners' will have to find out the hard way..) > > There was an interesting case IIRC, last year in europe, where a > internet-connected machine in a lab, was breached and valuable > information extracted - as in trade secrets/patent relevent stuff, not > your usual email lists... now that's WAY above the normal nuisance level > of > > So, there is if anything a _growing_ trend to disconnect design-lab > machines from the NET, or have one Document-NET PC in the corner... > Vendors that miss this trend, will get their fingers burnt. > > -jgArticle: 103128
dp wrote: > Jim, <snips) >>>the connection is always there to web. Question is - how long until license >>>codes for software rely on a web access for authorisation? >> >> Hopefully, that will never happen, as vendors will realise it will >>kill their business . > > > Well we can only hope you will be right on this. Maybe I am an optimist :) > My personal feeling > is that it is unavoidable - what will people do if the single source > of their parts suddenly switches to a web-authorising tool while > witholding > (as they do for decades) the information needed for other parties to > write an alternative? I don't think they will have many options except > to abandon the product (and possibly get out of busyness), complain > to the Pope, or just obey... Once one large corporations lawyers, contact another's, you'd be amazed at what can happen :) Or talk to "homeland security" (right name?) in the USA and mention that in deploying this system, if the net goes down, so does commerce... It is up to the user-base to point out the pitfalls, and risks, and I am (optimistic) sanity will prevail.... -jgArticle: 103129
jaxato@gmail.com wrote: > Hello PPL, > > I would like to know what are the current implementations for the > internal blocks inside a DSP48E. This of course applies to the new > Virtex-5 FPGA. How is Xilinx building, at RTL, the 25 X 18 multiplier > (is it a booth?) as well as the 48 X 48 adder blocks? > > Thanks for any help > Jacques > One hint to the internal construction lies in the fact that the V4 documentation tells you that the adder is a three input adder that performs the final add in the multiplier plus the C input. From that, you can infer a carry-save architecture (Booth is one possibility). Of course, you still don't know the exact details, but it does narrow it down considerably.Article: 103130
On Thu, 25 May 2006 20:47:59 -0400, Ray Andraka <ray@andraka.com> wrote: >jaxato@gmail.com wrote: >> Hello PPL, >> >> I would like to know what are the current implementations for the >> internal blocks inside a DSP48E. This of course applies to the new >> Virtex-5 FPGA. How is Xilinx building, at RTL, the 25 X 18 multiplier >> (is it a booth?) as well as the 48 X 48 adder blocks? >> >> Thanks for any help >> Jacques >> > One hint to the internal construction lies in the fact that the V4 >documentation tells you that the adder is a three input adder that >performs the final add in the multiplier plus the C input. From that, >you can infer a carry-save architecture (Booth is one possibility). Of >course, you still don't know the exact details, but it does narrow it >down considerably. Forgive me if I don't understand but what does Booth have to do with carry-save ? Booth is a partial product generation/reduction techique. How you add the resulting partial products (carry-save, carry-select, ripple) has nothing to do with it. Also you can do carry-save without doing a booth encoding first. Actually there are some studies which say that booth encoding is not suggested for vdsm technologies.Article: 103131
Stephen Craven wrote: > Mr. Andraka (and others), > > I am curious as to how you specify a single logic-layer in these > high-speed designs. Do you explicitly specify the individual LUTs in > an HDL, or can you code at a higher level and synthesize down to > single-layer logic between flops? > > Thank you, > Stephen Craven > You can do it either way. For inferring code, you just have to pay attention to how many signals affect each flip-flop bit, and recode as necessary to keep that to the 4 inputs. It gets a little messier with clock enables and direct synchronous resets, as the synthesis tools tend to do with those what they like (the resets in Virtex-4, for example are dreadfully slow, so you want to keep the tool from using those, and in all cases you want to limit reset and ce inputs to registered signals). Managing the resets and clock enables in an inferred design often means using syn_keep directives to force a particular implementation. You can also use instantiated LUTs or use an xc_map attribute on a separate entity representing the LUT logic to get a LUT primitive that you can add RLOCs to.Article: 103132
John_H wrote: > Folks, > > Does anyone know if either Xilinx or Synplicity have provided a mechanism to > explicitly place an inferred LUT? > > I can produce LUTs that only feed a keep_buf but don't maintain the same LUT > name across compiles for RLOCing. I can guarantee the net name for Place & > route with the keep_buf but can't associate the net with the LUT's > placement. > > I'd love for the Xilinx tools to propagate a location constraint back to the > primitive that drives it since Synplicity hasn't come up with a nice way to > guarantee a net driver's name. > > Any help is appreciated, > - John_H > > John, no I haven't found a way to do this for inferred LUTs without making them a separate entity. If you keep your logic to 4 inputs, then the PAR software will generally place the LUT with the flip-flop, so you can usually get away with just placing the flip-flop and letting the inferred LUT follow it. For my commonly used IP blocks, I have a library of lut functions, each in its own entity. Synplicity lets you put an xc_map=LUT property on it that makes it into a LUT component. For example: --FMAP'd or2 library IEEE; use IEEE.std_logic_1164.all; entity fmap_or2 is port ( a, b : in std_logic; z : out std_logic); end fmap_or2; architecture rtl of fmap_or2 is attribute xc_map : STRING; attribute xc_map of rtl : architecture is "lut"; attribute syn_hier: string; attribute syn_hier of rtl:architecture is "hard"; begin z <= a or b; end rtl; produces a 2 input OR in a LUT. You can put an RLOC on the instantiation of this component, and it passes through the tools properly so that it winds up being a placed LUT. It obviously isn't as clean as putting z <= a or b; inline in your code, but it is still an RTL inference. Hope this helps.Article: 103133
mk wrote: > On Thu, 25 May 2006 20:47:59 -0400, Ray Andraka <ray@andraka.com> > wrote: > > >>jaxato@gmail.com wrote: >> >>>Hello PPL, >>> >>>I would like to know what are the current implementations for the >>>internal blocks inside a DSP48E. This of course applies to the new >>>Virtex-5 FPGA. How is Xilinx building, at RTL, the 25 X 18 multiplier >>>(is it a booth?) as well as the 48 X 48 adder blocks? >>> >>>Thanks for any help >>>Jacques >>> >> >> One hint to the internal construction lies in the fact that the V4 >>documentation tells you that the adder is a three input adder that >>performs the final add in the multiplier plus the C input. From that, >>you can infer a carry-save architecture (Booth is one possibility). Of >>course, you still don't know the exact details, but it does narrow it >>down considerably. > > > Forgive me if I don't understand but what does Booth have to do with > carry-save ? Booth is a partial product generation/reduction techique. > How you add the resulting partial products (carry-save, carry-select, > ripple) has nothing to do with it. Also you can do carry-save without > doing a booth encoding first. Actually there are some studies which > say that booth encoding is not suggested for vdsm technologies. Oops, My bad. I was thinking Wallace tree. Booth, as you correctly point out is a technique to reduce the number of partial products by recoding the sequence of 1 and 0 bits in the multiplicands. I don't know if Booth is used in the Xilinx multipliers or not.Article: 103134
Piotr Wyderski wrote: > Still without even the simplest free simulator? I use the free Icarus Simulator at: http://www.icarus.com/eda/verilog/ and I think it's great. Although it doesn't have a GUI interface, it's very simple and easy to use. I even use it in preference to the free simulators offered by some of the FPGA vendors, and have used it to develop a 2,000+ line Verilog program to implement the Elliptic Curve Factoring method an FPGA. RonArticle: 103135
rickman wrote: > I give my email address in order to get support and Xilinx feels the > need to send me spam. That's why I love Spamex.com because I can create an almost infinite number of different email addresses and disable or delete (or re-enable) any of them with a single click. I give each of my correspondents a unique email address and as soon as I get a single Spam email from that address I disable or delete it with a single click, and can also automatically create a different replacement email address if desired. Note: I am not affiliated with Spamex.com in any way. > I don't recall using this address, tektronix.drawing@arius.com, but I > don't know why I would be receiving spam from Analog Devices using it. Doesn't matter anymore because since you have posted that address to Usenet, it's toast and will be spammed mercilessly forever. ;-) RonArticle: 103136
Per Karlström wrote: > On 2006-05-16, Ray Andraka <ray@andraka.com> wrote: > >>Kevin Neilson wrote: >> >> >>>That's pretty impressive. How did you implement the carry-kill chain, >>>or whatever they call the ciruit that finds the location of the leading >>>'1'? This can be made with a carry chain, but I don't know if it would >>>work with a 2.5ns period. -Kevin >> >>A clever use of DSP48 and BRAM blocks. The fabric carry chain >>definitely won't reach 400MHz, especially with 30 bits. > > > Im just curious on how many pipeline-stages/clock-cycles it takes for > one sample to be processed. And also how many of these pipeline-stages > does the normalization use. > > \Per 128 clock pipeline for the 4/8/16 point FFT kernel. It accepts a complex sample on each clock cycle. The normalization is an 11 clock pipeline.Article: 103137
Any FPGA DIMM interface modules on the market today? This shounds interesting. --- PDTi [ http://www.productive-eda.com ] SpectaReg -- Spec-down code and doc generation for register mapsArticle: 103138
try ssh -XY... <antti.tyrvainen@luukku.com> wrote in message news:1148541826.862452.306430@j33g2000cwa.googlegroups.com... Hi! I'm running Quartus in remote Linux workstation and I use Cygwin X-server in my PC. If I use gnome desktop (xwin -query) Quartus opens nicely. But if I use a single X-terminal (ssh -X) to open Quartus it doesn't work. I receive an empty white Quartus splash screen. Option -no_splash doesn't help, then the main window is empty white. Any ideas? Antti Tyrväinen ElektrobitArticle: 103139
Hi I wanted to implement FFT in FPGA. I would like to do it using the CORDIC technique. Can anyone help to understand the technique. Matlab or C equivalent will be help ful rgds bijoyArticle: 103140
you can alway add a 1.5 USD MCU and 2 USD flash and have the config done over jtag :) AnttiArticle: 103141
you can add also: CORDIC Bibliography Site : http://web.archive.org/web/20001017173921/http://devil.ece.utexas.edu/Article: 103142
Ron wrote:
> You forgot to mention the price: $695 to $844 (depending on options).
> Prices are shown at: http://snipurl.com/qx87
>
> Ron
But you can evaluate the full version for 60 days before having to pay
anything. I ended up purchasing the program after those 60 days
though... I can't stress the usefulness of that sort of on-chip
debugging hard enough.
Marco, if you are talking about debugging of software running on the
embedded processors on the FPGA the gcc is available in EDK. It is not
very stable, but it works sometimes. Or if you have the time to wait for
debug prints to the terminal you can always add some
xil_printf("debug..."); to your c-code.
Take care!
Johan
--
-----------------------------------------------
Johan Bernspång, xjohbex@xfoix.se
Research engineer
Swedish Defence Research Agency - FOI
Division of Command & Control Systems
Department of Electronic Warfare Systems
www.foi.se
Please remove the x's in the email address if
replying to me personally.
-----------------------------------------------
Article: 103143Hi Brad, > Excellent! Felix, Thank you. I am glad to hear that this was helpful. > This code synthesizes to 26 slices on a V4. > Probably more if more I2C need to be sent. all I2C data are stored in a ROM (seq, seqT) which is probably 10 bits wide (i2cT) and as deep as your I2C sequence requires. In case you have longer sequences, you might want to check how this ROM is really synthesized. If the synthesizer does not infer the ROM properly, you might want to replace the command tag (i2cE) by a two-bit vector. > I needed to change only this clkdiv line to > help speed up a ModelSim simulate, > > -- signal clkdiv: unsigned(8 downto 0); > signal clkdiv: unsigned(1 downto 0); > > I'll change it back to adjust to my frequencies. the module was originally clocked by a 24 MHz clock. You might need to adjust it to your requirements. And of course: You will need to create your own I2C sequence. Please note that the module is cyclically repeating the pattern. This might or might not fit with your application. Best regards, Felix -- Dipl.-Ing. Felix Bertram http://www.bertram-family.com/felixArticle: 103144
Tim wrote: > The thin clients were activated by smart cards. When you had a problem you > could take your smart card to the guru down the corridor and show her the > exact screen with the problem on display. And when you wanted to work nearer > home for a few hours you could take the smart card to a local Sun facility > and pick up from exactly the point you left off. > We had those sorts of thin clients at uni for a while. I have never been using a more instable and slow system before nor after... The thought was good, but in reality when 100 students had a break at the same time and started Netscape simultaneously it sucked. Especially for us who tried to work on that system. I think I used the smartcard once or twice over a two year period of time... -- ----------------------------------------------- Johan Bernspång, xjohbex@xfoix.se Research engineer Swedish Defence Research Agency - FOI Division of Command & Control Systems Department of Electronic Warfare Systems www.foi.se Please remove the x's in the email address if replying to me personally. -----------------------------------------------Article: 103145
Hello, I'm trying to set PAL on adv7321, but the output signal is progressive timing mode. Does anybody know what is proper register setting (configuration) for interlaced mode (PAL or NTSC)? MarthaArticle: 103146
Matt Blanton <notreally@myemail.com> writes: > I managed to get around the issue by manually inserting copies of the > register containing the signal with the high fanout. This solves my initial > problem but unfortunately doesn't explain why setting the max fanout wasn't > working. Thanks to all that replied. > When flipflops get replicated by synthesis to reduce fanout, they get named by the tool in such a way as to make the mapper think they are part of a bus and then they get put in the same slice, never-more to be separated. This happens because they have anumber on the end of the original name. If you replicate by hand and name them _a, _b, etc this problem doesn't happen. Apprarantly even XST get's it wrong, and it should know better! Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.trw.com/conektArticle: 103147
Hi, Has anyone got experience using Celoxica Agility to synthesise SystemC? I haven't had much luck using version 1.0 (Build 4112) to generate VHDL. Problems include: - errors when assigning values to individual sc_bv elements (be it from boolean, int, char, or sc_logic). - difficulties with arrays of primitive types at class level (I converted my code to a mess of switch statements to avoid this). - failing to unroll a loop which assigned zeros to all elements of a small fixed-size boolean array. - fatal exceptions during synthesis. These problems arise with SystemC source that simulates OK. The errors seem fairly inconsistent, which makes me think that either Agility version 1.0 is still immature, or else my installation is broken somehow. I'd really appreciate it if someone could shed some light on this. Thanks! Bob.Article: 103148
Hi, I am using the VirtexII DCM in my design to generate the master clock for all the modules in my design. The input freq is 20.48 MHz and the output freq from DCM is 61.44 MHz. The "LOCKED" signal from DCM is AND'ed with the system reset and given as reset to all the modules in the design. When I generate the DCM using Coregen, there is a option "wait for DCM lock before DONE signal goes high" when I click the "Advanced" button. Can anyone clarify me what will happen if I dont check this option ? Will it affect the startup operation or the functioning of the FPGA after startup? What is the significance of this option? When I check this option, I am getting a message that I should specify a value for LCK_dll in the bitgen options. First of all, I am not finding any option on that name in bitgen. I felt that the "Release DLL" option maybe the LCK_dll option which the ISE tutorial refers to. Plz let me know whether I am correct. I also dont know what value I should enter for this LCK_dll option. How to decide on the number of clock cycles? Thanks & Regards, Srini.Article: 103149
On a sunny day (Fri, 26 May 2006 10:11:39 +1200) it happened Jim Granville <no.spam@designtools.co.nz> wrote in <44762b61$1@clear.net.nz>: >Jan Panteltje wrote: > >> >> Maybe you then simply pay for access time to the tools. >> Solves any update problem too. > >but just imagine the version control nightmares from that (shudder)....! Yes they will have to fix the tools, so version control only is needed for your code. Thus it will improve tool quality :-)
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Compare FPGA features and resources
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