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Messages from 103275

Article: 103275
Subject: Re: Power Up delay in FPGA !!!!!
From: Rene Tschaggelar <none@none.net>
Date: Tue, 30 May 2006 13:03:27 +0200
Links: << >>  << T >>  << A >>
jpvarkey@gmail.com wrote:

> Iam currently working on carbus project.I am really concerned with
> power delay factor in FPGA's especially Xilinx FPGA's .Will that create
> a problem for cardbus.Could somebody explain on, what all factors will
> affect the power up delay in SRAM based FPGA's.

The amount of bytes to be transferred from the
flash and their datarate.

Rene
-- 
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net

Article: 103276
Subject: Re: Power Up delay in FPGA !!!!!
From: "KJ" <kkjennings@sbcglobal.net>
Date: Tue, 30 May 2006 11:25:01 GMT
Links: << >>  << T >>  << A >>

> The amount of bytes to be transferred from the
> flash and their datarate.
>
As well as
- The delay prior to starting up the FPGA download.
- The delay after all of the data has been downloaded to the FPGA while 
you're waiting for the FPGA to switch into a 'user' mode (typically though 
this is pretty small).

KJ 



Article: 103277
Subject: generating IP cores
From: "Srikanth BJ" <bj.srikanth@gmail.com>
Date: 30 May 2006 04:44:45 -0700
Links: << >>  << T >>  << A >>
Hi,
       I've written the code for an application  using Xilinx 7.1 . Can
I create an IP core out of it?

Thanks and Regards,
Srikanth


Article: 103278
Subject: generating IP cores
From: "Srikanth BJ" <bj.srikanth@gmail.com>
Date: 30 May 2006 04:45:44 -0700
Links: << >>  << T >>  << A >>
Hi,
       I've written the code for an application  using Xilinx 7.1 . Is
it possible to I create an IP core out of it?

Thanks and Regards,
Srikanth


Article: 103279
Subject: Re: PCI Header types !!!
From: "colin" <colin_toogood@yahoo.com>
Date: 30 May 2006 04:58:12 -0700
Links: << >>  << T >>  << A >>
Three options

1) Download something from PLX or simillar. That will document what
they have done which is a good start.
2) Download PCISCOPE which is a software tool for looking at PCI
devices, the documentation may suffice.
3) Get hold of the spec (illegal) or a textbook.

colin

jpvarkey@gmail.com wrote:
> Could somebody give me the format of type 1 and type 2 configuration
> headers.


Article: 103280
Subject: Re: Mains pick-up on I/O pins
From: "Leon" <leon.heller@bulldoghome.com>
Date: 30 May 2006 05:10:00 -0700
Links: << >>  << T >>  << A >>
Try writing some very simple code (a few lines of VHDL) that just
drives an output high or low, and see if that works.

Leon


Article: 103281
Subject: Re: tft and uClinux
From: "Tushar Dongre" <dongre_tushar@rediffmail.com>
Date: Tue, 30 May 2006 05:18:21 -0700
Links: << >>  << T >>  << A >>
Dear Antti, I am new with EDK environment and want to interface with SDRAM, but when i add device SDRAM into my project my tool Xilinx EDK 7.1 doesn't include driver for SDRAM and also not including any API file for that, so please suggest some remedy for the same if possible

Article: 103282
Subject: Re: hard disk drivers problem
From: =?ISO-8859-1?Q?Michael_Sch=F6berl?= <MSchoeberl@mailtonne.de>
Date: Tue, 30 May 2006 14:18:48 +0200
Links: << >>  << T >>  << A >>
bjzhangwn schrieb:
> I am writing a interface about the ata interface but I have a problem
> that the dma request signal is sometimes always high when power up,and
> the hardware reset didn't work.

check your power-up sequence ...
the drive should go to a ready-state after delay and status-polling.
The procedure from the sepc just works fine for me and I never had an 
issue with *that* ...


bye,
Michael

Article: 103283
Subject: Re: generating IP cores
From: "Antti" <Antti.Lukats@xilant.com>
Date: 30 May 2006 05:29:32 -0700
Links: << >>  << T >>  << A >>
well what you have done already is an IP core,
so what is what you actually want todo?

a <= b or c;

the above as example is an IP core, in the matter of fact I have sold
such a IP core !

Antti


Article: 103284
Subject: Re: tft and uClinux
From: "Antti" <Antti.Lukats@xilant.com>
Date: 30 May 2006 05:46:31 -0700
Links: << >>  << T >>  << A >>
there is no driver needed
just access the memory with volatile pointer thats it

antti


Article: 103285
Subject: Re: Mains pick-up on I/O pins
From: "Gabor" <gabor@alacron.com>
Date: 30 May 2006 06:03:43 -0700
Links: << >>  << T >>  << A >>
It sounds to me like you're not getting a good ground return to
your scope.  If the board is powered by a "wall wart" supply it is
most likely isolated from third-wire ground.  If you have a ground
clip attached to the board, check to see that you're not also
seeing the 50 Hz when you probe the ground clip.  This could
indicate a bad connection to the probe ground return.

Good Luck,
Gabor

m_oylulan@hotmail.com wrote:
> Hello,
>
> I am trying to program an RC-100 demo board, which contains a
> Spartan-II chip. The board is supposed to send three logic outputs to
> external devices through I/O pins provided on an expansion header. I am
> pretty sure I've coded the program correctly (only to the extent that
> it works as intended in simulation), but when I probe the I/O pins with
> a scope all I'm getting is what I assume is mains pick-up (50 Hz
> ~5Vpk-pk).
>
> My probes have been calibrated; the probe and scope have adequate
> bandwidth (greater than 5x the signal bandwidth), and I get the same
> result whether I use the 'Auto-scale' function or manually set the
> 'Volts' and 'Time' division scales to the capture the expected
> waveforms. In the event that the source of the problem isn't my code,
> does anyone have any suggestions as to what I might be doing wrong?
> 
> Thanks,
> mees


Article: 103286
Subject: Re: Personalization of Xilinx ISE
From: "Gabor" <gabor@alacron.com>
Date: 30 May 2006 06:14:19 -0700
Links: << >>  << T >>  << A >>
As someone who regularly writes code for existing boards, I find it
annoying that ISE doesn't make it easier to find non-LOC'd I/O
pins.  I usually look first at the place&route report and check the
"number of LOCed IOBs" line to make sure it's 100%.  However there
is no translate option to report an error for non-LOCed I/O's.  Also
it's painful to browse through the pad report, which shows
the the status (LOCATED or not) of each IOB in a far right column
that is generally off-screen without scrolling.

Conversely I regularly need to set the (advanced) uption "Allow
unmatched LOC constraints" so I don't need to create a new
ucf file for each design on the same board.  I'd really rather
the unmatched LOC's be allowed (possibly with a warning) as
a default, and un-LOCed IOB's to be (optionally) flagged as an
error.  For anyone designing code for existing hardware, these
defaults make more sense.  Note that this includes anyone
using the Starter Kits, read inexperienced designers.

Just my 2 cents,
Gabor

Aurelian Lazarut wrote:
> you can create a script to check the pad report (from par)  to make sure
> pin locations and IO standards are correct for your particular demo design
> Aurash
>
> GaLaKtIkUs=99 wrote:
> > Hi all, Is there a method for personalization of ISE?
> > One of the personalizations:
> >       - For avoiding students to make errors in IOB proprties in UCF
> > files (the student's projects are for S3-Starter kit): is it possible
> > to add some step in the translate phase? I saw a perl interpreter
> > installed with ISE.
> >=20
> > Cheers
> >


Article: 103287
Subject: Re: Personalization of Xilinx ISE
From: Aurelian Lazarut <aurash@xilinx.com>
Date: Tue, 30 May 2006 14:38:20 +0100
Links: << >>  << T >>  << A >>
Hi Gabor,
why a non-locked pin should be considered an error?
if you want to constrain a pin to a location, the tools will (usually) 
obey, if you do not care by not adding a location constraint why the 
tools should care, or maybe you want a mechanism which will guess that 
you actually forgot an entry into your ucf.

Aurash


Gabor wrote:
> As someone who regularly writes code for existing boards, I find it
> annoying that ISE doesn't make it easier to find non-LOC'd I/O
> pins.  I usually look first at the place&route report and check the
> "number of LOCed IOBs" line to make sure it's 100%.  However there
> is no translate option to report an error for non-LOCed I/O's.
   Also
> it's painful to browse through the pad report, which shows
> the the status (LOCATED or not) of each IOB in a far right column
> that is generally off-screen without scrolling.
> 
> Conversely I regularly need to set the (advanced) uption "Allow
> unmatched LOC constraints" so I don't need to create a new
> ucf file for each design on the same board.  I'd really rather
> the unmatched LOC's be allowed (possibly with a warning) as
> a default, and un-LOCed IOB's to be (optionally) flagged as an
> error.  For anyone designing code for existing hardware, these
> defaults make more sense.  Note that this includes anyone
> using the Starter Kits, read inexperienced designers.
> 
> Just my 2 cents,
> Gabor
> 
> Aurelian Lazarut wrote:
> 
>>you can create a script to check the pad report (from par)  to make sure
>>pin locations and IO standards are correct for your particular demo design
>>Aurash
>>
>>GaLaKtIkUs™ wrote:
>>
>>>Hi all, Is there a method for personalization of ISE?
>>>One of the personalizations:
>>>      - For avoiding students to make errors in IOB proprties in UCF
>>>files (the student's projects are for S3-Starter kit): is it possible
>>>to add some step in the translate phase? I saw a perl interpreter
>>>installed with ISE.
>>>
>>>Cheers
>>
>>>
> 
> 
> 

Article: 103288
Subject: Re: generating IP cores
From: "Srikanth BJ" <bj.srikanth@gmail.com>
Date: 30 May 2006 07:01:27 -0700
Links: << >>  << T >>  << A >>

Antti wrote:
> well what you have done already is an IP core,
> so what is what you actually want todo?
>
> a <= b or c;
>
> the above as example is an IP core, in the matter of fact I have sold
> such a IP core !
>
> Antti

Take for example, FIFO or that sort of IP core from coregen. I want to
generate a similar stuff which packs instanciation template and
synthesize output file.

Thanks and Regards,
Srikanth


Article: 103289
Subject: Re: Personalization of Xilinx ISE
From: christopher.saunter@durham.ac.uk (c d saunter)
Date: Tue, 30 May 2006 14:07:04 +0000 (UTC)
Links: << >>  << T >>  << A >>
Aurelian Lazarut (aurash@xilinx.com) wrote:
: Hi Gabor,
: why a non-locked pin should be considered an error?
: if you want to constrain a pin to a location, the tools will (usually) 
: obey, if you do not care by not adding a location constraint why the 
: tools should care, or maybe you want a mechanism which will guess that 
: you actually forgot an entry into your ucf.

What'd be really nice would be for the tools to let the user specify the 
severity of a condition on a per project basis.  So for example a non 
LOCed IO could be flagged as 'no action', 'warning' or 'error'

Given how many spurious warnings are often kicked out by the tools, it'd 
be really usefull to have this as an integrated feature.

cds

Article: 103290
Subject: Re: Virtex-4 Gigabit Ethernet design
From: "David Q." <>
Date: Tue, 30 May 2006 07:08:27 -0700
Links: << >>  << T >>  << A >>
Hello

I just finished the test with the UC-II gigabit ethernet design for the ML403 board. Unfortunately, the design is very slow for high speed transmission. The main problem is the little quantity of memory for the code of the TCP/IP stack, so you need to optimize in space, and the instruction speed is decreased.

But for slow applications this is a great solution, because it's simply and easy to learn.

The next step? Hardware processing...

Regards

Article: 103291
Subject: Re: fpga uclinux, good starter board ?
From: "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk>
Date: Tue, 30 May 2006 15:32:42 +0100
Links: << >>  << T >>  << A >>
Well actually you can buy a single chip 4 Mbit RAM that will fit the DIL 
headers. There are solder bridges to facilitate that chip and others and 
there is one in Farnell last time I looked. A RAM module is also on it's way 
to if that is not enough. If you want more boot space then we can also 
accomodate a disk drive or MMC card with module add-on.

John Adair
Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan-3 Development 
Board.
http://www.enterpoint.co.uk


"Antti" <Antti.Lukats@xilant.com> wrote in message 
news:1148908918.240508.253910@j55g2000cwa.googlegroups.com...
> John,
>
> your boards are EXCELLENT for the money they cost but this time the OP
> asked for 'uclinux' ready boards.
>
> the requirement for uclinux is
>
> 1) xilinx FPGA S2-200 or larger, S3-1000 or larger preferred
> 2) 4MB RAM
> 3) some way to load boot image 2MB flash or some media load the image
> from
>
> Raggestone1 does not have a option with 4MB ram ASFAIK so its not an
> option for the OP
>
> Antti
> 



Article: 103292
Subject: Re: fpga uclinux, good starter board ?
From: "Antti" <Antti.Lukats@xilant.com>
Date: 30 May 2006 07:53:22 -0700
Links: << >>  << T >>  << A >>
John,

the requirement is 4 MBYTE RAM
not 4 mbit !!

there is no dil socketed 3.3V 4MBYTE ram modules available ASFAIK

Antti


Article: 103293
Subject: reverse from jedec to abel
From: "Ed" <edbroughton@yahoo.com>
Date: 30 May 2006 08:22:28 -0700
Links: << >>  << T >>  << A >>
 I have some very old jedecs for a 22v10 that I would like to back
compile into 
 abel logic equation files. Any ideas ? Thanks


Article: 103294
Subject: Re: PCI Header types !!!
From: "Brannon" <brannonking@yahoo.com>
Date: 30 May 2006 09:21:49 -0700
Links: << >>  << T >>  << A >>
> Google for pci local bus specification revision 2.2

google "pci23.pdf" 

it looks like it's the sixth link down


Article: 103295
Subject: OVERCOAT - FPGA Development Arrays
From: "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk>
Date: Tue, 30 May 2006 18:13:51 +0100
Links: << >>  << T >>  << A >>
For those that have asked about our Overcoat option to generate FPGA arrays 
there is now a page on our site at 
http://www.enterpoint.co.uk/moelbryn/overcoat.html showing the mechanics of 
how we do it. The array shown can operate either in a motherboard as shown 
or stand alone on the bench. Currently this a build to order option but we 
are looking at keeping some stock if there appears to be some demand.

John Adair
Enterpoint Ltd. - Home of Overcoat. FPGA Array Processing.
http://www.enterpoint.co.uk



Article: 103296
Subject: Re: Xilinx ML321 (v2pro rocket io): Adding PCIe functionality
From: "Eshwar" <ok@ok.com>
Date: Tue, 30 May 2006 14:24:12 -0400
Links: << >>  << T >>  << A >>
OK. But If I did manage to get hold of external clock recovery circuit, can 
the PCI SIG compliance board be used to add PCIe functionality to the FPGA 
development board (Xilinx PCIe Logicore will be used on the board) Are there 
any other cheaper alternatives like generic PCIe daughter cards, or other 
add in cards that can be used to connect the development board and a PC 
through PCIe?

Thanks,
Eshwar


"Antti" <Antti.Lukats@xilant.com> wrote in message 
news:1148584182.115716.17030@j33g2000cwa.googlegroups.com...
> V2pro rocket io is not PCIe compliant on the 'lock range' of the CDR so
> at least you need an external clock recovery circuit to be added - in
> short the answer is no, if you want PCIe functionality with Xilinx FPGA
> you should seek some other platform - as V2Pro is 2 families past the
> latest and greatest I dont think there will be any new things developed
> for it or for ML321 platform.
>
> Antti
> 



Article: 103297
Subject: Re: fpga debug
From: dalai lamah <antonio12358@hotmail.com>
Date: Tue, 30 May 2006 18:28:09 GMT
Links: << >>  << T >>  << A >>
Un bel giorno Falk Brunner digitò:

> In the real system, such 
> things are often not usefull, since the FPGA interacts in realtime with 
> external components (RAM, busses, whatever).

Since FPGA are static devices, it shouldn't be so hard to support
breakpoints by temporarily "disconnecting" the clocks, and watch/change the
"variables" through JTAG; if you can do partial reconfiguration, I suppose
you can also read/change the BRAM, registers and so on. Of course there are
asynchronous signals too, but even with normal software debug there are
asynchronous events you can't control.

-- 
asd

Article: 103298
Subject: Aurora sample design: Testing/Eye Diagrams
From: "billu" <bkamakot@gmail.com>
Date: 30 May 2006 11:43:27 -0700
Links: << >>  << T >>  << A >>
Hi All,

I have the following issues while trying to test a sample Aurora core.
I generated a core w/ the following specs:
HDL: Verilog, Lane: 1, Lane Width: 2, Interface: Streaming, Upper MGT
Clock: BREF_CLK, Upper MGT clock on GT_X0Y1 (from ucf file, corresponds
to MGT4 for a ML321 board)

After using xilperl to compile the design files, I simulated it using
Modelsim, and uploaded the bit file using Impact to the board.

I'm trying to test the core by feeding a 3.125Gbps (default data rate
based on onboard oscillator) PRBS signal onto MGT4(RXP & RXN). I test
the output signal from MGT4(TXP & TXN) by connecting it(TX ports)to a
oscilloscope and/or spectrum analyzer. Ideally, you would expect the
protocol to simply transmit that data that it received at the RX ports,
but the protocol fails to do that. I get an extremely weak signal on
the spectrum analyzer and bad eye on the scope. I also tried feeding in
a clock signal of 50MHz into BREF_CLK and testing the setup w/ 1Gbps
PRBS signal, but that didnt work either.

Can you tell me where I might be going wrong?

Thanks,
Billu


Article: 103299
Subject: Re: fpga debug
From: Falk Brunner <Falk.Brunner@gmx.de>
Date: Tue, 30 May 2006 20:46:44 +0200
Links: << >>  << T >>  << A >>
dalai lamah schrieb:

>>In the real system, such 
>>things are often not usefull, since the FPGA interacts in realtime with 
>>external components (RAM, busses, whatever).
> 
> 
> Since FPGA are static devices, it shouldn't be so hard to support
> breakpoints by temporarily "disconnecting" the clocks, and watch/change the

The problem is not the FPGA but the external components. Those are often 
not static, so this is no option.

> "variables" through JTAG; if you can do partial reconfiguration, I suppose
> you can also read/change the BRAM, registers and so on. Of course there are
> asynchronous signals too, but even with normal software debug there are
> asynchronous events you can't control.

The key word is real-time monitoring.

Regards
Falk



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