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Jim Granville wrote: > kulkarni.shailesh@gmail.com wrote: > > Hello, > > I have been working on a project and the submission date is > > due very soon. Now I am having some problems which need to be > > addressed. Here I go, > > > > I am using digilent Spartan 3 board for my project. My > > project needs to operate on the data sent by PC. I am using PCs > > parallel port to send and receive data. (I have a code written in C > > which uses outportb() and inportb() to exchange data. on the otherside > > in VHDL i have a data bus which is bi-directional.. inout... ) > > > > now the problem is the voltage levels these two operate at. FPGA > > operates at 3.3V and parallel port uses 5V to represent logic values... > > > > I saw a parallel I/O board (PIO1) on digilent website, but now have no > > time to order one... > > Series resistors ( wire between M-F DB25 as a cascade connector ) > should be good enough. Add clamp diodes if you like. > You only need microsecond region times, and probably do not care > about power loss. > > -jg If I remember correctly, I remember reading about connecting 3.3V CMOS configuration output signals to Xilinx 2.5V CMOS inputs and that was OK as long as the current limit (series resistor) limited the current to less than 10 mA. I think that was for Virtex II. I then remembered that the Spartan3 3.3V CMOS inputs are sensitive to overvoltage due to the 0.9 micron technology. There may be issues connecting 5 volt logic to Spartan3 3.3 volt inputs with series resistors. I think I remember someone saying that the IBIS model will tell you what the delta V of the input clamp diode will be at various input currents. Also consider that if the 3.3 V supply is lightly loaded, the 5 volt signals may have a sneak path through the assumed input clamp diodes and raise the 3.3 volt power supply above 3.3 volts. jg: Were the input clamp diodes to address the 0.9 micron issue, or the possible lack of an intrinsic input protection diode? - NewmanArticle: 101626
Nial- > ...after all the problems people have posted here I think > I might be better sticking to 7.1? Although known for a long time, In 8.1 these items are not fixed: -using a loop var with same name more than once (XST answer record 22625) -nested loops (XST answer record 22066) Another 7.1 issue was using @* 'wildcard' syntax in always block sensitivity list; this did not work in 7.1, but I've not heard yet if it works in 8.1. -JeffArticle: 101627
oops, it is not 0.9 micron but 90 nanometers. Shailesh: You might also double check to see that the parallel port accepts TTL level inputs and not regular 5 Volt HC input levels. -NewmanArticle: 101628
On Tue, 02 May 2006 13:52:43 +0000, Christopher Cole wrote: > The two versions of the Jungo windrvr drivers I was trying were: > > http://www.jungo.com/download/WD801LN.tgz > and > http://www.jungo.com/download/WD702LN.tgz > > Has anyone gotten these to compile under 2.6.16 or later? > Yes, it's quite a pain. I managed to tweak the Makefile to the 2.6.16 standard and get a working driver. I put it on a talk page of the Gentoo Wiki: http://gentoo-wiki.com/Talk:HOWTO_Xilinx The main article was very useful for me as well. > > Thanks, > -Chris No problem, DanArticle: 101629
Spartan is the low-cost FPGA product line, and thus more limited in size. Virtex -2 and Virtex-4 offer bigger sizes and higher speed (at higher cost) If the design does not fit, partition it into several chips, probably at minimal performance loss (if done right). Peter Alfke, XilinxArticle: 101630
I have to stick to parallel port!!!
@newman,
about connecting 3.3V to 5v parallel port(vice versa), can I use
some form of voltage dividers???
I need a configuration which is bi-directional..
Article: 101631This is very basic, remember the old masters; Ohm and Thevenin add FPGA datasheet EPP/ECP specification think...Article: 101632
kulkarni.shailesh@gmail.com wrote: > I have to stick to parallel port!!! > > @newman, > about connecting 3.3V to 5v parallel port(vice versa), can I use > some form of voltage dividers??? > I need a configuration which is bi-directional.. yes, but keep in mind a parallel port might use 3.3V output, so design it so it will work on 3.3V and 5V PPorts. -jgArticle: 101633
Hi, Does anyone have the circuit diagram for the voltage regulator on-board the XSA-50 board (manufactured by XESS )? If not, any ideas where one can find it ? Many thanks, ankyagArticle: 101634
Jeff Brower wrote: > Sam- > > This type of coding: > > assign data = hiZ ? 8'hzz : (buf1 ? buff_1 : 8'hzz); > assign data = hiZ ? 8'hzz : (buf2 ? buff_2 : 8'hzz); > > works Ok, it's just not implemented using actual internal tri-states. > Don't worry, tools handle it for you. ISE 7.1.04 may give warnings > about "the following tristate(s) are NOT replaced by logic..." and I > opened a webcase about that, but the word back is "just ignore". > > -Jeff > Thank you, However, in ISE8.1 ,it also gives warning "Inout dosenot connect". What should I do? Sam.Article: 101635
Robin Emery wrote: > Unfortunatly, I don't have access to ChipScope, so I cannot observe the > internal signals. You can evaluate ChipScope (full version) for free for 60 days without license. Just download it from the Xilinx website. Good luck. -- ----------------------------------------------- Johan Bernspång, xjohbex@xfoix.se Research engineer Swedish Defence Research Agency - FOI Division of Command & Control Systems Department of Electronic Warfare Systems www.foi.se Please remove the x's in the email address if replying to me personally. -----------------------------------------------Article: 101636
Jim Granville schrieb: > kulkarni.shailesh@gmail.com wrote: > >> I have to stick to parallel port!!! >> >> @newman, >> about connecting 3.3V to 5v parallel port(vice versa), can I use >> some form of voltage dividers??? >> I need a configuration which is bi-directional.. > > > yes, but keep in mind a parallel port might use 3.3V output, so > design it so it will work on 3.3V and 5V PPorts. The parallel port uses TTL levels. You must accept anything above 2.0V as high, and anything below 0.8V as low. Many parallel ports get very slow rise times above 1.6V, therefore the lower the threshold voltage the better. Using 2.5V CMOS IO on the FPGA with a series resistor to limit the 5V current should work fine with a threshold of 1.25V 3.3V CMOS IO gets you a threshold of 1.65V where the signals are dangerously flat allready. In that case you should add a schmitt trigger. You can build a schmitt trigger by using two FPGA pins per input. A resistor between the two pins and a resistor between one pin and the input allows you to feed back the received value to the input. Kolja SulimmaArticle: 101637
Did you simulate your VHDL description ? A functional simulation could shed some light on it, at least concerning functionality. Rgds AndreArticle: 101638
On Wed, 03 May 2006 18:10:15 -0700, Ron <News5@spamex.com> wrote: >Glory and riches are showered upon those who successfully factor one of >the RSA Challenge Numbers (see note [1]) ;-). I would like to be the >first to factor an RSA number using a standalone FPGA development >board(s) (ie; not connected to a conventional computer). > >The RSA Challenge numbers have traditionally been solved by networks of >supercomputers using a distributed Number Field Sieve (NFS) or similar >method. Sieving is unfortunately not suited to FPGA implementation, but >there is another integer factorization method called the Elliptic Curve >Method (ECM, see note [3]) that I think might stand a chance of cracking >RSA-704. I have therefore designed and tested a Verilog implementation >of ECM with a compile time bus-width specification (ie; `define L 704) >so that it's easy to determine how the LUT requirement increases as I >change the bus width. I've optimized the circuit for gate count to the >extent of multiplexing everything that is used more than once (multiply, >divide, modulo, etc) - a process that almost brought tears to my eyes at >one point, because I had to eliminate several areas that naturally lent >themselves to parallelization. > >Even so, the design requires far more LUTs than are currently available >from anyone as far as I know. I presently have Xilinx xc3s500e and Actel >ProASIC3E A3PE600 development boards, but I can't compile the design for >a 704 bit bus-width because I get the error message in Note [4] below (I >also get a similar message from the Actel synthesizer). I *can* compile >the design for a 384 bus-width however. Using a Xilinx 3s4000 as the >target device (even though I only have a 3s500) with a 384 bit >bus-width, I get the following Device utilization summary: > --------------------------- > Selected Device : 3s4000fg676-4 > Number of Slices: 49176 out of 27648 177% (*) > Number of Slice Flip Flops: 52253 out of 55296 94% > Number of 4 input LUTs: 83797 out of 55296 151% (*) > Number of bonded IOBs: 18 out of 489 3% > Number of GCLKs: 1 out of 8 12% > WARNING:Xst:1336 - (*) More than 100% of Device resources are used > --------------------------- > > >This would lead me to believe that my design would require at least >101,376 LUTs, and probably more depending on how much of the FPGA is >consumed by routing. Since the Xilinx 3s4000 has 55296 LUTs and 27648 >slices, I imagine a part with twice that number of slices & LUTs (a >Xilinx 3s8000 perhaps?) would be needed to fit my design. Anyone care to >hazard a guess as to if/when such a monster might be available? > >Also, thus far the longest number that has been factored with ECM is >only 66 decimal digits (see Note [3]). If RSA-704 (212 decimal digits) >were factored, it would set a new record for ECM factoring also. > >If such a device did become available, my only hope for acquiring the >requisite hardware/software would be to work out a deal with the FPGA >vendor or someone to lend me the necessary development board and s/w >tools in exchange for the potential fame and glory, since I am but a >humble retired engineer/hobbyist. :-) > >Ron > > >_________________ >Notes: > >[1] RSA Challenge Numbers: >http://www.rsasecurity.com/rsalabs/node.asp?id=2093 > >[2] Factoring Methods: >http://mathworld.wolfram.com/PrimeFactorizationAlgorithms.html > >[3] Elliptic Curve Factorization Method >http://mathworld.wolfram.com/EllipticCurveFactorizationMethod.html > >[4] When synthesizing ECM with a 704 bit bus-width for the Xilinx >xc3s4000-4fg676, I get: > >ERROR: Portability:3 - This Xilinx application has run out of memory or >has encountered a memory conflict. Current memory usage is 2092148 kb. > Memory problems may require a simple increase in available system >memory, or possibly a fix to the software or a special workaround. To >troubleshoot or remedy the problem, first: Try increasing your system's >RAM. Alternatively, you may try increasing your system's virtual memory >or swap space. If this does not fix the problem, please try the >following: Search the Answers Database at support.xilinx.com to locate >information on this error message. If neither of the above resources >produces an available solution, please use Web Support to open a case >with Xilinx Technical Support off of support.xilinx.com. As it is >likely that this may be an unforeseen problem, please be prepared to >submit relevant design files if necessary. >ERROR: XST failed >Process "Synthesize" did not complete. Maybe you should talk to XIlinx about lending you a devboard for one of their high-end chips, in return for some good publicity when you crack it..?Article: 101639
Hi group, Scenario: Multiple identical boards with a Virtex-II each all being fed the same clock signal which is being fed to a DCM on each device. Lets assume the clock signal has no skew between the FPGAs and all FPGAs get powered/configured at the same time (so the clock signals enter the DCMs in phase). Will the DCMs achieve lock at the same time and therefore produce output clocks that are in phase relative to each other on all 4 FPGAs? Or will the lock time vary? The datasheet says anything up to for example 120us (for 24-30MHz input, using DLL op) but does this mean a potential phase difference of 120us between the outputs of the DCMs? What about when multiplying/dividing or using the CLKFX outputs? Does that make a difference? Many thanks for your time, DaveArticle: 101640
"Colin Paul Gloster" <Colin_Paul_Gloster@ACM.org> schrieb im Newsbeitrag news:20060503210430.A70973@docenti.ing.unipi.it... > Of course implementing parallelism with real parallelism is easier, but > verifying something whether it is implemented with true parallelism or > interleaved sequential code should take the same effort no matter the > implementation: check whether the inputs and the outputs match. I still believe that verifying parallel structures on a PLD is easier than on a CPU. Imagine a program, that has to handle certain communication interfaces (CAN, RS232,..) and has to measure some real-time signals at the same time. In case of a PLD these modules could be checked separately, since no dependencies according to a single CPU are present. In case of a CPU based system this dependencies are crucial (in real-time systems) and a lot of test efford is spend to examine these.Article: 101641
Brad Smallridge wrote: > What are you writing out? And do you delay the write data? Hi Brad, Yes I delay the data. I solved the problem. For testing my controller on hardware I used RS232 controller + ChipScope VIO: I send some data from the PC, than using a VIO button I send data from the RS232 RX FIFO to memory and than I read back the memory and send to PC through RS232 TX. The problem was that there were latencies on RS232 controllers and I got wrong data.Article: 101642
Hi boys, good news!! The GSRD team will be release a new version of the GSRD using the MPMC2 at the end of May. I'm waiting that impatiently Best regardsArticle: 101643
Matt Blanton wrote: > I was hoping to avoid that because I am using a custom hardware module to > control plb bram controllers which write to the BRAMs. I assume moving to > the OPB will require a lot of changes to my hdl code and XPS project files, > but I may have to end up doing that if the number of slaves I have on the > PLB ends up being the problem. Thanks for the idea. plb_v34.pdf says the maximum number of slaves is 16. opb_v20.pdf says there is no maximum number of slaves, but Xilinx recommends 16. Perhaps you need a custom bram controller. Alan NishiokaArticle: 101644
Dave wrote: > Hi group, > > Scenario: Multiple identical boards with a Virtex-II each all being > fed the same clock signal which is being fed to a DCM on each device. > > Lets assume the clock signal has no skew between the FPGAs and all > FPGAs get powered/configured at the same time (so the clock signals > enter the DCMs in phase). > > Will the DCMs achieve lock at the same time and therefore produce > output clocks that are in phase relative to each other on all 4 FPGAs? > Or will the lock time vary? The datasheet says anything up to for > example 120us (for 24-30MHz input, using DLL op) but does this mean a > potential phase difference of 120us between the outputs of the DCMs? Don't count on them being equally fast to lock. There is no "in phase" in distributed systems, strictly speaking. The phase is the delay between clock cycles, so the max phase error is plus minus half the clock. You can synch multiple devices to within a clock cycle, provided the system is less distributed than a clockcycle is fast, with a trigger pulse. To achieve better synchronization, you need some hardware delay or PLL. Most highend FPGAs do have internal cClock PLLs. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 101645
> You'll probably have to resurrect an old system > slower/older than a pentium 166 to get it to work. Couldn't he use a dos emulator like DOSBox or something like that? That's what I do when I want to play some archaic PC game from back in the day... RobinArticle: 101646
There must be some dodgy code involved if it's taking the i/o out... "sam" <samxxxbah@yahoo.com> wrote in message news:44599e9a$0$27293$c3e8da3@news.astraweb.com... > Jeff Brower wrote: >> Sam- >> >> This type of coding: >> >> assign data = hiZ ? 8'hzz : (buf1 ? buff_1 : 8'hzz); >> assign data = hiZ ? 8'hzz : (buf2 ? buff_2 : 8'hzz); >> >> works Ok, it's just not implemented using actual internal tri-states. >> Don't worry, tools handle it for you. ISE 7.1.04 may give warnings >> about "the following tristate(s) are NOT replaced by logic..." and I >> opened a webcase about that, but the word back is "just ignore". >> >> -Jeff >> > Thank you, > However, in ISE8.1 ,it also gives warning "Inout dosenot connect". > What should I do? > Sam.Article: 101647
Hi:
I have added a page about a Cordic-based Sine Computer to
the MyHDL CookBook:
http://myhdl.jandecaluwe.com/doku.php/cookbook:sinecomp
This page demonstrates several features of the MyHDL to Verilog
convertor tool. In particular:
- it shows how the convertor takes care of the tricky issues
with negative numbers in Verilog automatically
- it shows how you can use non-synthesizable constructs in MyHDL
and still get synthesizable Verilog out of it :-) (Really!)
Regards,
Jan
--
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
From Python to silicon:
http://myhdl.jandecaluwe.com
Article: 101648Jan Decaluwe schrieb: > - it shows how you can use non-synthesizable constructs in MyHDL > and still get synthesizable Verilog out of it :-) (Really!) I heard a research talk on a GI workshop that talked about using simple XSLT translations to make common unsynthesizable VHDL code synthesizable. IMHO it is embarrassing that a 2006 compiler cannot synthesize if rising_edge(clk) and enable='1' then... Kolja SulimmaArticle: 101649
Mike Harrison wrote: > Maybe you should talk to XIlinx about lending you a devboard for one of their high-end chips, in > return for some good publicity when you crack it..? Exactly what I was thinking Mike. :-) What's frustrating is that although I could see spending a thousand or two thousand dollars for a development board, I simply cannot justify spending $2,495 of my retirement nest egg for the software tools alone. I wonder if Peter Alfke of Xilinx would care to comment on the possibility of my acquiring a loaner devboard and development s/w? I'm located in the San Gabriel Valley just North-West of Los Angeles. The email address I'm using (News5@spamex.com) is valid by the way, at least until it starts getting too much spam, and then I'll change it to News6, News7, etc. Some of the large computer software makers (MatLab, MapleSoft, etc) offer non-profit discounts for educational and personal non-commercial use. It would be wonderful if Xilinx (my favorite) or one of the other FPGA vendors would offer some sort of low cost alternative to me and those in my situation who would love to use your high end FPGAs, but cannot afford the cost of the s/w development tools. Thanks, Ron
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